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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 25/26] hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI
Date: Thu, 11 Jan 2018 13:38:21 +0000	[thread overview]
Message-ID: <1515677902-23436-26-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1515677902-23436-1-git-send-email-peter.maydell@linaro.org>

The GICv3 specification says that reserved register addresses
should RAZ/WI. This means we need to return MEMTX_OK, not MEMTX_ERROR,
because now that we support generating external aborts the
latter will cause an abort on new board models.

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1513183941-24300-2-git-send-email-peter.maydell@linaro.org
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
---
 hw/intc/arm_gicv3_dist.c       | 13 +++++++++++++
 hw/intc/arm_gicv3_its_common.c |  8 +++-----
 hw/intc/arm_gicv3_redist.c     | 13 +++++++++++++
 3 files changed, 29 insertions(+), 5 deletions(-)

diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
index 3ea3dd0..93fe936 100644
--- a/hw/intc/arm_gicv3_dist.c
+++ b/hw/intc/arm_gicv3_dist.c
@@ -817,6 +817,13 @@ MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data,
                       "%s: invalid guest read at offset " TARGET_FMT_plx
                       "size %u\n", __func__, offset, size);
         trace_gicv3_dist_badread(offset, size, attrs.secure);
+        /* The spec requires that reserved registers are RAZ/WI;
+         * so use MEMTX_ERROR returns from leaf functions as a way to
+         * trigger the guest-error logging but don't return it to
+         * the caller, or we'll cause a spurious guest data abort.
+         */
+        r = MEMTX_OK;
+        *data = 0;
     } else {
         trace_gicv3_dist_read(offset, *data, size, attrs.secure);
     }
@@ -852,6 +859,12 @@ MemTxResult gicv3_dist_write(void *opaque, hwaddr offset, uint64_t data,
                       "%s: invalid guest write at offset " TARGET_FMT_plx
                       "size %u\n", __func__, offset, size);
         trace_gicv3_dist_badwrite(offset, data, size, attrs.secure);
+        /* The spec requires that reserved registers are RAZ/WI;
+         * so use MEMTX_ERROR returns from leaf functions as a way to
+         * trigger the guest-error logging but don't return it to
+         * the caller, or we'll cause a spurious guest data abort.
+         */
+        r = MEMTX_OK;
     } else {
         trace_gicv3_dist_write(offset, data, size, attrs.secure);
     }
diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c
index 2bd2f0f..284c0a7 100644
--- a/hw/intc/arm_gicv3_its_common.c
+++ b/hw/intc/arm_gicv3_its_common.c
@@ -67,7 +67,8 @@ static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset,
                                         MemTxAttrs attrs)
 {
     qemu_log_mask(LOG_GUEST_ERROR, "ITS read at offset 0x%"PRIx64"\n", offset);
-    return MEMTX_ERROR;
+    *data = 0;
+    return MEMTX_OK;
 }
 
 static MemTxResult gicv3_its_trans_write(void *opaque, hwaddr offset,
@@ -82,15 +83,12 @@ static MemTxResult gicv3_its_trans_write(void *opaque, hwaddr offset,
         if (ret <= 0) {
             qemu_log_mask(LOG_GUEST_ERROR,
                           "ITS: Error sending MSI: %s\n", strerror(-ret));
-            return MEMTX_DECODE_ERROR;
         }
-
-        return MEMTX_OK;
     } else {
         qemu_log_mask(LOG_GUEST_ERROR,
                       "ITS write at bad offset 0x%"PRIx64"\n", offset);
-        return MEMTX_DECODE_ERROR;
     }
+    return MEMTX_OK;
 }
 
 static const MemoryRegionOps gicv3_its_trans_ops = {
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index 77e5cfa..8a8684d 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -455,6 +455,13 @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data,
                       "size %u\n", __func__, offset, size);
         trace_gicv3_redist_badread(gicv3_redist_affid(cs), offset,
                                    size, attrs.secure);
+        /* The spec requires that reserved registers are RAZ/WI;
+         * so use MEMTX_ERROR returns from leaf functions as a way to
+         * trigger the guest-error logging but don't return it to
+         * the caller, or we'll cause a spurious guest data abort.
+         */
+        r = MEMTX_OK;
+        *data = 0;
     } else {
         trace_gicv3_redist_read(gicv3_redist_affid(cs), offset, *data,
                                 size, attrs.secure);
@@ -505,6 +512,12 @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data,
                       "size %u\n", __func__, offset, size);
         trace_gicv3_redist_badwrite(gicv3_redist_affid(cs), offset, data,
                                     size, attrs.secure);
+        /* The spec requires that reserved registers are RAZ/WI;
+         * so use MEMTX_ERROR returns from leaf functions as a way to
+         * trigger the guest-error logging but don't return it to
+         * the caller, or we'll cause a spurious guest data abort.
+         */
+        r = MEMTX_OK;
     } else {
         trace_gicv3_redist_write(gicv3_redist_affid(cs), offset, data,
                                  size, attrs.secure);
-- 
2.7.4

  parent reply	other threads:[~2018-01-11 13:38 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-11 13:37 [Qemu-devel] [PULL 00/26] target-arm queue Peter Maydell
2018-01-11 13:37 ` [Qemu-devel] [PULL 01/26] linux-user: Add support for big-endian aarch64 Peter Maydell
2018-01-11 13:37 ` [Qemu-devel] [PULL 02/26] linux-user: Add separate aarch64_be uname Peter Maydell
2018-01-11 13:37 ` [Qemu-devel] [PULL 03/26] linux-user: Fix endianess of aarch64 signal trampoline Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 04/26] configure: Add aarch64_be-linux-user target Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 05/26] linux-user: Add aarch64_be magic numbers to qemu-binfmt-conf.sh Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 06/26] linux-user: Separate binfmt arm CPU families Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 07/26] linux-user: Activate armeb handler registration Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 08/26] target/arm: Fix stlxp for aarch64_be Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 09/26] Virt: ACPI: fix qemu assert due to re-assigned table data address Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 10/26] imx_fec: Do not link to netdev Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 11/26] imx_fec: Refactor imx_eth_enable_rx() Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 12/26] imx_fec: Change queue flushing heuristics Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 13/26] imx_fec: Move Tx frame buffer away from the stack Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 14/26] imx_fec: Use ENET_FTRL to determine truncation length Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 15/26] imx_fec: Use MIN instead of explicit ternary operator Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 16/26] imx_fec: Emulate SHIFT16 in ENETx_RACC Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 17/26] imx_fec: Add support for multiple Tx DMA rings Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 18/26] imx_fec: Use correct length for packet size Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 19/26] imx_fec: Fix a typo in imx_enet_receive() Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 20/26] imx_fec: Reserve full FSL_IMX25_FEC_SIZE page for the register file Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 21/26] hw/timer/pxa2xx_timer: replace hw_error() -> qemu_log_mask() Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 22/26] hw/sd/pxa2xx_mmci: add read/write() trace events Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 23/26] linux-user/arm/nwfpe: Check coprocessor number for FPA emulation Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 24/26] target/arm: Make disas_thumb2_insn() generate its own UNDEF exceptions Peter Maydell
2018-01-11 13:38 ` Peter Maydell [this message]
2018-01-11 13:38 ` [Qemu-devel] [PULL 26/26] hw/intc/arm_gic: reserved register addresses are RAZ/WI Peter Maydell
2018-01-11 14:19 ` [Qemu-devel] [PULL 00/26] target-arm queue no-reply
2018-01-11 15:24 ` Peter Maydell

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