From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Cc: Michael Clark <mjc@sifive.com>,
Palmer Dabbelt <palmer@sifive.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
RISC-V Patches <patches@groups.riscv.org>
Subject: [Qemu-devel] [PATCH v4 01/22] RISC-V Maintainers
Date: Mon, 5 Feb 2018 19:22:26 +1300 [thread overview]
Message-ID: <1517811767-75958-1-git-send-email-mjc@sifive.com> (raw)
Add Michael Clark, Palmer Dabbelt, Sagar Karandikar and Bastian
Koppelmann as RISC-V Maintainers.
Signed-off-by: Michael Clark <mjc@sifive.com>
---
MAINTAINERS | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0f952d4..d607039 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -210,6 +210,17 @@ F: hw/ppc/
F: include/hw/ppc/
F: disas/ppc.c
+RISC-V
+M: Michael Clark <mjc@sifive.com>
+M: Palmer Dabbelt <palmer@sifive.com>
+M: Sagar Karandikar <sagark@eecs.berkeley.edu>
+M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
+S: Maintained
+F: target/riscv/
+F: hw/riscv/
+F: include/hw/riscv/
+F: disas/riscv.c
+
S390
M: Richard Henderson <rth@twiddle.net>
M: Alexander Graf <agraf@suse.de>
--
2.7.0
next reply other threads:[~2018-02-05 6:24 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-05 6:22 Michael Clark [this message]
2018-02-05 6:22 ` [Qemu-devel] [PATCH v4 02/22] RISC-V ELF Machine Definition Michael Clark
2018-02-05 6:22 ` [Qemu-devel] [PATCH v4 03/22] RISC-V CPU Core Definition Michael Clark
2018-02-05 13:45 ` Richard Henderson
2018-02-05 22:15 ` Michael Clark
2018-02-05 15:04 ` Igor Mammedov
2018-02-05 22:09 ` Michael Clark
2018-02-06 15:03 ` Igor Mammedov
2018-02-08 2:19 ` Michael Clark
2018-02-08 10:28 ` Igor Mammedov
2018-02-05 6:22 ` [Qemu-devel] [PATCH v4 04/22] RISC-V Disassembler Michael Clark
2018-02-05 6:22 ` [Qemu-devel] [PATCH v4 05/22] RISC-V CPU Helpers Michael Clark
2018-02-05 13:55 ` Richard Henderson
2018-02-05 6:22 ` [Qemu-devel] [PATCH v4 06/22] RISC-V FPU Support Michael Clark
2018-02-05 14:01 ` Richard Henderson
2018-02-05 22:01 ` Michael Clark
2018-02-05 6:22 ` [Qemu-devel] [PATCH v4 07/22] RISC-V GDB Stub Michael Clark
2018-02-05 6:22 ` [Qemu-devel] [PATCH v4 08/22] RISC-V TCG Code Generation Michael Clark
2018-02-05 14:16 ` Richard Henderson
2018-02-05 6:22 ` [Qemu-devel] [PATCH v4 09/22] RISC-V Physical Memory Protection Michael Clark
2018-02-05 6:22 ` [Qemu-devel] [PATCH v4 10/22] RISC-V Linux User Emulation Michael Clark
2018-02-05 11:37 ` Andreas Schwab
2018-02-06 1:23 ` Michael Clark
2018-02-05 6:22 ` [Qemu-devel] [PATCH v4 11/22] RISC-V HTIF Console Michael Clark
2018-02-05 6:22 ` [Qemu-devel] [PATCH v4 12/22] RISC-V HART Array Michael Clark
2018-02-05 6:22 ` [Qemu-devel] [PATCH v4 13/22] SiFive RISC-V CLINT Block Michael Clark
2018-02-05 6:22 ` [Qemu-devel] [PATCH v4 14/22] SiFive RISC-V PLIC Block Michael Clark
2018-02-05 6:22 ` [Qemu-devel] [PATCH v4 15/22] RISC-V Spike Machines Michael Clark
2018-02-05 6:22 ` [Qemu-devel] [PATCH v4 16/22] RISC-V VirtIO Machine Michael Clark
2018-02-05 6:22 ` [Qemu-devel] [PATCH v4 17/22] SiFive RISC-V UART Device Michael Clark
2018-02-05 6:22 ` [Qemu-devel] [PATCH v4 18/22] SiFive RISC-V PRCI Block Michael Clark
2018-02-05 6:22 ` [Qemu-devel] [PATCH v4 19/22] SiFive RISC-V Test Finisher Michael Clark
2018-02-05 6:22 ` [Qemu-devel] [PATCH v4 20/22] SiFive Freedom E300 RISC-V Machine Michael Clark
2018-02-05 6:22 ` [Qemu-devel] [PATCH v4 21/22] SiFive Freedom U500 " Michael Clark
2018-02-05 6:22 ` [Qemu-devel] [PATCH v4 22/22] RISC-V Build Infrastructure Michael Clark
2018-02-05 14:19 ` Richard Henderson
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