* [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support
@ 2018-02-05 13:39 Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 01/14] hw/arm/smmu-common: smmu base device and datatypes Eric Auger
` (14 more replies)
0 siblings, 15 replies; 18+ messages in thread
From: Eric Auger @ 2018-02-05 13:39 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, peter.maydell, qemu-arm, qemu-devel,
prem.mallappa, alex.williamson
Cc: tn, mst, christoffer.dall, bharat.bhushan, jean-philippe.brucker,
edgar.iglesias, linuc.decode, peterx
This series implements the emulation code for ARM SMMUv3.
SMMUv3 gets instantiated by adding ",iommu=smmuv3" to the virt
machine option.
VHOST integration will be handled in a separate series. VFIO
integration is not targeted at the moment. Only stage 1 and
AArch64 page table walk are supported.
Main changes since v7:
I Took into account Peter's comments:
- revisit queue data structures
- use registerfields.h and got rid of reg array
- use dma_memory_read for all descriptor fetches
- got rid of page table walk for an iova range and
implemented standard page table walk for single IOVA
- revisit event data structure
- report events in many more situations and pass the event
handle all along the decode and ptw phases
- fix gerror/gerron computations
- completely got rid of stage2 decoding
- use a machine option for instantiation
- get rid of VFIO integration
- get rid of VHOST integration (this will be added in a
- abort in case vhost/vfio notifiers get detected
second step together with TLB emulation)
- Tested migration
- fixed TTBR index computation (issue reported by Tomasz)
Best Regards
Eric
This series can be found at:
v8: https://github.com/eauger/qemu/tree/v2.11.0-SMMU-v8
Previous version at:
v7: https://github.com/eauger/qemu/tree/v2.10.0-SMMU-v7
History:
v7 -> v8:
- see above and individual patch change log
v6 -> v7:
- DPDK testpmd now running on guest with 2 assigned VFs
- Changed the instantiation method: add the following option to
the QEMU command line
-device smmu # for virtio/vhost use cases
-device smmu,caching-mode # for vfio use cases (based on [1])
- splitted the series into smaller patches to allow the review
- the VFIO integration based on "ltlbi-on-map" smmuv3 driver
is isolated from the rest: last 2 patches, not for upstream.
This is shipped for testing/bench until a better solution is found.
- Reworked permission flag checks and event generation
v5 -> v6:
- Rebase on 2.10 and IOMMUMemoryRegion
- add ACPI TLBI_ON_MAP support (VFIO integration also works in
ACPI mode)
- fix block replay
- handle implementation defined SMMU_CMD_TLBI_NH_VA_AM cmd
(goes along with TLBI_ON_MAP FW quirk)
- replay systematically unmap the whole range first
- smmuv3_map_hook does not unmap anymore and the unmap is done
before the replay
- add and use smmuv3_context_device_invalidate instead of
blindly replaying everything
v4 -> v5:
- initial_level now part of SMMUTransCfg
- smmu_page_walk_64 takes into account the max input size
- implement sys->iommu_ops.replay and sys->iommu_ops.notify_flag_changed
- smmuv3_translate: bug fix: don't walk on bypass
- smmu_update_qreg: fix PROD index update
- I did not yet address Peter's comments as the code is not mature enough
to be split into sub patches.
v3 -> v4 [Eric]:
- page table walk rewritten to allow scan of the page table within a
range of IOVA. This prepares for VFIO integration and replay.
- configuration parsing partially reworked.
- do not advertise unsupported/untested features: S2, S1 + S2, HYP,
PRI, ATS, ..
- added ACPI table generation
- migrated to dynamic traces
- mingw compilation fix
v2 -> v3 [Eric]:
- rebased on 2.9
- mostly code and patch reorganization to ease the review process
- optional patches removed. They may be handled separately. I am currently
working on ACPI enablement.
- optional instantiation of the smmu in mach-virt
- removed [2/9] (fdt functions) since not mandated
- start splitting main patch into base and derived object
- no new function feature added
v1 -> v2 [Prem]:
- Adopted review comments from Eric Auger
- Make SMMU_DPRINTF to internally call qemu_log
(since translation requests are too many, we need control
on the type of log we want)
- SMMUTransCfg modified to suite simplicity
- Change RegInfo to uint64 register array
- Code cleanup
- Test cleanups
- Reshuffled patches
v0 -> v1 [Prem]:
- As per SMMUv3 spec 16.0 (only is_ste_consistant() is noticeable)
- Reworked register access/update logic
- Factored out translation code for
- single point bug fix
- sharing/removal in future
- (optional) Unit tests added, with PCI test device
- S1 with 4k/64k, S1+S2 with 4k/64k
- (S1 or S2) only can be verified by Linux 4.7 driver
- (optional) Priliminary ACPI support
v0 [Prem]:
- Implements SMMUv3 spec 11.0
- Supported for PCIe devices,
- Command Queue and Event Queue supported
- LPAE only, S1 is supported and Tested, S2 not tested
- BE mode Translation not supported
- IRQ support (legacy, no MSI)
- Tested with DPDK and e1000
Eric Auger (11):
hw/arm/smmu-common: smmu base device and datatypes
hw/arm/smmu-common: IOMMU memory region and address space setup
hw/arm/smmu-common: VMSAv8-64 page table walk
hw/arm/smmuv3: Wired IRQ and GERROR helpers
hw/arm/smmuv3: Queue helpers
hw/arm/smmuv3: Implement MMIO write operations
hw/arm/smmuv3: Event queue recording helper
hw/arm/smmuv3: Implement translate callback
hw/arm/smmuv3: Abort on vfio or vhost case
target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route
hw/arm/virt: Handle iommu in 2.12 machine type
Prem Mallappa (3):
hw/arm/smmuv3: Skeleton
hw/arm/virt: Add SMMUv3 to the virt board
hw/arm/virt-acpi-build: Add smmuv3 node in IORT table
default-configs/aarch64-softmmu.mak | 1 +
hw/arm/Makefile.objs | 1 +
hw/arm/smmu-common.c | 352 ++++++++++++
hw/arm/smmu-internal.h | 104 ++++
hw/arm/smmuv3-internal.h | 599 +++++++++++++++++++
hw/arm/smmuv3.c | 1088 +++++++++++++++++++++++++++++++++++
hw/arm/trace-events | 38 ++
hw/arm/virt-acpi-build.c | 56 +-
hw/arm/virt.c | 109 +++-
include/hw/acpi/acpi-defs.h | 15 +
include/hw/arm/smmu-common.h | 138 +++++
include/hw/arm/smmuv3.h | 91 +++
include/hw/arm/virt.h | 11 +
target/arm/kvm.c | 27 +
target/arm/trace-events | 3 +
15 files changed, 2625 insertions(+), 8 deletions(-)
create mode 100644 hw/arm/smmu-common.c
create mode 100644 hw/arm/smmu-internal.h
create mode 100644 hw/arm/smmuv3-internal.h
create mode 100644 hw/arm/smmuv3.c
create mode 100644 include/hw/arm/smmu-common.h
create mode 100644 include/hw/arm/smmuv3.h
--
2.5.5
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v8 01/14] hw/arm/smmu-common: smmu base device and datatypes
2018-02-05 13:39 [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support Eric Auger
@ 2018-02-05 13:39 ` Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 02/14] hw/arm/smmu-common: IOMMU memory region and address space setup Eric Auger
` (13 subsequent siblings)
14 siblings, 0 replies; 18+ messages in thread
From: Eric Auger @ 2018-02-05 13:39 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, peter.maydell, qemu-arm, qemu-devel,
prem.mallappa, alex.williamson
Cc: tn, mst, christoffer.dall, bharat.bhushan, jean-philippe.brucker,
edgar.iglesias, linuc.decode, peterx
The patch introduces the smmu base device and class for the ARM
smmu. Devices for specific versions will be derived from this
base device.
We also introduce some important datatypes.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com>
---
v7 -> v8:
- add bus_num property
- add primary-bus property
- add realize and remove instance_init
- rename TYPE and related macros to match naming convention using
for GIC
- add SMMUPageTableWalkEventInfo
- tt[2] in translation config
v3 -> v4:
- added smmu_find_as_from_bus_num
- SMMU_PCI_BUS_MAX and SMMU_PCI_DEVFN_MAX in smmu-common header
- new fields in SMMUState:
- iommu_ops, smmu_as_by_busptr, smmu_as_by_bus_num
- add aa64[] field in SMMUTransCfg
v3:
- moved the base code in a separate patch to ease the review.
- clearer separation between base class and smmuv3 class
- translate_* only implemented as class methods
Conflicts:
default-configs/aarch64-softmmu.mak
---
default-configs/aarch64-softmmu.mak | 1 +
hw/arm/Makefile.objs | 1 +
hw/arm/smmu-common.c | 71 ++++++++++++++++++++
include/hw/arm/smmu-common.h | 126 ++++++++++++++++++++++++++++++++++++
4 files changed, 199 insertions(+)
create mode 100644 hw/arm/smmu-common.c
create mode 100644 include/hw/arm/smmu-common.h
diff --git a/default-configs/aarch64-softmmu.mak b/default-configs/aarch64-softmmu.mak
index 9ddccf8..6f790f0 100644
--- a/default-configs/aarch64-softmmu.mak
+++ b/default-configs/aarch64-softmmu.mak
@@ -8,3 +8,4 @@ CONFIG_DDC=y
CONFIG_DPCD=y
CONFIG_XLNX_ZYNQMP=y
CONFIG_XLNX_ZYNQMP_ARM=y
+CONFIG_ARM_SMMUV3=y
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 1c896ba..c84c5ac 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -20,3 +20,4 @@ obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
obj-$(CONFIG_MPS2) += mps2.o
obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o
+obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
new file mode 100644
index 0000000..c2f6b15
--- /dev/null
+++ b/hw/arm/smmu-common.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2014-2016 Broadcom Corporation
+ * Copyright (c) 2017 Red Hat, Inc.
+ * Written by Prem Mallappa, Eric Auger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Author: Prem Mallappa <pmallapp@broadcom.com>
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "sysemu/sysemu.h"
+#include "exec/address-spaces.h"
+#include "trace.h"
+#include "exec/target_page.h"
+#include "qom/cpu.h"
+#include "hw/qdev-properties.h"
+#include "qapi/error.h"
+
+#include "qemu/error-report.h"
+#include "hw/arm/smmu-common.h"
+
+static void smmu_base_realize(DeviceState *dev, Error **errp)
+{
+}
+
+static Property smmu_dev_properties[] = {
+ DEFINE_PROP_UINT8("bus_num", SMMUState, bus_num, 0),
+ DEFINE_PROP_LINK("primary-bus", SMMUState, primary_bus, "PCI", PCIBus *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void smmu_base_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SMMUBaseClass *sbc = ARM_SMMU_CLASS(klass);
+
+ dc->props = smmu_dev_properties;
+ sbc->parent_realize = dc->realize;
+ dc->realize = smmu_base_realize;
+}
+
+static const TypeInfo smmu_base_info = {
+ .name = TYPE_ARM_SMMU,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(SMMUState),
+ .class_data = NULL,
+ .class_size = sizeof(SMMUBaseClass),
+ .class_init = smmu_base_class_init,
+ .abstract = true,
+};
+
+static void smmu_base_register_types(void)
+{
+ type_register_static(&smmu_base_info);
+}
+
+type_init(smmu_base_register_types)
+
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
new file mode 100644
index 0000000..0f9af40
--- /dev/null
+++ b/include/hw/arm/smmu-common.h
@@ -0,0 +1,126 @@
+/*
+ * ARM SMMU Support
+ *
+ * Copyright (C) 2015-2016 Broadcom Corporation
+ * Copyright (c) 2017 Red Hat, Inc.
+ * Written by Prem Mallappa, Eric Auger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_ARM_SMMU_COMMON_H
+#define HW_ARM_SMMU_COMMON_H
+
+#include <hw/sysbus.h>
+#include "hw/pci/pci.h"
+
+#define SMMU_PCI_BUS_MAX 256
+#define SMMU_PCI_DEVFN_MAX 256
+
+#define SMMU_MAX_VA_BITS 48
+
+/*
+ * Page table walk error types
+ */
+typedef enum {
+ SMMU_PTW_ERR_NONE,
+ SMMU_PTW_ERR_WALK_EABT, /* Translation walk external abort */
+ SMMU_PTW_ERR_TRANSLATION, /* Translation fault */
+ SMMU_PTW_ERR_ADDR_SIZE, /* Address Size fault */
+ SMMU_PTW_ERR_ACCESS, /* Access fault */
+ SMMU_PTW_ERR_PERMISSION, /* Permission fault */
+} SMMUPTWEventType;
+
+typedef struct SMMUPTWEventInfo {
+ SMMUPTWEventType type;
+ dma_addr_t addr; /* fetched address that induced an abort, if any */
+} SMMUPTWEventInfo;
+
+typedef struct SMMUTransTableInfo {
+ bool disabled; /* is the translation table disabled? */
+ uint64_t ttb; /* TT base address */
+ uint8_t tsz; /* input range, ie. 2^(64 -tsz)*/
+ uint8_t granule_sz; /* granule page shift */
+ uint8_t initial_level; /* initial lookup level */
+} SMMUTransTableInfo;
+
+/*
+ * Generic structure populated by derived SMMU devices
+ * after decoding the configuration information and used as
+ * input to the page table walk
+ */
+typedef struct SMMUTransCfg {
+ int stage; /* translation stage */
+ bool aa64; /* arch64 or aarch32 translation table */
+ bool disabled; /* smmu is disabled */
+ bool bypassed; /* translation is bypassed */
+ bool aborted; /* translation is aborted */
+ uint64_t ttb; /* TT base address */
+ uint8_t oas; /* output address width */
+ uint8_t tbi; /* Top Byte Ignore */
+ SMMUTransTableInfo tt[2];
+} SMMUTransCfg;
+
+typedef struct SMMUDevice {
+ void *smmu;
+ PCIBus *bus;
+ int devfn;
+ IOMMUMemoryRegion iommu;
+ AddressSpace as;
+} SMMUDevice;
+
+typedef struct SMMUNotifierNode {
+ SMMUDevice *sdev;
+ QLIST_ENTRY(SMMUNotifierNode) next;
+} SMMUNotifierNode;
+
+typedef struct SMMUPciBus {
+ PCIBus *bus;
+ SMMUDevice *pbdev[0]; /* Parent array is sparse, so dynamically alloc */
+} SMMUPciBus;
+
+typedef struct SMMUState {
+ /* <private> */
+ SysBusDevice dev;
+ char *mrtypename;
+ MemoryRegion iomem;
+
+ GHashTable *smmu_as_by_busptr;
+ SMMUPciBus *smmu_as_by_bus_num[SMMU_PCI_BUS_MAX];
+ PCIBus *pci_bus;
+ QLIST_HEAD(, SMMUNotifierNode) notifiers_list;
+ uint8_t bus_num;
+ PCIBus *primary_bus;
+} SMMUState;
+
+typedef int (*smmu_page_walk_hook)(IOMMUTLBEntry *entry, void *private);
+
+typedef struct {
+ /* <private> */
+ SysBusDeviceClass parent_class;
+
+ /*< public >*/
+
+ DeviceRealize parent_realize;
+
+} SMMUBaseClass;
+
+#define TYPE_ARM_SMMU "arm-smmu"
+#define ARM_SMMU(obj) OBJECT_CHECK(SMMUState, (obj), TYPE_ARM_SMMU)
+#define ARM_SMMU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(SMMUBaseClass, (klass), TYPE_ARM_SMMU)
+#define ARM_SMMU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(SMMUBaseClass, (obj), TYPE_ARm_SMMU)
+
+#endif /* HW_ARM_SMMU_COMMON */
--
2.5.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v8 02/14] hw/arm/smmu-common: IOMMU memory region and address space setup
2018-02-05 13:39 [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 01/14] hw/arm/smmu-common: smmu base device and datatypes Eric Auger
@ 2018-02-05 13:39 ` Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 03/14] hw/arm/smmu-common: VMSAv8-64 page table walk Eric Auger
` (12 subsequent siblings)
14 siblings, 0 replies; 18+ messages in thread
From: Eric Auger @ 2018-02-05 13:39 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, peter.maydell, qemu-arm, qemu-devel,
prem.mallappa, alex.williamson
Cc: tn, mst, christoffer.dall, bharat.bhushan, jean-philippe.brucker,
edgar.iglesias, linuc.decode, peterx
We enumerate all the PCI devices attached to the SMMU and
initialize an associated IOMMU memory region and address space.
This happens on SMMU base instance init.
Those info are stored in SMMUDevice objects. The devices are
grouped according to the PCIBus they belong to. A hash table
indexed by the PCIBus poinet is used. Also an array indexed by
the bus number allows to find the list of SMMUDevices.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v7 -> v8:
- introduce SMMU_MAX_VA_BITS
- use PCI bus handle as a key
- do not clear s->smmu_as_by_bus_num
- use g_new0 instead of g_malloc0
- use primary_bus field
---
hw/arm/smmu-common.c | 61 ++++++++++++++++++++++++++++++++++++++++++++
include/hw/arm/smmu-common.h | 6 +++++
2 files changed, 67 insertions(+)
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index c2f6b15..7bf8e57 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -32,8 +32,69 @@
#include "qemu/error-report.h"
#include "hw/arm/smmu-common.h"
+SMMUPciBus *smmu_find_as_from_bus_num(SMMUState *s, uint8_t bus_num)
+{
+ SMMUPciBus *smmu_pci_bus = s->smmu_as_by_bus_num[bus_num];
+
+ if (!smmu_pci_bus) {
+ GHashTableIter iter;
+
+ g_hash_table_iter_init(&iter, s->smmu_as_by_busptr);
+ while (g_hash_table_iter_next(&iter, NULL, (void **)&smmu_pci_bus)) {
+ if (pci_bus_num(smmu_pci_bus->bus) == bus_num) {
+ s->smmu_as_by_bus_num[bus_num] = smmu_pci_bus;
+ return smmu_pci_bus;
+ }
+ }
+ }
+ return smmu_pci_bus;
+}
+
+static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn)
+{
+ SMMUState *s = opaque;
+ SMMUPciBus *sbus = g_hash_table_lookup(s->smmu_as_by_busptr, &bus);
+ SMMUDevice *sdev;
+
+ if (!sbus) {
+ sbus = g_malloc0(sizeof(SMMUPciBus) +
+ sizeof(SMMUDevice *) * SMMU_PCI_DEVFN_MAX);
+ sbus->bus = bus;
+ g_hash_table_insert(s->smmu_as_by_busptr, bus, sbus);
+ }
+
+ sdev = sbus->pbdev[devfn];
+ if (!sdev) {
+ char *name = g_strdup_printf("%s-%d-%d",
+ s->mrtypename,
+ pci_bus_num(bus), devfn);
+ sdev = sbus->pbdev[devfn] = g_new0(SMMUDevice, 1);
+
+ sdev->smmu = s;
+ sdev->bus = bus;
+ sdev->devfn = devfn;
+
+ memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu),
+ s->mrtypename,
+ OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS);
+ address_space_init(&sdev->as,
+ MEMORY_REGION(&sdev->iommu), name);
+ }
+
+ return &sdev->as;
+}
+
static void smmu_base_realize(DeviceState *dev, Error **errp)
{
+ SMMUState *s = ARM_SMMU(dev);
+
+ s->smmu_as_by_busptr = g_hash_table_new(NULL, NULL);
+
+ if (s->primary_bus) {
+ pci_setup_iommu(s->primary_bus, smmu_find_add_as, s);
+ } else {
+ error_setg(errp, "SMMU is not attached to any PCI bus!");
+ }
}
static Property smmu_dev_properties[] = {
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index 0f9af40..1495bce 100644
--- a/include/hw/arm/smmu-common.h
+++ b/include/hw/arm/smmu-common.h
@@ -123,4 +123,10 @@ typedef struct {
#define ARM_SMMU_GET_CLASS(obj) \
OBJECT_GET_CLASS(SMMUBaseClass, (obj), TYPE_ARm_SMMU)
+SMMUPciBus *smmu_find_as_from_bus_num(SMMUState *s, uint8_t bus_num);
+
+static inline uint16_t smmu_get_sid(SMMUDevice *sdev)
+{
+ return ((pci_bus_num(sdev->bus) & 0xff) << 8) | sdev->devfn;
+}
#endif /* HW_ARM_SMMU_COMMON */
--
2.5.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v8 03/14] hw/arm/smmu-common: VMSAv8-64 page table walk
2018-02-05 13:39 [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 01/14] hw/arm/smmu-common: smmu base device and datatypes Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 02/14] hw/arm/smmu-common: IOMMU memory region and address space setup Eric Auger
@ 2018-02-05 13:39 ` Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 04/14] hw/arm/smmuv3: Skeleton Eric Auger
` (11 subsequent siblings)
14 siblings, 0 replies; 18+ messages in thread
From: Eric Auger @ 2018-02-05 13:39 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, peter.maydell, qemu-arm, qemu-devel,
prem.mallappa, alex.williamson
Cc: tn, mst, christoffer.dall, bharat.bhushan, jean-philippe.brucker,
edgar.iglesias, linuc.decode, peterx
This patch implements the page table walk for VMSAv8-64.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v7 -> v8:
- rework get_pte
- use LOG_LEVEL_ERROR
- remove error checking in get_block_pte_address
- page table walk simplified (no VFIO replay anymore)
- handle PTW error events
- use dma_memory_read
v6 -> v7:
- fix wrong error handling in walk_page_table
- check perm in smmu_translate
v5 -> v6:
- use IOMMUMemoryRegion
- remove initial_lookup_level()
- fix block replay
v4 -> v5:
- add initial level in translation config
- implement block pte
- rename must_translate into nofail
- introduce call_entry_hook
- small changes to dynamic traces
- smmu_page_walk code moved from smmuv3.c to this file
- remove smmu_translate*
v3 -> v4:
- reworked page table walk to prepare for VFIO integration
(capability to scan a range of IOVA). Same function is used
for translate for a single iova. This is largely inspired
from intel_iommu.c
- as the translate function was not straightforward to me,
I tried to stick more closely to the VMSA spec.
- remove support of nested stage (kernel driver does not
support it anyway)
- use error_report and trace events
- add aa64[] field in SMMUTransCfg
---
hw/arm/smmu-common.c | 220 +++++++++++++++++++++++++++++++++++++++++++
hw/arm/smmu-internal.h | 104 ++++++++++++++++++++
hw/arm/trace-events | 12 +++
include/hw/arm/smmu-common.h | 6 ++
4 files changed, 342 insertions(+)
create mode 100644 hw/arm/smmu-internal.h
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index 7bf8e57..cb1855f 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -31,6 +31,226 @@
#include "qemu/error-report.h"
#include "hw/arm/smmu-common.h"
+#include "smmu-internal.h"
+
+/* VMSAv8-64 Translation */
+
+/**
+ * get_pte - Get the content of a page table entry located t
+ * @base_addr[@index]
+ */
+static int get_pte(dma_addr_t baseaddr, uint32_t index, uint64_t *pte,
+ SMMUPTWEventInfo *info)
+{
+ int ret;
+ dma_addr_t addr = baseaddr + index * sizeof(*pte);
+
+ ret = dma_memory_read(&address_space_memory, addr,
+ (uint8_t *)pte, sizeof(*pte));
+
+ if (ret != MEMTX_OK) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Cannot fetch pte at address=0x%"PRIx64"\n", addr);
+ info->type = SMMU_PTW_ERR_WALK_EABT;
+ info->addr = addr;
+ return -EINVAL;
+ }
+ trace_smmu_get_pte(baseaddr, index, addr, *pte);
+ return 0;
+}
+
+/* VMSAv8-64 Translation Table Format Descriptor Decoding */
+
+#define PTE_ADDRESS(pte, shift) (extract64(pte, shift, 47 - shift) << shift)
+
+/**
+ * get_page_pte_address - returns the L3 descriptor output address,
+ * ie. the page frame
+ * ARM ARM spec: Figure D4-17 VMSAv8-64 level 3 descriptor format
+ */
+static inline hwaddr get_page_pte_address(uint64_t pte, int granule_sz)
+{
+ return PTE_ADDRESS(pte, granule_sz);
+}
+
+/**
+ * get_table_pte_address - return table descriptor output address,
+ * ie. address of next level table
+ * ARM ARM Figure D4-16 VMSAv8-64 level0, level1, and level 2 descriptor formats
+ */
+static inline hwaddr get_table_pte_address(uint64_t pte, int granule_sz)
+{
+ return PTE_ADDRESS(pte, granule_sz);
+}
+
+/**
+ * get_block_pte_address - return block descriptor output address and block size
+ * ARM ARM Figure D4-16 VMSAv8-64 level0, level1, and level 2 descriptor formats
+ */
+static hwaddr get_block_pte_address(uint64_t pte, int level, int granule_sz,
+ uint64_t *bsz)
+{
+ int n = 0;
+
+ switch (granule_sz) {
+ case 12:
+ if (level == 1) {
+ n = 30;
+ } else if (level == 2) {
+ n = 21;
+ }
+ break;
+ case 14:
+ if (level == 2) {
+ n = 25;
+ }
+ break;
+ case 16:
+ if (level == 2) {
+ n = 29;
+ }
+ break;
+ }
+ if (!n) {
+ error_setg(&error_fatal,
+ "wrong granule/level combination (%d/%d)",
+ granule_sz, level);
+ }
+ *bsz = 1 << n;
+ return PTE_ADDRESS(pte, n);
+}
+
+static inline bool check_perm(int access_attrs, int mem_attrs)
+{
+ if (((access_attrs & IOMMU_RO) && !(mem_attrs & IOMMU_RO)) ||
+ ((access_attrs & IOMMU_WO) && !(mem_attrs & IOMMU_WO))) {
+ return false;
+ }
+ return true;
+}
+
+SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova)
+{
+ if (!extract64(iova, 64 - cfg->tt[0].tsz, cfg->tt[0].tsz - cfg->tbi)) {
+ return &cfg->tt[0];
+ }
+ return &cfg->tt[1];
+}
+
+/**
+ * smmu_ptw_64 - VMSAv8-64 Walk of the page tables for a given IOVA
+ * @cfg: translation config
+ * @tlbe: pre-filled IOMMUTLBEntry
+ * @info: handle to an error info
+ *
+ * Return 0 on success, < 0 on error. In case of error @info is filled
+ */
+static int smmu_ptw_64(SMMUTransCfg *cfg, IOMMUTLBEntry *tlbe,
+ SMMUPTWEventInfo *info)
+{
+ dma_addr_t baseaddr;
+ int stage = cfg->stage;
+ dma_addr_t iova = tlbe->iova;
+ SMMUTransTableInfo *tt = select_tt(cfg, iova);
+ uint8_t level;
+ uint8_t granule_sz;
+
+ if (tt->disabled) {
+ info->type = SMMU_PTW_ERR_TRANSLATION;
+ goto error;
+ }
+
+ level = tt->initial_level;
+ granule_sz = tt->granule_sz;
+ baseaddr = extract64(tt->ttb, 0, 48);
+
+ tlbe->addr_mask = (1 << tt->granule_sz) - 1;
+
+ while (level <= 3) {
+ uint64_t subpage_size = 1ULL << level_shift(level, granule_sz);
+ uint64_t mask = subpage_size - 1;
+ uint32_t offset = iova_level_offset(iova, level, granule_sz);
+ uint64_t pte;
+ dma_addr_t pte_addr = baseaddr + offset * sizeof(pte);
+
+ trace_smmu_page_walk_level(level, iova, subpage_size,
+ baseaddr, offset, pte);
+
+ if (get_pte(baseaddr, offset, &pte, info)) {
+ info->type = SMMU_PTW_ERR_WALK_EABT;
+ info->addr = pte_addr;
+ goto error;
+ }
+ if (is_invalid_pte(pte) || is_reserved_pte(pte, level)) {
+ trace_smmu_page_walk_level_res_invalid_pte(stage, level, baseaddr,
+ pte_addr, offset, pte);
+ info->type = SMMU_PTW_ERR_TRANSLATION;
+ goto error;
+ }
+
+ if (is_page_pte(pte, level)) {
+ uint64_t gpa = get_page_pte_address(pte, granule_sz);
+ if (is_fault(tlbe->perm, pte, true)) {
+ info->type = SMMU_PTW_ERR_PERMISSION;
+ goto error;
+ }
+
+ tlbe->translated_addr = gpa + (iova & mask);
+ trace_smmu_page_walk_level_page_pte(stage, level, iova,
+ baseaddr, pte_addr, pte, gpa);
+ return 0;
+ }
+ if (is_block_pte(pte, level)) {
+ uint64_t block_size;
+ hwaddr gpa = get_block_pte_address(pte, level, granule_sz,
+ &block_size);
+ if (is_fault(tlbe->perm, pte, true)) {
+ info->type = SMMU_PTW_ERR_PERMISSION;
+ goto error;
+ }
+
+ trace_smmu_page_walk_level_block_pte(stage, level, baseaddr,
+ pte_addr, pte, iova, gpa,
+ (int)(block_size >> 20));
+
+ tlbe->translated_addr = gpa + (iova & mask);
+ return 0;
+ }
+
+ /* table pte */
+ if (is_fault(tlbe->perm, pte, false)) {
+ info->type = SMMU_PTW_ERR_PERMISSION;
+ goto error;
+ }
+ baseaddr = get_table_pte_address(pte, granule_sz);
+ level++;
+ }
+
+ info->type = SMMU_PTW_ERR_TRANSLATION;
+
+error:
+ return -EINVAL;
+}
+
+/**
+ * smmu_ptw - Walk the page tables for an IOVA, according to @cfg
+ *
+ * @cfg: translation configuration
+ * @tlbe: pre-filled entry
+ * @info: ptw event handle
+ *
+ * return 0 on success
+ */
+int smmu_ptw(SMMUTransCfg *cfg, IOMMUTLBEntry *tlbe,
+ SMMUPTWEventInfo *info)
+{
+ if (!cfg->aa64) {
+ error_setg(&error_fatal,
+ "SMMUv3 model does not support VMSAv8-32 page walk yet");
+ }
+
+ return smmu_ptw_64(cfg, tlbe, info);
+}
SMMUPciBus *smmu_find_as_from_bus_num(SMMUState *s, uint8_t bus_num)
{
diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h
new file mode 100644
index 0000000..7dd3a53
--- /dev/null
+++ b/hw/arm/smmu-internal.h
@@ -0,0 +1,104 @@
+/*
+ * ARM SMMU support - Internal API
+ *
+ * Copyright (c) 2017 Red Hat, Inc.
+ * Written by Eric Auger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_ARM_SMMU_INTERNAL_H
+#define HW_ARM_SMMU_INTERNAL_H
+
+#define ARM_LPAE_MAX_ADDR_BITS 48
+#define ARM_LPAE_MAX_LEVELS 4
+
+/* PTE Manipulation */
+
+#define ARM_LPAE_PTE_TYPE_SHIFT 0
+#define ARM_LPAE_PTE_TYPE_MASK 0x3
+
+#define ARM_LPAE_PTE_TYPE_BLOCK 1
+#define ARM_LPAE_PTE_TYPE_TABLE 3
+
+#define ARM_LPAE_L3_PTE_TYPE_RESERVED 1
+#define ARM_LPAE_L3_PTE_TYPE_PAGE 3
+
+#define ARM_LPAE_PTE_VALID (1 << 0)
+
+static inline bool is_invalid_pte(uint64_t pte)
+{
+ return !(pte & ARM_LPAE_PTE_VALID);
+}
+
+static inline bool is_reserved_pte(uint64_t pte, int level)
+{
+ return (level == 3) &&
+ ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_L3_PTE_TYPE_RESERVED);
+}
+
+static inline bool is_block_pte(uint64_t pte, int level)
+{
+ return (level < 3) &&
+ ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_PTE_TYPE_BLOCK);
+}
+
+static inline bool is_table_pte(uint64_t pte, int level)
+{
+ return (level < 3) &&
+ ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_PTE_TYPE_TABLE);
+}
+
+static inline bool is_page_pte(uint64_t pte, int level)
+{
+ return (level == 3) &&
+ ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_L3_PTE_TYPE_PAGE);
+}
+
+static inline bool is_fault(int perm, uint64_t pte, bool leaf)
+{
+ uint64_t ap; /* AP or APTable */
+
+ if (leaf) {
+ ap = extract64(pte, 6, 2);
+ } else {
+ ap = extract64(pte, 61, 2);
+ }
+ return (perm & IOMMU_WO) && (ap & 0x2);
+}
+
+/* Level Indexing */
+
+static inline int level_shift(int level, int granule_sz)
+{
+ return granule_sz + (3 - level) * (granule_sz - 3);
+}
+
+static inline uint64_t level_page_mask(int level, int granule_sz)
+{
+ return ~((1ULL << level_shift(level, granule_sz)) - 1);
+}
+
+/**
+ * TODO: handle the case where the level resolves less than
+ * granule_sz -3 IA bits.
+ */
+static inline
+uint64_t iova_level_offset(uint64_t iova, int level, int granule_sz)
+{
+ return (iova >> level_shift(level, granule_sz)) &
+ ((1ULL << (granule_sz - 3)) - 1);
+}
+
+#endif
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
index 193063e..c67cd39 100644
--- a/hw/arm/trace-events
+++ b/hw/arm/trace-events
@@ -2,3 +2,15 @@
# hw/arm/virt-acpi-build.c
virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing out."
+
+# hw/arm/smmu-common.c
+
+smmu_page_walk(int stage, uint64_t baseaddr, int first_level, uint64_t start, uint64_t end) "stage=%d, baseaddr=0x%"PRIx64", first level=%d, start=0x%"PRIx64", end=0x%"PRIx64
+smmu_page_walk_level_in(int level, uint64_t baseaddr, int granule_sz, uint64_t start, uint64_t end, int flags, uint64_t subpage_size) "level=%d baseaddr=0x%"PRIx64" granule=%d, start=0x%"PRIx64" end=0x%"PRIx64" flags=%d subpage_size=0x%lx"
+smmu_page_walk_level(int level, uint64_t iova, size_t subpage_size, uint64_t baseaddr, uint32_t offset, uint64_t pte) "level=%d iova=0x%lx subpage_sz=0x%lx baseaddr=0x%"PRIx64" offset=%d => pte=0x%lx"
+smmu_page_walk_level_res_invalid_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint32_t offset, uint64_t pte) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" offset=%d pte=0x%lx"
+smmu_page_walk_level_page_pte(int stage, int level, uint64_t iova, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t address) "stage=%d level=%d iova=0x%"PRIx64" base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" page address = 0x%"PRIx64
+smmu_page_walk_level_block_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t iova, uint64_t gpa, int bsize_mb) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" iova=0x%"PRIx64" block address = 0x%"PRIx64" block size = %d MiB"
+smmu_page_walk_level_table_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t address) "stage=%d, level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" next table address = 0x%"PRIx64
+smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte) "baseaddr=0x%"PRIx64" index=0x%x, pteaddr=0x%"PRIx64", pte=0x%"PRIx64
+smmu_set_translated_address(hwaddr iova, hwaddr pa) "iova = 0x%"PRIx64" -> pa = 0x%"PRIx64
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index 1495bce..e29ea00 100644
--- a/include/hw/arm/smmu-common.h
+++ b/include/hw/arm/smmu-common.h
@@ -129,4 +129,10 @@ static inline uint16_t smmu_get_sid(SMMUDevice *sdev)
{
return ((pci_bus_num(sdev->bus) & 0xff) << 8) | sdev->devfn;
}
+
+int smmu_ptw(SMMUTransCfg *cfg, IOMMUTLBEntry *tlbe,
+ SMMUPTWEventInfo *info);
+
+SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova);
+
#endif /* HW_ARM_SMMU_COMMON */
--
2.5.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v8 04/14] hw/arm/smmuv3: Skeleton
2018-02-05 13:39 [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support Eric Auger
` (2 preceding siblings ...)
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 03/14] hw/arm/smmu-common: VMSAv8-64 page table walk Eric Auger
@ 2018-02-05 13:39 ` Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 05/14] hw/arm/smmuv3: Wired IRQ and GERROR helpers Eric Auger
` (10 subsequent siblings)
14 siblings, 0 replies; 18+ messages in thread
From: Eric Auger @ 2018-02-05 13:39 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, peter.maydell, qemu-arm, qemu-devel,
prem.mallappa, alex.williamson
Cc: tn, mst, christoffer.dall, bharat.bhushan, jean-philippe.brucker,
edgar.iglesias, linuc.decode, peterx
From: Prem Mallappa <prem.mallappa@broadcom.com>
This patch implements a skeleton for the smmuv3 device.
Datatypes and register definitions are introduced. The MMIO
region, the interrupts and the queue are initialized.
Only the MMIO read operation is implemented here.
Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v7 -> v8:
- remove __smmu_data structs
- revisit struct SMMUQueue
- do not advertise stage 2 support anymore
- use the register definition API and get rid of REG array
- get read of queue structs
v6 -> v7:
- split into several patches
v5 -> v6:
- Use IOMMUMemoryregion
- regs become uint32_t and fix 64b MMIO access (.impl)
- trace_smmuv3_write/read_mmio take the size param
v4 -> v5:
- change smmuv3_translate proto (IOMMUAccessFlags flag)
- has_stagex replaced by is_ste_stagex
- smmu_cfg_populate removed
- added smmuv3_decode_config and reworked error management
- remwork the naming of IOMMU mrs
- fix SMMU_CMDQ_CONS offset
v3 -> v4
- smmu_irq_update
- fix hash key allocation
- set smmu_iommu_ops
- set SMMU_REG_CR0,
- smmuv3_translate: ret.perm not set in bypass mode
- use trace events
- renamed STM2U64 into L1STD_L2PTR and STMSPAN into L1STD_SPAN
- rework smmu_find_ste
- fix tg2granule in TT0/0b10 corresponds to 16kB
v2 -> v3:
- move creation of include/hw/arm/smmuv3.h to this patch to fix compil issue
- compilation allowed
- fix sbus allocation in smmu_init_pci_iommu
- restructure code into headers
- misc cleanups
---
hw/arm/Makefile.objs | 2 +-
hw/arm/smmuv3-internal.h | 155 +++++++++++++++++++++
hw/arm/smmuv3.c | 344 +++++++++++++++++++++++++++++++++++++++++++++++
hw/arm/trace-events | 3 +
include/hw/arm/smmuv3.h | 91 +++++++++++++
5 files changed, 594 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/smmuv3-internal.h
create mode 100644 hw/arm/smmuv3.c
create mode 100644 include/hw/arm/smmuv3.h
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index c84c5ac..676b222 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -20,4 +20,4 @@ obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
obj-$(CONFIG_MPS2) += mps2.o
obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o
-obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o
+obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o smmuv3.o
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
new file mode 100644
index 0000000..84a15c1
--- /dev/null
+++ b/hw/arm/smmuv3-internal.h
@@ -0,0 +1,155 @@
+/*
+ * ARM SMMUv3 support - Internal API
+ *
+ * Copyright (C) 2014-2016 Broadcom Corporation
+ * Copyright (c) 2017 Red Hat, Inc.
+ * Written by Prem Mallappa, Eric Auger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_ARM_SMMU_V3_INTERNAL_H
+#define HW_ARM_SMMU_V3_INTERNAL_H
+
+#include "trace.h"
+#include "qemu/error-report.h"
+#include "hw/arm/smmu-common.h"
+
+/* MMIO Registers */
+
+REG32(IDR0, 0x0)
+ FIELD(IDR0, S1P, 1 , 1)
+ FIELD(IDR0, TTF, 2 , 2)
+ FIELD(IDR0, COHACC, 4 , 1)
+ FIELD(IDR0, ASID16, 12, 1)
+ FIELD(IDR0, TTENDIAN, 21, 2)
+ FIELD(IDR0, STALL_MODEL, 24, 2)
+ FIELD(IDR0, TERM_MODEL, 26, 1)
+ FIELD(IDR0, STLEVEL, 27, 2)
+
+REG32(IDR1, 0x4)
+ FIELD(IDR1, SIDSIZE, 0 , 6)
+ FIELD(IDR1, EVENTQS, 16, 5)
+ FIELD(IDR1, CMDQS, 21, 5)
+
+#define SMMU_IDR1_SIDSIZE 16
+
+REG32(IDR2, 0x8)
+REG32(IDR3, 0xc)
+REG32(IDR4, 0x10)
+REG32(IDR5, 0x14)
+ FIELD(IDR5, OAS, 0, 3);
+ FIELD(IDR5, GRAN4K, 4, 1);
+ FIELD(IDR5, GRAN16K, 5, 1);
+ FIELD(IDR5, GRAN64K, 6, 1);
+
+#define SMMU_IDR5_OAS 4
+
+REG32(IIDR, 0x1c)
+REG32(CR0, 0x20)
+ FIELD(CR0, SMMU_ENABLE, 0, 1)
+ FIELD(CR0, EVENTQEN, 2, 1)
+ FIELD(CR0, CMDQEN, 3, 1)
+
+REG32(CR0ACK, 0x24)
+REG32(CR1, 0x28)
+REG32(CR2, 0x2c)
+REG32(STATUSR, 0x40)
+REG32(IRQ_CTRL, 0x50)
+ FIELD(IRQ_CTRL, GERROR_IRQEN, 0, 1)
+ FIELD(IRQ_CTRL, PRI_IRQEN, 1, 1)
+ FIELD(IRQ_CTRL, EVENTQ_IRQEN, 2, 1)
+
+REG32(IRQ_CTRL_ACK, 0x54)
+REG32(GERROR, 0x60)
+ FIELD(GERROR, CMDQ_ERR, 0, 1)
+ FIELD(GERROR, EVENTQ_ABT_ERR, 2, 1)
+ FIELD(GERROR, PRIQ_ABT_ERR, 3, 1)
+ FIELD(GERROR, MSI_CMDQ_ABT_ERR, 4, 1)
+ FIELD(GERROR, MSI_EVENTQ_ABT_ERR, 5, 1)
+ FIELD(GERROR, MSI_PRIQ_ABT_ERR, 6, 1)
+ FIELD(GERROR, MSI_GERROR_ABT_ERR, 7, 1)
+ FIELD(GERROR, MSI_SFM_ERR, 8, 1)
+
+REG32(GERRORN, 0x64)
+
+#define A_GERROR_IRQ_CFG0 0x68 /* 64b */
+REG32(GERROR_IRQ_CFG1, 0x70)
+REG32(GERROR_IRQ_CFG2, 0x74)
+
+#define A_STRTAB_BASE 0x80 /* 64b */
+
+#define SMMU_BASE_ADDR_MASK 0xffffffffffe0
+
+REG32(STRTAB_BASE_CFG, 0x88)
+ FIELD(STRTAB_BASE_CFG, FMT, 16, 2)
+ FIELD(STRTAB_BASE_CFG, SPLIT, 6 , 5)
+ FIELD(STRTAB_BASE_CFG, LOG2SIZE, 0 , 6)
+
+#define A_CMDQ_BASE 0x90 /* 64b */
+REG32(CMDQ_PROD, 0x98)
+REG32(CMDQ_CONS, 0x9c)
+ FIELD(CMDQ_CONS, ERR, 24, 7)
+
+#define A_EVENTQ_BASE 0xa0 /* 64b */
+REG32(EVENTQ_PROD, 0xa8)
+REG32(EVENTQ_CONS, 0xac)
+
+#define A_EVENTQ_IRQ_CFG0 0xb0 /* 64b */
+REG32(EVENTQ_IRQ_CFG1, 0xb8)
+REG32(EVENTQ_IRQ_CFG2, 0xbc)
+
+REG32(CIDR0, 0xff0)
+REG32(CIDR1, 0xff4)
+REG32(CIDR2, 0xff8)
+REG32(CIDR3, 0xffc)
+REG32(PIDR0, 0xfe0)
+REG32(PIDR1, 0xfe4)
+REG32(PIDR2, 0xfe8)
+REG32(PIDR3, 0xfec)
+REG32(PIDR4, 0xfd0)
+
+static inline int smmu_enabled(SMMUv3State *s)
+{
+ return FIELD_EX32(s->cr[0], CR0, SMMU_ENABLE);
+}
+
+typedef struct Cmd {
+ uint32_t word[4];
+} Cmd;
+
+typedef struct Evt {
+ uint32_t word[8];
+} Evt;
+
+static inline uint64_t smmu_read64(uint64_t r, unsigned offset,
+ unsigned size)
+{
+ if (size == 8 && !offset) {
+ return r;
+ }
+
+ /* 32 bit access */
+
+ if (offset && offset != 4) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "SMMUv3 MMIO read: bad offset/size %u/%u\n",
+ offset, size);
+ return 0;
+ }
+
+ return extract64(r, offset << 3, 32);
+}
+
+#endif
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
new file mode 100644
index 0000000..c9a13b0
--- /dev/null
+++ b/hw/arm/smmuv3.c
@@ -0,0 +1,344 @@
+/*
+ * Copyright (C) 2014-2016 Broadcom Corporation
+ * Copyright (c) 2017 Red Hat, Inc.
+ * Written by Prem Mallappa, Eric Auger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/boards.h"
+#include "sysemu/sysemu.h"
+#include "hw/sysbus.h"
+#include "hw/pci/pci.h"
+#include "exec/address-spaces.h"
+#include "trace.h"
+#include "qemu/error-report.h"
+#include "qapi/error.h"
+
+#include "hw/arm/smmuv3.h"
+#include "smmuv3-internal.h"
+
+static void smmuv3_init_regs(SMMUv3State *s)
+{
+ /**
+ * IDR0: stage1 only, AArch64 only, coherent access, 16b ASID,
+ * multi-level stream table
+ */
+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, S1P, 1); /* stage 1 supported */
+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TTF, 2); /* AArch64 PTW only */
+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, COHACC, 1); /* IO coherent */
+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ASID16, 1); /* 16-bit ASID */
+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TTENDIAN, 2); /* little endian */
+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, STALL_MODEL, 1); /* No stall */
+ /* terminated transaction will always be aborted/error returned */
+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TERM_MODEL, 1);
+ /* 2-level stream table supported */
+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, STLEVEL, 1);
+
+ s->idr[1] = FIELD_DP32(s->idr[1], IDR1, SIDSIZE, SMMU_IDR1_SIDSIZE);
+ s->idr[1] = FIELD_DP32(s->idr[1], IDR1, EVENTQS, 19);
+ s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS, 19);
+
+ /* 4K and 64K granule support */
+ s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1);
+ s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1);
+ s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 bits */
+
+ s->cmdq.base = deposit64(s->cmdq.base, 0, 5, 19); /* LOG2SIZE = 19 */
+ s->cmdq.prod = 0;
+ s->cmdq.cons = 0;
+ s->cmdq.entry_size = sizeof(struct Cmd);
+ s->eventq.base = deposit64(s->eventq.base, 0, 5, 19); /* LOG2SIZE = 19 */
+ s->eventq.prod = 0;
+ s->eventq.cons = 0;
+ s->eventq.entry_size = sizeof(struct Evt);
+
+ s->features = 0;
+ s->sid_split = 0;
+}
+
+static void smmu_write_mmio(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ /* not yet implemented */
+}
+
+static uint64_t smmu_read_mmio(void *opaque, hwaddr addr, unsigned size)
+{
+ SMMUState *sys = opaque;
+ SMMUv3State *s = ARM_SMMUV3(sys);
+ uint64_t val;
+
+ /* CONSTRAINED UNPREDICTABLE choice to have page0/1 be exact aliases */
+ addr &= ~0x10000;
+
+ if (size != 4 && size != 8) {
+ qemu_log_mask(LOG_GUEST_ERROR, "SMMUv3 MMIO read: bad size %u\n", size);
+ return 0;
+ }
+
+ /* Primecell/Corelink ID registers */
+ switch (addr) {
+ case A_CIDR0:
+ val = 0x0D;
+ break;
+ case A_CIDR1:
+ val = 0xF0;
+ break;
+ case A_CIDR2:
+ val = 0x05;
+ break;
+ case A_CIDR3:
+ val = 0xB1;
+ break;
+ case A_PIDR0:
+ val = 0x84; /* Part Number */
+ break;
+ case A_PIDR1:
+ val = 0xB4; /* JEP106 ID code[3:0] for Arm and Part numver[11:8] */
+ break;
+ case A_PIDR3:
+ val = 0x10; /* MMU600 p1 */
+ break;
+ case A_PIDR4:
+ val = 0x4; /* 4KB region count, JEP106 continuation code for Arm */
+ break;
+ case 0xFD4 ... 0xFDC: /* SMMU_PDIR 5-7 */
+ val = 0;
+ break;
+ case A_IDR0 ... A_IDR5:
+ val = s->idr[(addr - A_IDR0) / 4];
+ break;
+ case A_IIDR:
+ val = s->iidr;
+ break;
+ case A_CR0:
+ val = s->cr[0];
+ break;
+ case A_CR0ACK:
+ val = s->cr0ack;
+ break;
+ case A_CR1:
+ val = s->cr[1];
+ break;
+ case A_CR2:
+ val = s->cr[2];
+ break;
+ case A_STATUSR:
+ val = s->statusr;
+ break;
+ case A_IRQ_CTRL:
+ val = s->irq_ctrl;
+ break;
+ case A_IRQ_CTRL_ACK:
+ val = s->irq_ctrl_ack;
+ break;
+ case A_GERROR:
+ val = s->gerror;
+ break;
+ case A_GERRORN:
+ val = s->gerrorn;
+ break;
+ case A_GERROR_IRQ_CFG0: /* 64b */
+ val = smmu_read64(s->gerror_irq_cfg0, 0, size);
+ break;
+ case A_GERROR_IRQ_CFG0 + 4:
+ val = smmu_read64(s->gerror_irq_cfg0, 4, size);
+ break;
+ case A_GERROR_IRQ_CFG1:
+ val = s->gerror_irq_cfg1;
+ break;
+ case A_GERROR_IRQ_CFG2:
+ val = s->gerror_irq_cfg2;
+ break;
+ case A_STRTAB_BASE: /* 64b */
+ val = smmu_read64(s->strtab_base, 0, size);
+ break;
+ case A_STRTAB_BASE + 4: /* 64b */
+ val = smmu_read64(s->strtab_base, 4, size);
+ break;
+ case A_STRTAB_BASE_CFG:
+ val = s->strtab_base_cfg;
+ break;
+ case A_CMDQ_BASE: /* 64b */
+ val = smmu_read64(s->cmdq.base, 0, size);
+ break;
+ case A_CMDQ_BASE + 4:
+ val = smmu_read64(s->cmdq.base, 4, size);
+ break;
+ case A_CMDQ_PROD:
+ val = s->cmdq.prod;
+ break;
+ case A_CMDQ_CONS:
+ val = s->cmdq.cons;
+ break;
+ case A_EVENTQ_BASE: /* 64b */
+ val = smmu_read64(s->eventq.base, 0, size);
+ break;
+ case A_EVENTQ_BASE + 4: /* 64b */
+ val = smmu_read64(s->eventq.base, 4, size);
+ break;
+ case A_EVENTQ_PROD:
+ val = s->eventq.prod;
+ break;
+ case A_EVENTQ_CONS:
+ val = s->eventq.cons;
+ break;
+ default:
+ error_report("%s unhandled access at 0x%"PRIx64, __func__, addr);
+ break;
+ }
+
+ trace_smmuv3_read_mmio(addr, val, size);
+ return val;
+}
+
+static const MemoryRegionOps smmu_mem_ops = {
+ .read = smmu_read_mmio,
+ .write = smmu_write_mmio,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 8,
+ },
+};
+
+static void smmu_init_irq(SMMUv3State *s, SysBusDevice *dev)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
+ sysbus_init_irq(dev, &s->irq[i]);
+ }
+}
+
+static void smmu_reset(DeviceState *dev)
+{
+ SMMUv3State *s = ARM_SMMUV3(dev);
+ smmuv3_init_regs(s);
+}
+
+static void smmu_realize(DeviceState *d, Error **errp)
+{
+ SMMUState *sys = ARM_SMMU(d);
+ SMMUv3State *s = ARM_SMMUV3(sys);
+ SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s);
+ SysBusDevice *dev = SYS_BUS_DEVICE(d);
+ Error *local_err = NULL;
+
+ c->parent_realize(d, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ memory_region_init_io(&sys->iomem, OBJECT(s),
+ &smmu_mem_ops, sys, TYPE_ARM_SMMUV3, 0x20000);
+
+ sys->mrtypename = g_strdup(TYPE_SMMUV3_IOMMU_MEMORY_REGION);
+
+ sysbus_init_mmio(dev, &sys->iomem);
+
+ smmu_init_irq(s, dev);
+}
+
+static const VMStateDescription vmstate_smmuv3 = {
+ .name = "smmuv3",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(features, SMMUv3State),
+ VMSTATE_UINT8(sid_size, SMMUv3State),
+ VMSTATE_UINT8(sid_split, SMMUv3State),
+
+ VMSTATE_UINT32_ARRAY(idr, SMMUv3State, 6),
+ VMSTATE_UINT32(iidr, SMMUv3State),
+ VMSTATE_UINT32_ARRAY(cr, SMMUv3State, 3),
+ VMSTATE_UINT32(cr0ack, SMMUv3State),
+ VMSTATE_UINT32(statusr, SMMUv3State),
+ VMSTATE_UINT32(irq_ctrl, SMMUv3State),
+ VMSTATE_UINT32(irq_ctrl_ack, SMMUv3State),
+ VMSTATE_UINT32(gerror, SMMUv3State),
+ VMSTATE_UINT32(gerrorn, SMMUv3State),
+ VMSTATE_UINT64(gerror_irq_cfg0, SMMUv3State),
+ VMSTATE_UINT32(gerror_irq_cfg1, SMMUv3State),
+ VMSTATE_UINT32(gerror_irq_cfg2, SMMUv3State),
+ VMSTATE_UINT64(strtab_base, SMMUv3State),
+ VMSTATE_UINT32(strtab_base_cfg, SMMUv3State),
+ VMSTATE_UINT64(eventq_irq_cfg0, SMMUv3State),
+ VMSTATE_UINT32(eventq_irq_cfg1, SMMUv3State),
+ VMSTATE_UINT32(eventq_irq_cfg2, SMMUv3State),
+
+ VMSTATE_UINT64(cmdq.base, SMMUv3State),
+ VMSTATE_UINT32(cmdq.prod, SMMUv3State),
+ VMSTATE_UINT32(cmdq.cons, SMMUv3State),
+ VMSTATE_UINT8(cmdq.entry_size, SMMUv3State),
+ VMSTATE_UINT64(eventq.base, SMMUv3State),
+ VMSTATE_UINT32(eventq.prod, SMMUv3State),
+ VMSTATE_UINT32(eventq.cons, SMMUv3State),
+ VMSTATE_UINT8(eventq.entry_size, SMMUv3State),
+
+ VMSTATE_END_OF_LIST(),
+ },
+};
+
+static void smmuv3_instance_init(Object *obj)
+{
+ /* Nothing much to do here as of now */
+}
+
+static void smmuv3_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SMMUv3Class *c = ARM_SMMUV3_CLASS(klass);
+
+ dc->reset = smmu_reset;
+ dc->vmsd = &vmstate_smmuv3;
+ c->parent_realize = dc->realize;
+ dc->realize = smmu_realize;
+}
+
+static void smmuv3_iommu_memory_region_class_init(ObjectClass *klass,
+ void *data)
+{
+}
+
+static const TypeInfo smmuv3_type_info = {
+ .name = TYPE_ARM_SMMUV3,
+ .parent = TYPE_ARM_SMMU,
+ .instance_size = sizeof(SMMUv3State),
+ .instance_init = smmuv3_instance_init,
+ .class_size = sizeof(SMMUv3Class),
+ .class_init = smmuv3_class_init,
+};
+
+static const TypeInfo smmuv3_iommu_memory_region_info = {
+ .parent = TYPE_IOMMU_MEMORY_REGION,
+ .name = TYPE_SMMUV3_IOMMU_MEMORY_REGION,
+ .class_init = smmuv3_iommu_memory_region_class_init,
+};
+
+static void smmuv3_register_types(void)
+{
+ type_register(&smmuv3_type_info);
+ type_register(&smmuv3_iommu_memory_region_info);
+}
+
+type_init(smmuv3_register_types)
+
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
index c67cd39..8affbf7 100644
--- a/hw/arm/trace-events
+++ b/hw/arm/trace-events
@@ -14,3 +14,6 @@ smmu_page_walk_level_block_pte(int stage, int level, uint64_t baseaddr, uint64_t
smmu_page_walk_level_table_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t address) "stage=%d, level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" next table address = 0x%"PRIx64
smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte) "baseaddr=0x%"PRIx64" index=0x%x, pteaddr=0x%"PRIx64", pte=0x%"PRIx64
smmu_set_translated_address(hwaddr iova, hwaddr pa) "iova = 0x%"PRIx64" -> pa = 0x%"PRIx64
+
+#hw/arm/smmuv3.c
+smmuv3_read_mmio(hwaddr addr, uint64_t val, unsigned size) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x"
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
new file mode 100644
index 0000000..1d4e50e
--- /dev/null
+++ b/include/hw/arm/smmuv3.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2014-2016 Broadcom Corporation
+ * Copyright (c) 2017 Red Hat, Inc.
+ * Written by Prem Mallappa, Eric Auger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_ARM_SMMUV3_H
+#define HW_ARM_SMMUV3_H
+
+#include "hw/arm/smmu-common.h"
+#include "hw/registerfields.h"
+
+#define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-memory-region"
+
+#define SMMU_NREGS 0x200
+
+typedef struct SMMUQueue {
+ hwaddr base;
+ uint32_t prod;
+ uint32_t cons;
+ uint8_t entry_size;
+} SMMUQueue;
+
+typedef struct SMMUv3State {
+ SMMUState smmu_state;
+
+ /* Local cache of most-frequently used registers */
+#define SMMU_FEATURE_2LVL_STE (1 << 0)
+ uint32_t features;
+ uint8_t sid_size;
+ uint8_t sid_split;
+
+ uint32_t idr[6];
+ uint32_t iidr;
+ uint32_t cr[3];
+ uint32_t cr0ack;
+ uint32_t statusr;
+ uint32_t irq_ctrl;
+ uint32_t irq_ctrl_ack;
+ uint32_t gerror;
+ uint32_t gerrorn;
+ uint64_t gerror_irq_cfg0;
+ uint32_t gerror_irq_cfg1;
+ uint32_t gerror_irq_cfg2;
+ uint64_t strtab_base;
+ uint32_t strtab_base_cfg;
+ uint64_t eventq_irq_cfg0;
+ uint32_t eventq_irq_cfg1;
+ uint32_t eventq_irq_cfg2;
+
+ SMMUQueue eventq, cmdq;
+
+ qemu_irq irq[4];
+} SMMUv3State;
+
+typedef enum {
+ SMMU_IRQ_EVTQ,
+ SMMU_IRQ_PRIQ,
+ SMMU_IRQ_CMD_SYNC,
+ SMMU_IRQ_GERROR,
+} SMMUIrq;
+
+typedef struct {
+ /*< private >*/
+ SMMUBaseClass smmu_base_class;
+ /*< public >*/
+
+ DeviceRealize parent_realize;
+} SMMUv3Class;
+
+#define TYPE_ARM_SMMUV3 "arm-smmuv3"
+#define ARM_SMMUV3(obj) OBJECT_CHECK(SMMUv3State, (obj), TYPE_ARM_SMMUV3)
+#define ARM_SMMUV3_CLASS(klass) \
+ OBJECT_CLASS_CHECK(SMMUv3Class, (klass), TYPE_ARM_SMMUV3)
+#define ARM_SMMUV3_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(SMMUv3Class, (obj), TYPE_ARM_SMMUV3)
+
+#endif
--
2.5.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v8 05/14] hw/arm/smmuv3: Wired IRQ and GERROR helpers
2018-02-05 13:39 [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support Eric Auger
` (3 preceding siblings ...)
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 04/14] hw/arm/smmuv3: Skeleton Eric Auger
@ 2018-02-05 13:39 ` Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 06/14] hw/arm/smmuv3: Queue helpers Eric Auger
` (9 subsequent siblings)
14 siblings, 0 replies; 18+ messages in thread
From: Eric Auger @ 2018-02-05 13:39 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, peter.maydell, qemu-arm, qemu-devel,
prem.mallappa, alex.williamson
Cc: tn, mst, christoffer.dall, bharat.bhushan, jean-philippe.brucker,
edgar.iglesias, linuc.decode, peterx
We introduce some helpers to handle wired IRQs and especially
GERROR interrupt. SMMU writes GERROR register on GERROR event
and SW acks GERROR interrupts by setting GERRORn.
The Wired interrupts are edge sensitive hence the pulse usage.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v7 -> v8:
- remove SMMU_PENDING_GERRORS macro
- properly toggle gerror
- properly sanitize gerrorn write
---
hw/arm/smmuv3-internal.h | 10 ++++++++
hw/arm/smmuv3.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++
hw/arm/trace-events | 3 +++
3 files changed, 77 insertions(+)
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index 84a15c1..72d9c6c 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -152,4 +152,14 @@ static inline uint64_t smmu_read64(uint64_t r, unsigned offset,
return extract64(r, offset << 3, 32);
}
+/* Interrupts */
+
+#define smmuv3_eventq_irq_enabled(s) \
+ (FIELD_EX32(s->irq_ctrl, IRQ_CTRL, EVENTQ_IRQEN))
+#define smmuv3_gerror_irq_enabled(s) \
+ (FIELD_EX32(s->irq_ctrl, IRQ_CTRL, GERROR_IRQEN))
+
+void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq, uint32_t gerror_mask);
+void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t gerrorn);
+
#endif
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index c9a13b0..6bad7e8 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -30,6 +30,70 @@
#include "hw/arm/smmuv3.h"
#include "smmuv3-internal.h"
+/**
+ * smmuv3_trigger_irq - pulse @irq if enabled and update
+ * GERROR register in case of GERROR interrupt
+ *
+ * @irq: irq type
+ * @gerror_mask: mask of gerrors to toggle (relevant if @irq is GERROR)
+ */
+void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq, uint32_t gerror_mask)
+{
+
+ bool pulse = false;
+
+ switch (irq) {
+ case SMMU_IRQ_EVTQ:
+ pulse = smmuv3_eventq_irq_enabled(s);
+ break;
+ case SMMU_IRQ_PRIQ:
+ error_setg(&error_fatal, "PRI not supported");
+ break;
+ case SMMU_IRQ_CMD_SYNC:
+ pulse = true;
+ break;
+ case SMMU_IRQ_GERROR:
+ {
+ uint32_t pending = s->gerror ^ s->gerrorn;
+ uint32_t new_gerrors = ~pending & gerror_mask;
+
+ if (!new_gerrors) {
+ /* only toggle non pending errors */
+ return;
+ }
+ s->gerror ^= new_gerrors;
+ trace_smmuv3_write_gerror(new_gerrors, s->gerror);
+
+ /* pulse the GERROR irq only if all previous gerrors were acked */
+ pulse = smmuv3_gerror_irq_enabled(s) && !pending;
+ break;
+ }
+ }
+ if (pulse) {
+ trace_smmuv3_trigger_irq(irq);
+ qemu_irq_pulse(s->irq[irq]);
+ }
+}
+
+void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t new_gerrorn)
+{
+ uint32_t pending = s->gerror ^ s->gerrorn;
+ uint32_t toggled = s->gerrorn ^ new_gerrorn;
+ uint32_t acked;
+
+ if (toggled & ~pending) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "guest toggles non pending errors = 0x%x\n",
+ toggled & ~pending);
+ }
+
+ /* Make sure SW does not toggle irqs that are not active */
+ acked = toggled & pending;
+ s->gerrorn ^= acked;
+
+ trace_smmuv3_write_gerrorn(acked, s->gerrorn);
+}
+
static void smmuv3_init_regs(SMMUv3State *s)
{
/**
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
index 8affbf7..957a67e 100644
--- a/hw/arm/trace-events
+++ b/hw/arm/trace-events
@@ -17,3 +17,6 @@ smmu_set_translated_address(hwaddr iova, hwaddr pa) "iova = 0x%"PRIx64" -> pa =
#hw/arm/smmuv3.c
smmuv3_read_mmio(hwaddr addr, uint64_t val, unsigned size) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x"
+smmuv3_trigger_irq(int irq) "irq=%d"
+smmuv3_write_gerror(uint32_t toggled, uint32_t gerror) "toggled=0x%x, new gerror=0x%x"
+smmuv3_write_gerrorn(uint32_t acked, uint32_t gerrorn) "acked=0x%x, new gerrorn=0x%x"
--
2.5.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v8 06/14] hw/arm/smmuv3: Queue helpers
2018-02-05 13:39 [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support Eric Auger
` (4 preceding siblings ...)
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 05/14] hw/arm/smmuv3: Wired IRQ and GERROR helpers Eric Auger
@ 2018-02-05 13:39 ` Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 07/14] hw/arm/smmuv3: Implement MMIO write operations Eric Auger
` (8 subsequent siblings)
14 siblings, 0 replies; 18+ messages in thread
From: Eric Auger @ 2018-02-05 13:39 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, peter.maydell, qemu-arm, qemu-devel,
prem.mallappa, alex.williamson
Cc: tn, mst, christoffer.dall, bharat.bhushan, jean-philippe.brucker,
edgar.iglesias, linuc.decode, peterx
We introduce helpers to read/write into the command and event
circular queues.
smmuv3_write_eventq and smmuv3_cmq_consume will become static
in subsequent patches.
Invalidation commands are not yet dealt with. We do not cache
data that need to be invalidated. This will change with vhost
integration.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v7 -> v8
- use address_space_rw
- helpers inspired from spec
---
hw/arm/smmuv3-internal.h | 142 ++++++++++++++++++++++++++++++++++++++++++++
hw/arm/smmuv3.c | 151 +++++++++++++++++++++++++++++++++++++++++++++++
hw/arm/trace-events | 4 ++
3 files changed, 297 insertions(+)
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index 72d9c6c..44564ed 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -162,4 +162,146 @@ static inline uint64_t smmu_read64(uint64_t r, unsigned offset,
void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq, uint32_t gerror_mask);
void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t gerrorn);
+/* Queue Handling */
+
+#define LOG2SIZE(q) extract64((q)->base, 0, 5)
+#define BASE(q) ((q)->base & SMMU_BASE_ADDR_MASK)
+#define WRAP_MASK(q) (1 << LOG2SIZE(q))
+#define INDEX_MASK(q) ((1 << LOG2SIZE(q)) - 1)
+#define WRAP_INDEX_MASK(q) ((1 << (LOG2SIZE(q) + 1)) - 1)
+
+#define Q_CONS_ENTRY(q) (BASE(q) + \
+ (q)->entry_size * ((q)->cons & INDEX_MASK(q)))
+#define Q_PROD_ENTRY(q) (BASE(q) + \
+ (q)->entry_size * ((q)->prod & INDEX_MASK(q)))
+
+#define Q_CONS(q) ((q)->cons & INDEX_MASK(q))
+#define Q_PROD(q) ((q)->prod & INDEX_MASK(q))
+
+#define Q_CONS_WRAP(q) (((q)->cons & WRAP_MASK(q)) >> LOG2SIZE(q))
+#define Q_PROD_WRAP(q) (((q)->prod & WRAP_MASK(q)) >> LOG2SIZE(q))
+
+#define Q_FULL(q) \
+ (((((q)->cons) & INDEX_MASK(q)) == \
+ (((q)->prod) & INDEX_MASK(q))) && \
+ ((((q)->cons) & WRAP_MASK(q)) != \
+ (((q)->prod) & WRAP_MASK(q))))
+
+#define Q_EMPTY(q) \
+ (((((q)->cons) & INDEX_MASK(q)) == \
+ (((q)->prod) & INDEX_MASK(q))) && \
+ ((((q)->cons) & WRAP_MASK(q)) == \
+ (((q)->prod) & WRAP_MASK(q))))
+
+#define SMMUV3_CMDQ_ENABLED(s) \
+ (FIELD_EX32(s->cr[0], CR0, CMDQEN))
+
+#define SMMUV3_EVENTQ_ENABLED(s) \
+ (FIELD_EX32(s->cr[0], CR0, EVENTQEN))
+
+static inline void smmu_write_cmdq_err(SMMUv3State *s, uint32_t err_type)
+{
+ s->cmdq.cons = FIELD_DP32(s->cmdq.cons, CMDQ_CONS, ERR, err_type);
+}
+
+void smmuv3_write_eventq(SMMUv3State *s, Evt *evt);
+
+/* Commands */
+
+enum {
+ SMMU_CMD_PREFETCH_CONFIG = 0x01,
+ SMMU_CMD_PREFETCH_ADDR,
+ SMMU_CMD_CFGI_STE,
+ SMMU_CMD_CFGI_STE_RANGE,
+ SMMU_CMD_CFGI_CD,
+ SMMU_CMD_CFGI_CD_ALL,
+ SMMU_CMD_CFGI_ALL,
+ SMMU_CMD_TLBI_NH_ALL = 0x10,
+ SMMU_CMD_TLBI_NH_ASID,
+ SMMU_CMD_TLBI_NH_VA,
+ SMMU_CMD_TLBI_NH_VAA,
+ SMMU_CMD_TLBI_EL3_ALL = 0x18,
+ SMMU_CMD_TLBI_EL3_VA = 0x1a,
+ SMMU_CMD_TLBI_EL2_ALL = 0x20,
+ SMMU_CMD_TLBI_EL2_ASID,
+ SMMU_CMD_TLBI_EL2_VA,
+ SMMU_CMD_TLBI_EL2_VAA, /* 0x23 */
+ SMMU_CMD_TLBI_S12_VMALL = 0x28,
+ SMMU_CMD_TLBI_S2_IPA = 0x2a,
+ SMMU_CMD_TLBI_NSNH_ALL = 0x30,
+ SMMU_CMD_ATC_INV = 0x40,
+ SMMU_CMD_PRI_RESP,
+ SMMU_CMD_RESUME = 0x44,
+ SMMU_CMD_STALL_TERM,
+ SMMU_CMD_SYNC, /* 0x46 */
+};
+
+static const char *cmd_stringify[] = {
+ [SMMU_CMD_PREFETCH_CONFIG] = "SMMU_CMD_PREFETCH_CONFIG",
+ [SMMU_CMD_PREFETCH_ADDR] = "SMMU_CMD_PREFETCH_ADDR",
+ [SMMU_CMD_CFGI_STE] = "SMMU_CMD_CFGI_STE",
+ [SMMU_CMD_CFGI_STE_RANGE] = "SMMU_CMD_CFGI_STE_RANGE",
+ [SMMU_CMD_CFGI_CD] = "SMMU_CMD_CFGI_CD",
+ [SMMU_CMD_CFGI_CD_ALL] = "SMMU_CMD_CFGI_CD_ALL",
+ [SMMU_CMD_CFGI_ALL] = "SMMU_CMD_CFGI_ALL",
+ [SMMU_CMD_TLBI_NH_ALL] = "SMMU_CMD_TLBI_NH_ALL",
+ [SMMU_CMD_TLBI_NH_ASID] = "SMMU_CMD_TLBI_NH_ASID",
+ [SMMU_CMD_TLBI_NH_VA] = "SMMU_CMD_TLBI_NH_VA",
+ [SMMU_CMD_TLBI_NH_VAA] = "SMMU_CMD_TLBI_NH_VAA",
+ [SMMU_CMD_TLBI_EL3_ALL] = "SMMU_CMD_TLBI_EL3_ALL",
+ [SMMU_CMD_TLBI_EL3_VA] = "SMMU_CMD_TLBI_EL3_VA",
+ [SMMU_CMD_TLBI_EL2_ALL] = "SMMU_CMD_TLBI_EL2_ALL",
+ [SMMU_CMD_TLBI_EL2_ASID] = "SMMU_CMD_TLBI_EL2_ASID",
+ [SMMU_CMD_TLBI_EL2_VA] = "SMMU_CMD_TLBI_EL2_VA",
+ [SMMU_CMD_TLBI_EL2_VAA] = "SMMU_CMD_TLBI_EL2_VAA",
+ [SMMU_CMD_TLBI_S12_VMALL] = "SMMU_CMD_TLBI_S12_VMALL",
+ [SMMU_CMD_TLBI_S2_IPA] = "SMMU_CMD_TLBI_S2_IPA",
+ [SMMU_CMD_TLBI_NSNH_ALL] = "SMMU_CMD_TLBI_NSNH_ALL",
+ [SMMU_CMD_ATC_INV] = "SMMU_CMD_ATC_INV",
+ [SMMU_CMD_PRI_RESP] = "SMMU_CMD_PRI_RESP",
+ [SMMU_CMD_RESUME] = "SMMU_CMD_RESUME",
+ [SMMU_CMD_STALL_TERM] = "SMMU_CMD_STALL_TERM",
+ [SMMU_CMD_SYNC] = "SMMU_CMD_SYNC",
+};
+
+/* CMDQ fields */
+
+typedef enum {
+ SMMU_CERROR_NONE = 0,
+ SMMU_CERROR_ILL,
+ SMMU_CERROR_ABT,
+ SMMU_CERROR_ATC_INV_SYNC,
+} SMMUCmdError;
+
+enum { /* Command completion notification */
+ CMD_SYNC_SIG_NONE,
+ CMD_SYNC_SIG_IRQ,
+ CMD_SYNC_SIG_SEV,
+};
+
+#define CMD_TYPE(x) extract32((x)->word[0], 0, 8)
+#define CMD_SEC(x) extract32((x)->word[0], 9, 1)
+#define CMD_SEV(x) extract32((x)->word[0], 10, 1)
+#define CMD_AC(x) extract32((x)->word[0], 12, 1)
+#define CMD_AB(x) extract32((x)->word[0], 13, 1)
+#define CMD_CS(x) extract32((x)->word[0], 12, 2)
+#define CMD_SSID(x) extract32((x)->word[0], 16, 16)
+#define CMD_SID(x) ((x)->word[1])
+#define CMD_VMID(x) extract32((x)->word[1], 0, 16)
+#define CMD_ASID(x) extract32((x)->word[1], 16, 16)
+#define CMD_STAG(x) extract32((x)->word[2], 0, 16)
+#define CMD_RESP(x) extract32((x)->word[2], 11, 2)
+#define CMD_GRPID(x) extract32((x)->word[3], 0, 8)
+#define CMD_SIZE(x) extract32((x)->word[3], 0, 16)
+#define CMD_LEAF(x) extract32((x)->word[3], 0, 1)
+#define CMD_SPAN(x) extract32((x)->word[3], 0, 5)
+#define CMD_ADDR(x) ({ \
+ uint64_t addr = (uint64_t)(x)->word[3]; \
+ addr <<= 32; \
+ addr |= extract32((x)->word[3], 12, 20); \
+ addr; \
+ })
+
+int smmuv3_cmdq_consume(SMMUv3State *s);
+
#endif
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 6bad7e8..79970d7 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -94,6 +94,75 @@ void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t new_gerrorn)
trace_smmuv3_write_gerrorn(acked, s->gerrorn);
}
+static uint32_t queue_index_inc(uint32_t val,
+ uint32_t qidx_mask, uint32_t qwrap_mask)
+{
+ uint32_t i = (val + 1) & qidx_mask;
+
+ if (i <= (val & qidx_mask)) {
+ i = ((val & qwrap_mask) ^ qwrap_mask) | i;
+ } else {
+ i = (val & qwrap_mask) | i;
+ }
+ return i;
+}
+
+static MemTxResult smmu_queue_read(SMMUQueue *q, void *data)
+{
+ dma_addr_t addr = Q_CONS_ENTRY(q);
+ MemTxResult ret;
+
+ ret = dma_memory_read(&address_space_memory, addr,
+ (uint8_t *)data, q->entry_size);
+ if (ret != MEMTX_OK) {
+ return ret;
+ }
+
+ q->cons = queue_index_inc(q->cons, INDEX_MASK(q), WRAP_MASK(q));
+ return ret;
+}
+
+static void smmu_queue_write(SMMUQueue *q, void *data)
+{
+ dma_addr_t addr = Q_PROD_ENTRY(q);
+ MemTxResult ret;
+
+ ret = dma_memory_write(&address_space_memory, addr,
+ (uint8_t *)data, q->entry_size);
+ if (ret != MEMTX_OK) {
+ return;
+ }
+
+ q->prod = queue_index_inc(q->prod, INDEX_MASK(q), WRAP_MASK(q));
+}
+
+static inline MemTxResult smmuv3_read_cmdq(SMMUv3State *s, Cmd *cmd)
+{
+ SMMUQueue *q = &s->cmdq;
+ return smmu_queue_read(q, cmd);
+}
+
+void smmuv3_write_eventq(SMMUv3State *s, Evt *evt)
+{
+ SMMUQueue *q = &s->eventq;
+ bool q_empty = Q_EMPTY(q);
+ bool q_full = Q_FULL(q);
+
+ if (!SMMUV3_EVENTQ_ENABLED(s)) {
+ return;
+ }
+
+ if (q_full) {
+ return;
+ }
+
+ smmu_queue_write(q, evt);
+
+ if (q_empty) {
+ smmuv3_trigger_irq(s, SMMU_IRQ_EVTQ, 0);
+ }
+}
+
static void smmuv3_init_regs(SMMUv3State *s)
{
/**
@@ -133,6 +202,88 @@ static void smmuv3_init_regs(SMMUv3State *s)
s->sid_split = 0;
}
+int smmuv3_cmdq_consume(SMMUv3State *s)
+{
+ SMMUCmdError cmd_error = SMMU_CERROR_NONE;
+ SMMUQueue *q = &s->cmdq;
+
+
+ if (!SMMUV3_CMDQ_ENABLED(s)) {
+ return 0;
+ }
+
+ while (!Q_EMPTY(q)) {
+ uint32_t pending = s->gerror ^ s->gerrorn;
+ uint32_t type;
+ Cmd cmd;
+
+ trace_smmuv3_cmdq_consume(Q_PROD(q), Q_CONS(q),
+ Q_PROD_WRAP(q), Q_CONS_WRAP(q));
+
+ if (FIELD_EX32(pending, GERROR, CMDQ_ERR)) {
+ break;
+ }
+
+ if (smmuv3_read_cmdq(s, &cmd) != MEMTX_OK) {
+ cmd_error = SMMU_CERROR_ABT;
+ break;
+ }
+
+ type = CMD_TYPE(&cmd);
+
+ switch (type) {
+ case SMMU_CMD_SYNC:
+ if (CMD_CS(&cmd) & CMD_SYNC_SIG_IRQ) {
+ smmuv3_trigger_irq(s, SMMU_IRQ_CMD_SYNC, 0);
+ }
+ break;
+ case SMMU_CMD_PREFETCH_CONFIG:
+ case SMMU_CMD_PREFETCH_ADDR:
+ case SMMU_CMD_CFGI_STE:
+ case SMMU_CMD_CFGI_STE_RANGE: /* same as SMMU_CMD_CFGI_ALL */
+ case SMMU_CMD_CFGI_CD:
+ case SMMU_CMD_CFGI_CD_ALL:
+ case SMMU_CMD_TLBI_NH_ALL:
+ case SMMU_CMD_TLBI_NH_ASID:
+ case SMMU_CMD_TLBI_NH_VA:
+ case SMMU_CMD_TLBI_NH_VAA:
+ case SMMU_CMD_TLBI_EL3_ALL:
+ case SMMU_CMD_TLBI_EL3_VA:
+ case SMMU_CMD_TLBI_EL2_ALL:
+ case SMMU_CMD_TLBI_EL2_ASID:
+ case SMMU_CMD_TLBI_EL2_VA:
+ case SMMU_CMD_TLBI_EL2_VAA:
+ case SMMU_CMD_TLBI_S12_VMALL:
+ case SMMU_CMD_TLBI_S2_IPA:
+ case SMMU_CMD_TLBI_NSNH_ALL:
+ case SMMU_CMD_ATC_INV:
+ case SMMU_CMD_PRI_RESP:
+ case SMMU_CMD_RESUME:
+ case SMMU_CMD_STALL_TERM:
+ trace_smmuv3_unhandled_cmd(type);
+ break;
+ default:
+ cmd_error = SMMU_CERROR_ILL;
+ error_report("Illegal command type: %d", CMD_TYPE(&cmd));
+ break;
+ }
+ if (type != SMMU_CERROR_ILL) {
+ trace_smmuv3_cmdq_opcode(cmd_stringify[type]);
+ }
+ }
+
+ if (cmd_error) {
+ error_report("GERROR_CMDQ: CONS.ERR=%d", cmd_error);
+ smmu_write_cmdq_err(s, cmd_error);
+ smmuv3_trigger_irq(s, SMMU_IRQ_GERROR, R_GERROR_CMDQ_ERR_MASK);
+ }
+
+ trace_smmuv3_cmdq_consume_out(Q_PROD(q), Q_CONS(q),
+ Q_PROD_WRAP(q), Q_CONS_WRAP(q));
+
+ return 0;
+}
+
static void smmu_write_mmio(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
index 957a67e..d73e151 100644
--- a/hw/arm/trace-events
+++ b/hw/arm/trace-events
@@ -20,3 +20,7 @@ smmuv3_read_mmio(hwaddr addr, uint64_t val, unsigned size) "addr: 0x%"PRIx64" va
smmuv3_trigger_irq(int irq) "irq=%d"
smmuv3_write_gerror(uint32_t toggled, uint32_t gerror) "toggled=0x%x, new gerror=0x%x"
smmuv3_write_gerrorn(uint32_t acked, uint32_t gerrorn) "acked=0x%x, new gerrorn=0x%x"
+smmuv3_unhandled_cmd(uint32_t type) "Unhandled command type=%d"
+smmuv3_cmdq_consume(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "prod=%d cons=%d prod.wrap=%d cons.wrap=%d"
+smmuv3_cmdq_opcode(const char *opcode) "<--- %s"
+smmuv3_cmdq_consume_out(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "prod:%d, cons:%d, prod_wrap:%d, cons_wrap:%d "
--
2.5.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v8 07/14] hw/arm/smmuv3: Implement MMIO write operations
2018-02-05 13:39 [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support Eric Auger
` (5 preceding siblings ...)
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 06/14] hw/arm/smmuv3: Queue helpers Eric Auger
@ 2018-02-05 13:39 ` Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 08/14] hw/arm/smmuv3: Event queue recording helper Eric Auger
` (7 subsequent siblings)
14 siblings, 0 replies; 18+ messages in thread
From: Eric Auger @ 2018-02-05 13:39 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, peter.maydell, qemu-arm, qemu-devel,
prem.mallappa, alex.williamson
Cc: tn, mst, christoffer.dall, bharat.bhushan, jean-philippe.brucker,
edgar.iglesias, linuc.decode, peterx
Now we have relevant helpers for queue and irq
management, let's implement MMIO write operations.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v7 -> v8:
- precise in the commit message invalidation commands
are not yet treated.
- use new queue helpers
- do not decode unhandled commands at this stage
---
hw/arm/smmuv3-internal.h | 24 +++++++---
hw/arm/smmuv3.c | 111 +++++++++++++++++++++++++++++++++++++++++++++--
hw/arm/trace-events | 6 +++
3 files changed, 132 insertions(+), 9 deletions(-)
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index 44564ed..799bce0 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -152,6 +152,25 @@ static inline uint64_t smmu_read64(uint64_t r, unsigned offset,
return extract64(r, offset << 3, 32);
}
+static inline void smmu_write64(uint64_t *r, unsigned offset,
+ unsigned size, uint64_t value)
+{
+ if (size == 8 && !offset) {
+ *r = value;
+ }
+
+ /* 32 bit access */
+
+ if (offset && offset != 4) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "SMMUv3 MMIO write: bad offset/size %u/%u\n",
+ offset, size);
+ return ;
+ }
+
+ *r = deposit64(*r, offset << 3, 32, value);
+}
+
/* Interrupts */
#define smmuv3_eventq_irq_enabled(s) \
@@ -159,9 +178,6 @@ static inline uint64_t smmu_read64(uint64_t r, unsigned offset,
#define smmuv3_gerror_irq_enabled(s) \
(FIELD_EX32(s->irq_ctrl, IRQ_CTRL, GERROR_IRQEN))
-void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq, uint32_t gerror_mask);
-void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t gerrorn);
-
/* Queue Handling */
#define LOG2SIZE(q) extract64((q)->base, 0, 5)
@@ -302,6 +318,4 @@ enum { /* Command completion notification */
addr; \
})
-int smmuv3_cmdq_consume(SMMUv3State *s);
-
#endif
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 79970d7..8e9eab2 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -37,7 +37,8 @@
* @irq: irq type
* @gerror_mask: mask of gerrors to toggle (relevant if @irq is GERROR)
*/
-void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq, uint32_t gerror_mask)
+static void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq,
+ uint32_t gerror_mask)
{
bool pulse = false;
@@ -75,7 +76,7 @@ void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq, uint32_t gerror_mask)
}
}
-void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t new_gerrorn)
+static void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t new_gerrorn)
{
uint32_t pending = s->gerror ^ s->gerrorn;
uint32_t toggled = s->gerrorn ^ new_gerrorn;
@@ -202,7 +203,7 @@ static void smmuv3_init_regs(SMMUv3State *s)
s->sid_split = 0;
}
-int smmuv3_cmdq_consume(SMMUv3State *s)
+static int smmuv3_cmdq_consume(SMMUv3State *s)
{
SMMUCmdError cmd_error = SMMU_CERROR_NONE;
SMMUQueue *q = &s->cmdq;
@@ -287,7 +288,109 @@ int smmuv3_cmdq_consume(SMMUv3State *s)
static void smmu_write_mmio(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
- /* not yet implemented */
+ SMMUState *sys = opaque;
+ SMMUv3State *s = ARM_SMMUV3(sys);
+
+ /* CONSTRAINED UNPREDICTABLE choice to have page0/1 be exact aliases */
+ addr &= ~0x10000;
+
+ if (size != 4 && size != 8) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "SMMUv3 MMIO write: bad size %u\n", size);
+ }
+
+ trace_smmuv3_write_mmio(addr, val, size);
+
+ switch (addr) {
+ case A_CR0:
+ s->cr[0] = val;
+ s->cr0ack = val;
+ /* in case the command queue has been enabled */
+ smmuv3_cmdq_consume(s);
+ return;
+ case A_CR1:
+ s->cr[1] = val;
+ return;
+ case A_CR2:
+ s->cr[2] = val;
+ return;
+ case A_IRQ_CTRL:
+ s->irq_ctrl = val;
+ return;
+ case A_GERRORN:
+ smmuv3_write_gerrorn(s, val);
+ /*
+ * By acknowledging the CMDQ_ERR, SW may notify cmds can
+ * be processed again
+ */
+ smmuv3_cmdq_consume(s);
+ return;
+ case A_GERROR_IRQ_CFG0: /* 64b */
+ smmu_write64(&s->gerror_irq_cfg0, 0, size, val);
+ return;
+ case A_GERROR_IRQ_CFG0 + 4:
+ smmu_write64(&s->gerror_irq_cfg0, 4, size, val);
+ return;
+ case A_GERROR_IRQ_CFG1:
+ s->gerror_irq_cfg1 = val;
+ return;
+ case A_GERROR_IRQ_CFG2:
+ s->gerror_irq_cfg2 = val;
+ return;
+ case A_STRTAB_BASE: /* 64b */
+ smmu_write64(&s->strtab_base, 0, size, val);
+ return;
+ case A_STRTAB_BASE + 4:
+ smmu_write64(&s->strtab_base, 4, size, val);
+ return;
+ case A_STRTAB_BASE_CFG:
+ s->strtab_base_cfg = val;
+ if (FIELD_EX32(val, STRTAB_BASE_CFG, FMT) == 1) {
+ s->sid_split = FIELD_EX32(val, STRTAB_BASE_CFG, SPLIT);
+ s->features |= SMMU_FEATURE_2LVL_STE;
+ }
+ return;
+ case A_CMDQ_BASE: /* 64b */
+ smmu_write64(&s->cmdq.base, 0, size, val);
+ return;
+ case A_CMDQ_BASE + 4: /* 64b */
+ smmu_write64(&s->cmdq.base, 4, size, val);
+ return;
+ case A_CMDQ_PROD:
+ s->cmdq.prod = val;
+ smmuv3_cmdq_consume(s);
+ return;
+ case A_CMDQ_CONS:
+ s->cmdq.cons = val;
+ return;
+ case A_EVENTQ_BASE: /* 64b */
+ smmu_write64(&s->eventq.base, 0, size, val);
+ return;
+ case A_EVENTQ_BASE + 4:
+ smmu_write64(&s->eventq.base, 4, size, val);
+ return;
+ case A_EVENTQ_PROD:
+ s->eventq.prod = val;
+ return;
+ case A_EVENTQ_CONS:
+ s->eventq.cons = val;
+ return;
+ case A_EVENTQ_IRQ_CFG0: /* 64b */
+ s->eventq.prod = val;
+ smmu_write64(&s->eventq_irq_cfg0, 0, size, val);
+ return;
+ case A_EVENTQ_IRQ_CFG0 + 4:
+ smmu_write64(&s->eventq_irq_cfg0, 4, size, val);
+ return;
+ case A_EVENTQ_IRQ_CFG1:
+ s->eventq_irq_cfg1 = val;
+ return;
+ case A_EVENTQ_IRQ_CFG2:
+ s->eventq_irq_cfg2 = val;
+ return;
+ default:
+ error_report("%s unhandled access at 0x%"PRIx64, __func__, addr);
+ }
}
static uint64_t smmu_read_mmio(void *opaque, hwaddr addr, unsigned size)
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
index d73e151..8a4acb9 100644
--- a/hw/arm/trace-events
+++ b/hw/arm/trace-events
@@ -24,3 +24,9 @@ smmuv3_unhandled_cmd(uint32_t type) "Unhandled command type=%d"
smmuv3_cmdq_consume(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "prod=%d cons=%d prod.wrap=%d cons.wrap=%d"
smmuv3_cmdq_opcode(const char *opcode) "<--- %s"
smmuv3_cmdq_consume_out(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "prod:%d, cons:%d, prod_wrap:%d, cons_wrap:%d "
+smmuv3_update(bool is_empty, uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "q empty:%d prod:%d cons:%d p.wrap:%d p.cons:%d"
+smmuv3_update_check_cmd(int error) "cmdq not enabled or error :0x%x"
+smmuv3_write_mmio(hwaddr addr, uint64_t val, unsigned size) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x"
+smmuv3_write_mmio_idr(hwaddr addr, uint64_t val) "write to RO/Unimpl reg 0x%lx val64:0x%lx"
+smmuv3_write_mmio_evtq_cons_bef_clear(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "Before clearing interrupt prod:0x%x cons:0x%x prod.w:%d cons.w:%d"
+smmuv3_write_mmio_evtq_cons_after_clear(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "after clearing interrupt prod:0x%x cons:0x%x prod.w:%d cons.w:%d"
--
2.5.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v8 08/14] hw/arm/smmuv3: Event queue recording helper
2018-02-05 13:39 [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support Eric Auger
` (6 preceding siblings ...)
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 07/14] hw/arm/smmuv3: Implement MMIO write operations Eric Auger
@ 2018-02-05 13:39 ` Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 09/14] hw/arm/smmuv3: Implement translate callback Eric Auger
` (6 subsequent siblings)
14 siblings, 0 replies; 18+ messages in thread
From: Eric Auger @ 2018-02-05 13:39 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, peter.maydell, qemu-arm, qemu-devel,
prem.mallappa, alex.williamson
Cc: tn, mst, christoffer.dall, bharat.bhushan, jean-philippe.brucker,
edgar.iglesias, linuc.decode, peterx
Let's introduce a helper function aiming at recording an
event in the event queue.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v7 -> v8:
- use dma_addr_t instead of hwaddr in smmuv3_record_event()
- introduce struct SMMUEventInfo
- add event_stringify + helpers for all fields
---
hw/arm/smmuv3-internal.h | 136 ++++++++++++++++++++++++++++++++++++++++++++++-
hw/arm/smmuv3.c | 91 ++++++++++++++++++++++++++++++-
hw/arm/trace-events | 1 +
3 files changed, 225 insertions(+), 3 deletions(-)
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index 799bce0..2ed7f1e 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -220,8 +220,6 @@ static inline void smmu_write_cmdq_err(SMMUv3State *s, uint32_t err_type)
s->cmdq.cons = FIELD_DP32(s->cmdq.cons, CMDQ_CONS, ERR, err_type);
}
-void smmuv3_write_eventq(SMMUv3State *s, Evt *evt);
-
/* Commands */
enum {
@@ -318,4 +316,138 @@ enum { /* Command completion notification */
addr; \
})
+/* Events */
+
+typedef enum SMMUEventType {
+ SMMU_EVT_OK = 0x00,
+ SMMU_EVT_F_UUT = 0x01,
+ SMMU_EVT_C_BAD_STREAMID = 0x02,
+ SMMU_EVT_F_STE_FETCH = 0x03,
+ SMMU_EVT_C_BAD_STE = 0x04,
+ SMMU_EVT_F_BAD_ATS_TREQ = 0x05,
+ SMMU_EVT_F_STREAM_DISABLED = 0x06,
+ SMMU_EVT_F_TRANS_FORBIDDEN = 0x07,
+ SMMU_EVT_C_BAD_SUBSTREAMID = 0x08,
+ SMMU_EVT_F_CD_FETCH = 0x09,
+ SMMU_EVT_C_BAD_CD = 0x0a,
+ SMMU_EVT_F_WALK_EABT = 0x0b,
+ SMMU_EVT_F_TRANSLATION = 0x10,
+ SMMU_EVT_F_ADDR_SIZE = 0x11,
+ SMMU_EVT_F_ACCESS = 0x12,
+ SMMU_EVT_F_PERMISSION = 0x13,
+ SMMU_EVT_F_TLB_CONFLICT = 0x20,
+ SMMU_EVT_F_CFG_CONFLICT = 0x21,
+ SMMU_EVT_E_PAGE_REQ = 0x24,
+} SMMUEventType;
+
+static const char *event_stringify[] = {
+ [SMMU_EVT_OK] = "SMMU_EVT_OK",
+ [SMMU_EVT_F_UUT] = "SMMU_EVT_F_UUT",
+ [SMMU_EVT_C_BAD_STREAMID] = "SMMU_EVT_C_BAD_STREAMID",
+ [SMMU_EVT_F_STE_FETCH] = "SMMU_EVT_F_STE_FETCH",
+ [SMMU_EVT_C_BAD_STE] = "SMMU_EVT_C_BAD_STE",
+ [SMMU_EVT_F_BAD_ATS_TREQ] = "SMMU_EVT_F_BAD_ATS_TREQ",
+ [SMMU_EVT_F_STREAM_DISABLED] = "SMMU_EVT_F_STREAM_DISABLED",
+ [SMMU_EVT_F_TRANS_FORBIDDEN] = "SMMU_EVT_F_TRANS_FORBIDDEN",
+ [SMMU_EVT_C_BAD_SUBSTREAMID] = "SMMU_EVT_C_BAD_SUBSTREAMID",
+ [SMMU_EVT_F_CD_FETCH] = "SMMU_EVT_F_CD_FETCH",
+ [SMMU_EVT_C_BAD_CD] = "SMMU_EVT_C_BAD_CD",
+ [SMMU_EVT_F_WALK_EABT] = "SMMU_EVT_F_WALK_EABT",
+ [SMMU_EVT_F_TRANSLATION] = "SMMU_EVT_F_TRANSLATION",
+ [SMMU_EVT_F_ADDR_SIZE] = "SMMU_EVT_F_ADDR_SIZE",
+ [SMMU_EVT_F_ACCESS] = "SMMU_EVT_F_ACCESS",
+ [SMMU_EVT_F_PERMISSION] = "SMMU_EVT_F_PERMISSION",
+ [SMMU_EVT_F_TLB_CONFLICT] = "SMMU_EVT_F_TLB_CONFLICT",
+ [SMMU_EVT_F_CFG_CONFLICT] = "SMMU_EVT_F_CFG_CONFLICT",
+ [SMMU_EVT_E_PAGE_REQ] = "SMMU_EVT_E_PAGE_REQ",
+};
+
+typedef struct SMMUEventInfo {
+ SMMUEventType type;
+ uint32_t sid;
+ bool recorded;
+ bool record_trans_faults;
+ union {
+ struct {
+ uint32_t ssid;
+ bool ssv;
+ dma_addr_t addr;
+ bool rnw;
+ bool pnu;
+ bool ind;
+ } f_uut;
+ struct ssid_info {
+ uint32_t ssid;
+ bool ssv;
+ } c_bad_streamid;
+ struct ssid_addr_info {
+ uint32_t ssid;
+ bool ssv;
+ dma_addr_t addr;
+ } f_ste_fetch;
+ struct ssid_info c_bad_ste;
+ struct {
+ dma_addr_t addr;
+ bool rnw;
+ } f_transl_forbidden;
+ struct {
+ uint32_t ssid;
+ } c_bad_substream;
+ struct ssid_addr_info f_cd_fetch;
+ struct ssid_info c_bad_cd;
+ struct full_info {
+ bool stall;
+ uint16_t stag;
+ uint32_t ssid;
+ bool ssv;
+ bool s2;
+ dma_addr_t addr;
+ bool rnw;
+ bool pnu;
+ bool ind;
+ uint8_t class;
+ dma_addr_t addr2;
+ } f_walk_eabt;
+ struct full_info f_translation;
+ struct full_info f_addr_size;
+ struct full_info f_access;
+ struct full_info f_permission;
+ struct ssid_info f_cfg_conflict;
+ /**
+ * not supported yet:
+ * F_BAD_ATS_TREQ
+ * F_BAD_ATS_TREQ
+ * F_TLB_CONFLICT
+ * E_PAGE_REQUEST
+ * IMPDEF_EVENTn
+ */
+ } u;
+} SMMUEventInfo;
+
+/* EVTQ fields */
+
+#define EVT_Q_OVERFLOW (1 << 31)
+
+#define EVT_SET_TYPE(x, v) deposit32((x)->word[0], 0 , 8 , v)
+#define EVT_SET_SSV(x, v) deposit32((x)->word[0], 11, 1 , v)
+#define EVT_SET_SSID(x, v) deposit32((x)->word[0], 12, 20, v)
+#define EVT_SET_SID(x, v) ((x)->word[1] = v)
+#define EVT_SET_STAG(x, v) deposit32((x)->word[2], 0 , 16, v)
+#define EVT_SET_STALL(x, v) deposit32((x)->word[2], 31, 1 , v)
+#define EVT_SET_PNU(x, v) deposit32((x)->word[3], 1 , 1 , v)
+#define EVT_SET_IND(x, v) deposit32((x)->word[3], 2 , 1 , v)
+#define EVT_SET_RNW(x, v) deposit32((x)->word[3], 3 , 1 , v)
+#define EVT_SET_S2(x, v) deposit32((x)->word[3], 7 , 1 , v)
+#define EVT_SET_CLASS(x, v) deposit32((x)->word[3], 8 , 2 , v)
+#define EVT_SET_ADDR(x, addr) ({ \
+ (x)->word[5] = (uint32_t)(addr >> 32); \
+ (x)->word[4] = (uint32_t)(addr & 0xffffffff); \
+ })
+#define EVT_SET_ADDR2(x, addr) ({ \
+ deposit32((x)->word[7], 3, 29, addr >> 16); \
+ deposit32((x)->word[7], 0, 16, addr & 0xffff); \
+ })
+
+void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event);
+
#endif
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 8e9eab2..a90468d 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -143,7 +143,7 @@ static inline MemTxResult smmuv3_read_cmdq(SMMUv3State *s, Cmd *cmd)
return smmu_queue_read(q, cmd);
}
-void smmuv3_write_eventq(SMMUv3State *s, Evt *evt)
+static void smmuv3_write_eventq(SMMUv3State *s, Evt *evt)
{
SMMUQueue *q = &s->eventq;
bool q_empty = Q_EMPTY(q);
@@ -164,6 +164,95 @@ void smmuv3_write_eventq(SMMUv3State *s, Evt *evt)
}
}
+void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *info)
+{
+ Evt evt;
+
+ if (!SMMUV3_EVENTQ_ENABLED(s)) {
+ return;
+ }
+
+ EVT_SET_TYPE(&evt, info->type);
+ EVT_SET_SID(&evt, info->sid);
+
+ switch (info->type) {
+ case SMMU_EVT_OK:
+ return;
+ case SMMU_EVT_F_UUT:
+ EVT_SET_SSID(&evt, info->u.f_uut.ssid);
+ EVT_SET_SSV(&evt, info->u.f_uut.ssv);
+ EVT_SET_ADDR(&evt, info->u.f_uut.addr);
+ EVT_SET_RNW(&evt, info->u.f_uut.rnw);
+ EVT_SET_PNU(&evt, info->u.f_uut.pnu);
+ EVT_SET_IND(&evt, info->u.f_uut.ind);
+ break;
+ case SMMU_EVT_C_BAD_STREAMID:
+ EVT_SET_SSID(&evt, info->u.c_bad_streamid.ssid);
+ EVT_SET_SSV(&evt, info->u.c_bad_streamid.ssv);
+ break;
+ case SMMU_EVT_F_STE_FETCH:
+ EVT_SET_SSID(&evt, info->u.f_ste_fetch.ssid);
+ EVT_SET_SSV(&evt, info->u.f_ste_fetch.ssv);
+ EVT_SET_ADDR(&evt, info->u.f_ste_fetch.addr);
+ break;
+ case SMMU_EVT_C_BAD_STE:
+ EVT_SET_SSID(&evt, info->u.c_bad_ste.ssid);
+ EVT_SET_SSV(&evt, info->u.c_bad_ste.ssv);
+ break;
+ case SMMU_EVT_F_STREAM_DISABLED:
+ break;
+ case SMMU_EVT_F_TRANS_FORBIDDEN:
+ EVT_SET_ADDR(&evt, info->u.f_transl_forbidden.addr);
+ EVT_SET_RNW(&evt, info->u.f_transl_forbidden.rnw);
+ break;
+ case SMMU_EVT_C_BAD_SUBSTREAMID:
+ EVT_SET_SSID(&evt, info->u.c_bad_substream.ssid);
+ break;
+ case SMMU_EVT_F_CD_FETCH:
+ EVT_SET_SSID(&evt, info->u.f_cd_fetch.ssid);
+ EVT_SET_SSV(&evt, info->u.f_cd_fetch.ssv);
+ EVT_SET_ADDR(&evt, info->u.f_cd_fetch.addr);
+ break;
+ case SMMU_EVT_C_BAD_CD:
+ EVT_SET_SSID(&evt, info->u.c_bad_cd.ssid);
+ EVT_SET_SSV(&evt, info->u.c_bad_cd.ssv);
+ break;
+ case SMMU_EVT_F_WALK_EABT:
+ case SMMU_EVT_F_TRANSLATION:
+ case SMMU_EVT_F_ADDR_SIZE:
+ case SMMU_EVT_F_ACCESS:
+ case SMMU_EVT_F_PERMISSION:
+ EVT_SET_STALL(&evt, info->u.f_walk_eabt.stall);
+ EVT_SET_STAG(&evt, info->u.f_walk_eabt.stag);
+ EVT_SET_SSID(&evt, info->u.f_walk_eabt.ssid);
+ EVT_SET_SSV(&evt, info->u.f_walk_eabt.ssv);
+ EVT_SET_S2(&evt, info->u.f_walk_eabt.s2);
+ EVT_SET_ADDR(&evt, info->u.f_walk_eabt.addr);
+ EVT_SET_RNW(&evt, info->u.f_walk_eabt.rnw);
+ EVT_SET_PNU(&evt, info->u.f_walk_eabt.pnu);
+ EVT_SET_IND(&evt, info->u.f_walk_eabt.ind);
+ EVT_SET_CLASS(&evt, info->u.f_walk_eabt.class);
+ EVT_SET_ADDR2(&evt, info->u.f_walk_eabt.addr2);
+ break;
+ case SMMU_EVT_F_CFG_CONFLICT:
+ EVT_SET_SSID(&evt, info->u.f_cfg_conflict.ssid);
+ EVT_SET_SSV(&evt, info->u.f_cfg_conflict.ssv);
+ break;
+ /* rest is not implemented */
+ case SMMU_EVT_F_BAD_ATS_TREQ:
+ case SMMU_EVT_F_TLB_CONFLICT:
+ case SMMU_EVT_E_PAGE_REQ:
+ default:
+ error_report("%s event %d not supported", __func__,
+ info->type);
+ return;
+ }
+
+ trace_smmuv3_record_event(event_stringify[info->type], info->sid);
+ smmuv3_write_eventq(s, &evt);
+ info->recorded = true;
+}
+
static void smmuv3_init_regs(SMMUv3State *s)
{
/**
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
index 8a4acb9..f6757c1 100644
--- a/hw/arm/trace-events
+++ b/hw/arm/trace-events
@@ -30,3 +30,4 @@ smmuv3_write_mmio(hwaddr addr, uint64_t val, unsigned size) "addr: 0x%"PRIx64" v
smmuv3_write_mmio_idr(hwaddr addr, uint64_t val) "write to RO/Unimpl reg 0x%lx val64:0x%lx"
smmuv3_write_mmio_evtq_cons_bef_clear(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "Before clearing interrupt prod:0x%x cons:0x%x prod.w:%d cons.w:%d"
smmuv3_write_mmio_evtq_cons_after_clear(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "after clearing interrupt prod:0x%x cons:0x%x prod.w:%d cons.w:%d"
+smmuv3_record_event(const char *type, uint32_t sid) "%s sid=%d"
--
2.5.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v8 09/14] hw/arm/smmuv3: Implement translate callback
2018-02-05 13:39 [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support Eric Auger
` (7 preceding siblings ...)
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 08/14] hw/arm/smmuv3: Event queue recording helper Eric Auger
@ 2018-02-05 13:39 ` Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 10/14] hw/arm/smmuv3: Abort on vfio or vhost case Eric Auger
` (5 subsequent siblings)
14 siblings, 0 replies; 18+ messages in thread
From: Eric Auger @ 2018-02-05 13:39 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, peter.maydell, qemu-arm, qemu-devel,
prem.mallappa, alex.williamson
Cc: tn, mst, christoffer.dall, bharat.bhushan, jean-philippe.brucker,
edgar.iglesias, linuc.decode, peterx
This patch implements the IOMMU Memory Region translate()
callback. Most of the code relates to the translation
configuration decoding and check (STE, CD).
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v7 -> v8:
- use address_space_rw
- s/Ste/STE, s/Cd/CD
- use dma_memory_read
- remove everything related to stage 2
- collect data for both TTx
- renamings
- pass the event handle all along the config decoding path
- decode tbi, ars
---
hw/arm/smmuv3-internal.h | 146 +++++++++++++++++++++
hw/arm/smmuv3.c | 326 +++++++++++++++++++++++++++++++++++++++++++++++
hw/arm/trace-events | 9 ++
3 files changed, 481 insertions(+)
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index 2ed7f1e..853dd93 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -450,4 +450,150 @@ typedef struct SMMUEventInfo {
void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event);
+/* Configuration Data */
+
+/* STE Level 1 Descriptor */
+typedef struct STEDesc {
+ uint32_t word[2];
+} STEDesc;
+
+/* CD Level 1 Descriptor */
+typedef struct CDDesc {
+ uint32_t word[2];
+} CDDesc;
+
+/* Stream Table Entry(STE) */
+typedef struct STE {
+ uint32_t word[16];
+} STE;
+
+/* Context Descriptor(CD) */
+typedef struct CD {
+ uint32_t word[16];
+} CD;
+
+/* STE fields */
+
+#define STE_VALID(x) extract32((x)->word[0], 0, 1) /* 0 */
+
+#define STE_CONFIG(x) extract32((x)->word[0], 1, 3)
+#define STE_CFG_S1_ENABLED(config) (config & 0x1)
+#define STE_CFG_S2_ENABLED(config) (config & 0x2)
+#define STE_CFG_ABORT(config) (!(config & 0x4))
+#define STE_CFG_BYPASS(config) (config == 0x4)
+
+#define STE_S1FMT(x) extract32((x)->word[0], 4 , 2)
+#define STE_S1CDMAX(x) extract32((x)->word[1], 27, 5)
+#define STE_EATS(x) extract32((x)->word[2], 28, 2)
+#define STE_STRW(x) extract32((x)->word[2], 30, 2)
+#define STE_S2VMID(x) extract32((x)->word[4], 0 , 16)
+#define STE_S2T0SZ(x) extract32((x)->word[5], 0 , 6)
+#define STE_S2SL0(x) extract32((x)->word[5], 6 , 2)
+#define STE_S2TG(x) extract32((x)->word[5], 14, 2)
+#define STE_S2PS(x) extract32((x)->word[5], 16, 3)
+#define STE_S2AA64(x) extract32((x)->word[5], 19, 1)
+#define STE_S2HD(x) extract32((x)->word[5], 24, 1)
+#define STE_S2HA(x) extract32((x)->word[5], 25, 1)
+#define STE_S2S(x) extract32((x)->word[5], 26, 1)
+#define STE_CTXPTR(x) \
+ ({ \
+ unsigned long addr; \
+ addr = (uint64_t)extract32((x)->word[1], 0, 16) << 32; \
+ addr |= (uint64_t)((x)->word[0] & 0xffffffc0); \
+ addr; \
+ })
+
+#define STE_S2TTB(x) \
+ ({ \
+ unsigned long addr; \
+ addr = (uint64_t)extract32((x)->word[7], 0, 16) << 32; \
+ addr |= (uint64_t)((x)->word[6] & 0xfffffff0); \
+ addr; \
+ })
+
+static inline int oas2bits(int oas_field)
+{
+ switch (oas_field) {
+ case 0b011:
+ return 42;
+ case 0b100:
+ return 44;
+ default:
+ return 32 + (1 << oas_field);
+ }
+}
+
+static inline int pa_range(STE *ste)
+{
+ int oas_field = MIN(STE_S2PS(ste), SMMU_IDR5_OAS);
+
+ if (!STE_S2AA64(ste)) {
+ return 40;
+ }
+
+ return oas2bits(oas_field);
+}
+
+#define MAX_PA(ste) ((1 << pa_range(ste)) - 1)
+
+/* CD fields */
+
+#define CD_VALID(x) extract32((x)->word[0], 30, 1)
+#define CD_ASID(x) extract32((x)->word[1], 16, 16)
+#define CD_TTB(x, sel) \
+ ({ \
+ uint64_t hi, lo; \
+ hi = extract32((x)->word[(sel) * 2 + 3], 0, 16); \
+ hi <<= 32; \
+ lo = (x)->word[(sel) * 2 + 2] & ~0xf; \
+ hi | lo; \
+ })
+
+#define CD_TSZ(x, sel) extract32((x)->word[0], (16 * (sel)) + 0, 6)
+#define CD_TG(x, sel) extract32((x)->word[0], (16 * (sel)) + 6, 2)
+#define CD_EPD(x, sel) extract32((x)->word[0], (16 * (sel)) + 14, 1)
+#define CD_ENDI(x) extract32((x)->word[0], 15, 1)
+#define CD_IPS(x) extract32((x)->word[1], 0 , 3)
+#define CD_TBI(x) extract32((x)->word[1], 6 , 2)
+#define CD_S(x) extract32((x)->word[1], 12, 1)
+#define CD_R(x) extract32((x)->word[1], 13, 1)
+#define CD_A(x) extract32((x)->word[1], 14, 1)
+#define CD_AARCH64(x) extract32((x)->word[1], 9 , 1)
+
+#define CDM_VALID(x) ((x)->word[0] & 0x1)
+
+static inline int is_cd_valid(SMMUv3State *s, STE *ste, CD *cd)
+{
+ return CD_VALID(cd);
+}
+
+/**
+ * tg2granule - Decodes the CD translation granule size field according
+ * to the ttbr in use
+ * @bits: TG0/1 fields
+ * @ttbr: ttbr index in use
+ */
+static inline int tg2granule(int bits, int ttbr)
+{
+ switch (bits) {
+ case 1:
+ return ttbr ? 14 : 16;
+ case 2:
+ return ttbr ? 12 : 14;
+ case 3:
+ return ttbr ? 16 : 12;
+ default:
+ return 12;
+ }
+}
+
+#define L1STD_L2PTR(stm) ({ \
+ uint64_t hi, lo; \
+ hi = (stm)->word[1]; \
+ lo = (stm)->word[0] & ~(uint64_t)0x1f; \
+ hi << 32 | lo; \
+ })
+
+#define L1STD_SPAN(stm) (extract32((stm)->word[0], 0, 4))
+
#endif
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index a90468d..da05d47 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -292,6 +292,329 @@ static void smmuv3_init_regs(SMMUv3State *s)
s->sid_split = 0;
}
+static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
+ SMMUEventInfo *event)
+{
+ int ret;
+
+ trace_smmuv3_get_ste(addr);
+ ret = dma_memory_read(&address_space_memory, addr,
+ (void *)buf, sizeof(*buf));
+ if (ret != MEMTX_OK) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Cannot fetch pte at address=0x%"PRIx64"\n", addr);
+ event->type = SMMU_EVT_F_STE_FETCH;
+ event->u.f_ste_fetch.addr = addr;
+ return -EINVAL;
+ }
+ return 0;
+
+}
+
+/* @ssid > 0 not supported yet */
+static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid,
+ CD *buf, SMMUEventInfo *event)
+{
+ dma_addr_t addr = STE_CTXPTR(ste);
+ int ret;
+
+ trace_smmuv3_get_cd(addr);
+ ret = dma_memory_read(&address_space_memory, addr,
+ (void *)buf, sizeof(*buf));
+ if (ret != MEMTX_OK) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Cannot fetch pte at address=0x%"PRIx64"\n", addr);
+ event->type = SMMU_EVT_F_CD_FETCH;
+ event->u.f_ste_fetch.addr = addr;
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg,
+ STE *ste, SMMUEventInfo *event)
+{
+ uint32_t config = STE_CONFIG(ste);
+ int ret = -EINVAL;
+
+ if (STE_CFG_ABORT(config)) {
+ /* abort but don't record any event */
+ cfg->aborted = true;
+ return ret;
+ }
+
+ if (STE_CFG_BYPASS(config)) {
+ cfg->bypassed = true;
+ return ret;
+ }
+
+ if (!STE_VALID(ste)) {
+ goto bad_ste;
+ }
+
+ if (STE_CFG_S2_ENABLED(config)) {
+ error_setg(&error_fatal, "SMMUv3 does not support stage 2 yet");
+ }
+
+ if (STE_S1CDMAX(ste) != 0) {
+ error_setg(&error_fatal,
+ "SMMUv3 does not support multiple context descriptors yet");
+ goto bad_ste;
+ }
+ return 0;
+
+bad_ste:
+ event->type = SMMU_EVT_C_BAD_STE;
+ return -EINVAL;
+}
+
+/**
+ * smmu_find_ste - Return the stream table entry associated
+ * to the sid
+ *
+ * @s: smmuv3 handle
+ * @sid: stream ID
+ * @ste: returned stream table entry
+ * @event: handle to an event info
+ *
+ * Supports linear and 2-level stream table
+ * Return 0 on success, -EINVAL otherwise
+ */
+static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste,
+ SMMUEventInfo *event)
+{
+ dma_addr_t addr;
+ int ret;
+
+ trace_smmuv3_find_ste(sid, s->features, s->sid_split);
+ /* Check SID range */
+ if (sid > (1 << SMMU_IDR1_SIDSIZE)) {
+ event->type = SMMU_EVT_C_BAD_STREAMID;
+ return -EINVAL;
+ }
+ if (s->features & SMMU_FEATURE_2LVL_STE) {
+ int l1_ste_offset, l2_ste_offset, max_l2_ste, span;
+ dma_addr_t strtab_base, l1ptr, l2ptr;
+ STEDesc l1std;
+
+ strtab_base = s->strtab_base & SMMU_BASE_ADDR_MASK;
+ l1_ste_offset = sid >> s->sid_split;
+ l2_ste_offset = sid & ((1 << s->sid_split) - 1);
+ l1ptr = (dma_addr_t)(strtab_base + l1_ste_offset * sizeof(l1std));
+ ret = dma_memory_read(&address_space_memory, l1ptr,
+ (uint8_t *)&l1std, sizeof(l1std));
+ if (ret != MEMTX_OK) {
+ error_report("Could not read L1PTR at 0X%"PRIx64, l1ptr);
+ event->type = SMMU_EVT_F_STE_FETCH;
+ event->u.f_ste_fetch.addr = l1ptr;
+ return -EINVAL;
+ }
+
+ span = L1STD_SPAN(&l1std);
+
+ if (!span) {
+ /* l2ptr is not valid */
+ error_report("invalid sid=%d (L1STD span=0)", sid);
+ event->type = SMMU_EVT_C_BAD_STREAMID;
+ return -EINVAL;
+ }
+ max_l2_ste = (1 << span) - 1;
+ l2ptr = L1STD_L2PTR(&l1std);
+ trace_smmuv3_find_ste_2lvl(s->strtab_base, l1ptr, l1_ste_offset,
+ l2ptr, l2_ste_offset, max_l2_ste);
+ if (l2_ste_offset > max_l2_ste) {
+ error_report("l2_ste_offset=%d > max_l2_ste=%d",
+ l2_ste_offset, max_l2_ste);
+ event->type = SMMU_EVT_C_BAD_STE;
+ return -EINVAL;
+ }
+ addr = L1STD_L2PTR(&l1std) + l2_ste_offset * sizeof(*ste);
+ } else {
+ addr = s->strtab_base + sid * sizeof(*ste);
+ }
+
+ if (smmu_get_ste(s, addr, ste, event)) {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event)
+{
+ int ret = -EINVAL;
+ int i;
+
+ if (!CD_VALID(cd) || !CD_AARCH64(cd)) {
+ goto error;
+ }
+
+ /* we support only those at the moment */
+ cfg->aa64 = true;
+ cfg->stage = 1;
+
+ cfg->oas = oas2bits(CD_IPS(cd));
+ cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas);
+ cfg->tbi = CD_TBI(cd);
+
+ trace_smmuv3_decode_cd(cfg->oas);
+
+ /* decode data dependent on TT */
+ for (i = 0; i <= 1; i++) {
+ int tg, tsz;
+ SMMUTransTableInfo *tt = &cfg->tt[i];
+
+ cfg->tt[i].disabled = CD_EPD(cd, i);
+ if (cfg->tt[i].disabled) {
+ continue;
+ }
+
+ tsz = CD_TSZ(cd, i);
+ if (tsz < 16 || tsz > 39) {
+ goto error;
+ }
+
+ tg = CD_TG(cd, i);
+ tt->granule_sz = tg2granule(tg, i);
+ if ((tt->granule_sz != 12 && tt->granule_sz != 16) || CD_ENDI(cd)) {
+ goto error;
+ }
+
+ tt->tsz = tsz;
+ tt->initial_level = 4 - (64 - tsz - 4) / (tt->granule_sz - 3);
+ tt->ttb = CD_TTB(cd, i);
+ tt->ttb = extract64(tt->ttb, 0, cfg->oas);
+ trace_smmuv3_decode_cd_tt(i, tt->tsz, tt->ttb,
+ tt->granule_sz, tt->initial_level);
+ }
+
+ event->record_trans_faults = CD_R(cd);
+
+ return 0;
+
+error:
+ event->type = SMMU_EVT_C_BAD_CD;
+ return ret;
+}
+
+/**
+ * smmuv3_decode_config - Prepare the translation configuration
+ * for the @mr iommu region
+ * @mr: iommu memory region the translation config must be prepared for
+ * @cfg: output translation configuration which is populated through
+ * the different configuration decodng steps
+ * @event: must be zero'ed by the caller
+ *
+ * return < 0 if the translation needs to be aborted (@event is filled
+ * accordingly). Return 0 otherwise.
+ */
+static int smmuv3_decode_config(IOMMUMemoryRegion *mr, SMMUTransCfg *cfg,
+ SMMUEventInfo *event)
+{
+ SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu);
+ uint32_t sid = smmu_get_sid(sdev);
+ SMMUv3State *s = sdev->smmu;
+ int ret = -EINVAL;
+ STE ste;
+ CD cd;
+
+ if (smmu_find_ste(s, sid, &ste, event)) {
+ return ret;
+ }
+
+ if (decode_ste(s, cfg, &ste, event)) {
+ return ret;
+ }
+
+ if (smmu_get_cd(s, &ste, 0 /* ssid */, &cd, event)) {
+ return ret;
+ }
+
+ return decode_cd(cfg, &cd, event);
+}
+
+static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
+ IOMMUAccessFlags flag)
+{
+ SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu);
+ SMMUv3State *s = sdev->smmu;
+ uint16_t sid = smmu_get_sid(sdev);
+ SMMUEventInfo event = {.type = SMMU_EVT_OK, .sid = sid};
+ SMMUPTWEventInfo ptw_info = {};
+ SMMUTransCfg cfg = {};
+ IOMMUTLBEntry entry = {
+ .target_as = &address_space_memory,
+ .iova = addr,
+ .translated_addr = addr,
+ .addr_mask = ~(hwaddr)0,
+ .perm = flag,
+ };
+
+ if (!smmu_enabled(s)) {
+ goto out;
+ }
+
+ if (smmuv3_decode_config(mr, &cfg, &event)) {
+ goto out;
+ }
+
+ if (smmu_ptw(&cfg, &entry, &ptw_info)) {
+ switch (ptw_info.type) {
+ case SMMU_PTW_ERR_WALK_EABT:
+ event.type = SMMU_EVT_F_WALK_EABT;
+ event.u.f_walk_eabt.addr = addr;
+ event.u.f_walk_eabt.rnw = flag & 0x1;
+ event.u.f_walk_eabt.class = 0x1;
+ event.u.f_walk_eabt.addr2 = ptw_info.addr;
+ break;
+ case SMMU_PTW_ERR_TRANSLATION:
+ if (event.record_trans_faults) {
+ event.type = SMMU_EVT_F_TRANSLATION;
+ event.u.f_translation.addr = addr;
+ event.u.f_translation.rnw = flag & 0x1;
+ }
+ break;
+ case SMMU_PTW_ERR_ADDR_SIZE:
+ if (event.record_trans_faults) {
+ event.type = SMMU_EVT_F_ADDR_SIZE;
+ event.u.f_addr_size.addr = addr;
+ event.u.f_addr_size.rnw = flag & 0x1;
+ }
+ break;
+ case SMMU_PTW_ERR_ACCESS:
+ if (event.record_trans_faults) {
+ event.type = SMMU_EVT_F_ACCESS;
+ event.u.f_access.addr = addr;
+ event.u.f_access.rnw = flag & 0x1;
+ }
+ break;
+ case SMMU_PTW_ERR_PERMISSION:
+ if (event.record_trans_faults) {
+ event.type = SMMU_EVT_F_PERMISSION;
+ event.u.f_permission.addr = addr;
+ event.u.f_permission.rnw = flag & 0x1;
+ }
+ break;
+ default:
+ error_setg(&error_fatal, "SMMUV3 BUG");
+ }
+ }
+
+ trace_smmuv3_translate(mr->parent_obj.name, sid, addr,
+ entry.translated_addr, entry.perm);
+out:
+ if (event.type) {
+ error_report("%s translation failed for iova=0x%"PRIx64" (%s)",
+ mr->parent_obj.name, addr, event_stringify[event.type]);
+ entry.perm = IOMMU_NONE;
+ smmuv3_record_event(s, &event);
+ }
+ if (cfg.aborted) {
+ entry.perm = IOMMU_NONE;
+ }
+ return entry;
+}
+
static int smmuv3_cmdq_consume(SMMUv3State *s)
{
SMMUCmdError cmd_error = SMMU_CERROR_NONE;
@@ -724,6 +1047,9 @@ static void smmuv3_class_init(ObjectClass *klass, void *data)
static void smmuv3_iommu_memory_region_class_init(ObjectClass *klass,
void *data)
{
+ IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
+
+ imrc->translate = smmuv3_translate;
}
static const TypeInfo smmuv3_type_info = {
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
index f6757c1..ec335c1 100644
--- a/hw/arm/trace-events
+++ b/hw/arm/trace-events
@@ -31,3 +31,12 @@ smmuv3_write_mmio_idr(hwaddr addr, uint64_t val) "write to RO/Unimpl reg 0x%lx v
smmuv3_write_mmio_evtq_cons_bef_clear(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "Before clearing interrupt prod:0x%x cons:0x%x prod.w:%d cons.w:%d"
smmuv3_write_mmio_evtq_cons_after_clear(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "after clearing interrupt prod:0x%x cons:0x%x prod.w:%d cons.w:%d"
smmuv3_record_event(const char *type, uint32_t sid) "%s sid=%d"
+smmuv3_find_ste(uint16_t sid, uint32_t features, uint16_t sid_split) "SID:0x%x features:0x%x, sid_split:0x%x"
+smmuv3_find_ste_2lvl(uint64_t strtab_base, hwaddr l1ptr, int l1_ste_offset, hwaddr l2ptr, int l2_ste_offset, int max_l2_ste) "strtab_base:0x%lx l1ptr:0x%"PRIx64" l1_off:0x%x, l2ptr:0x%"PRIx64" l2_off:0x%x max_l2_ste:%d"
+smmuv3_get_ste(hwaddr addr) "STE addr: 0x%"PRIx64
+smmuv3_translate_bypass(const char *n, uint16_t sid, hwaddr addr, bool is_write) "%s sid=%d bypass iova:0x%"PRIx64" is_write=%d"
+smmuv3_translate_in(uint16_t sid, int pci_bus_num, hwaddr strtab_base) "SID:0x%x bus:%d strtab_base:0x%"PRIx64
+smmuv3_get_cd(hwaddr addr) "CD addr: 0x%"PRIx64
+smmuv3_translate(const char *n, uint16_t sid, hwaddr iova, hwaddr translated, int perm) "%s sid=%d iova=0x%"PRIx64" translated=0x%"PRIx64" perm=0x%x"
+smmuv3_decode_cd(uint32_t oas) "oas=%d"
+smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz, int initial_level) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d, initial_level = %d"
--
2.5.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v8 10/14] hw/arm/smmuv3: Abort on vfio or vhost case
2018-02-05 13:39 [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support Eric Auger
` (8 preceding siblings ...)
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 09/14] hw/arm/smmuv3: Implement translate callback Eric Auger
@ 2018-02-05 13:39 ` Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 11/14] target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route Eric Auger
` (4 subsequent siblings)
14 siblings, 0 replies; 18+ messages in thread
From: Eric Auger @ 2018-02-05 13:39 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, peter.maydell, qemu-arm, qemu-devel,
prem.mallappa, alex.williamson
Cc: tn, mst, christoffer.dall, bharat.bhushan, jean-philippe.brucker,
edgar.iglesias, linuc.decode, peterx
At the moment, the SMMUv3 does not support notification on
TLB invalidation. So let's abort as soon as such notifier gets
enabled.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
hw/arm/smmuv3.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index da05d47..0753208 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -1044,12 +1044,23 @@ static void smmuv3_class_init(ObjectClass *klass, void *data)
dc->realize = smmu_realize;
}
+static void smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu,
+ IOMMUNotifierFlag old,
+ IOMMUNotifierFlag new)
+{
+ if (old == IOMMU_NOTIFIER_NONE) {
+ error_setg(&error_fatal,
+ "SMMUV3: vhost and vfio notifiers not yet supported");
+ }
+}
+
static void smmuv3_iommu_memory_region_class_init(ObjectClass *klass,
void *data)
{
IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
imrc->translate = smmuv3_translate;
+ imrc->notify_flag_changed = smmuv3_notify_flag_changed;
}
static const TypeInfo smmuv3_type_info = {
--
2.5.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v8 11/14] target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route
2018-02-05 13:39 [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support Eric Auger
` (9 preceding siblings ...)
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 10/14] hw/arm/smmuv3: Abort on vfio or vhost case Eric Auger
@ 2018-02-05 13:39 ` Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 12/14] hw/arm/virt: Add SMMUv3 to the virt board Eric Auger
` (3 subsequent siblings)
14 siblings, 0 replies; 18+ messages in thread
From: Eric Auger @ 2018-02-05 13:39 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, peter.maydell, qemu-arm, qemu-devel,
prem.mallappa, alex.williamson
Cc: tn, mst, christoffer.dall, bharat.bhushan, jean-philippe.brucker,
edgar.iglesias, linuc.decode, peterx
In case the MSI is translated by an IOMMU we need to fixup the
MSI route with the translated address.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v5 -> v6:
- use IOMMUMemoryRegionClass API
It is still unclear to me if we need to register an IOMMUNotifier
to handle any change in the MSI doorbell which would occur behind
the scene and would not lead to any call to kvm_arch_fixup_msi_route().
---
target/arm/kvm.c | 27 +++++++++++++++++++++++++++
target/arm/trace-events | 3 +++
2 files changed, 30 insertions(+)
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 211a7bf..f0bd4d0 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -20,8 +20,13 @@
#include "sysemu/kvm.h"
#include "kvm_arm.h"
#include "cpu.h"
+#include "trace.h"
#include "internals.h"
#include "hw/arm/arm.h"
+#include "hw/pci/pci.h"
+#include "hw/pci/msi.h"
+#include "hw/arm/smmu-common.h"
+#include "hw/arm/smmuv3.h"
#include "exec/memattrs.h"
#include "exec/address-spaces.h"
#include "hw/boards.h"
@@ -666,6 +671,28 @@ int kvm_arm_vgic_probe(void)
int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
uint64_t address, uint32_t data, PCIDevice *dev)
{
+ AddressSpace *as = pci_device_iommu_address_space(dev);
+ IOMMUMemoryRegionClass *imrc;
+ IOMMUTLBEntry entry;
+ SMMUDevice *sdev;
+
+ if (as == &address_space_memory) {
+ return 0;
+ }
+
+ /* MSI doorbell address is translated by an IOMMU */
+ sdev = container_of(as, SMMUDevice, as);
+ imrc = IOMMU_MEMORY_REGION_GET_CLASS(&sdev->iommu);
+
+ entry = imrc->translate(&sdev->iommu, address, IOMMU_WO);
+
+ route->u.msi.address_lo = entry.translated_addr;
+ route->u.msi.address_hi = entry.translated_addr >> 32;
+
+ trace_kvm_arm_fixup_msi_route(address, sdev->devfn,
+ sdev->iommu.parent_obj.name,
+ entry.translated_addr);
+
return 0;
}
diff --git a/target/arm/trace-events b/target/arm/trace-events
index 9e37131..8b3c220 100644
--- a/target/arm/trace-events
+++ b/target/arm/trace-events
@@ -8,3 +8,6 @@ arm_gt_tval_write(int timer, uint64_t value) "gt_tval_write: timer %d value 0x%"
arm_gt_ctl_write(int timer, uint64_t value) "gt_ctl_write: timer %d value 0x%" PRIx64
arm_gt_imask_toggle(int timer, int irqstate) "gt_ctl_write: timer %d IMASK toggle, new irqstate %d"
arm_gt_cntvoff_write(uint64_t value) "gt_cntvoff_write: value 0x%" PRIx64
+
+# target/arm/kvm.c
+kvm_arm_fixup_msi_route(uint64_t iova, uint32_t devid, const char *name, uint64_t gpa) "MSI addr = 0x%"PRIx64" is translated for devfn=%d through %s into 0x%"PRIx64
--
2.5.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v8 12/14] hw/arm/virt: Add SMMUv3 to the virt board
2018-02-05 13:39 [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support Eric Auger
` (10 preceding siblings ...)
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 11/14] target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route Eric Auger
@ 2018-02-05 13:39 ` Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 13/14] hw/arm/virt-acpi-build: Add smmuv3 node in IORT table Eric Auger
` (2 subsequent siblings)
14 siblings, 0 replies; 18+ messages in thread
From: Eric Auger @ 2018-02-05 13:39 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, peter.maydell, qemu-arm, qemu-devel,
prem.mallappa, alex.williamson
Cc: tn, mst, christoffer.dall, bharat.bhushan, jean-philippe.brucker,
edgar.iglesias, linuc.decode, peterx
From: Prem Mallappa <prem.mallappa@broadcom.com>
Add code to instantiate an smmuv3 in virt machine. A new iommu
integer member is introduced in VirtMachineState to store the type
of the iommu in use.
Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v7 -> v8:
- integer iommu member
- add primary-bus property
v4 -> v5:
- add dma-coherent property
v2 -> v3:
- vbi was removed. Use vms instead
- migrate to new smmu binding format (iommu-map)
- don't use appendprop anymore
- add vms->smmu and guard instantiation with this latter
- interrupts type changed to edge
Conflicts:
hw/arm/smmuv3.c
---
hw/arm/virt.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++-
include/hw/arm/virt.h | 10 ++++++++
2 files changed, 73 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index b334c82..a760a68 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -58,6 +58,7 @@
#include "hw/smbios/smbios.h"
#include "qapi/visitor.h"
#include "standard-headers/linux/input.h"
+#include "hw/arm/smmuv3.h"
#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
@@ -141,6 +142,7 @@ static const MemMapEntry a15memmap[] = {
[VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
[VIRT_GPIO] = { 0x09030000, 0x00001000 },
[VIRT_SECURE_UART] = { 0x09040000, 0x00001000 },
+ [VIRT_SMMU] = { 0x09050000, 0x00020000 }, /* 128K, needed */
[VIRT_MMIO] = { 0x0a000000, 0x00000200 },
/* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
[VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
@@ -161,6 +163,7 @@ static const int a15irqmap[] = {
[VIRT_SECURE_UART] = 8,
[VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
[VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
+ [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
[VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
};
@@ -1001,7 +1004,57 @@ static void create_pcie_irq_map(const VirtMachineState *vms,
0x7 /* PCI irq */);
}
-static void create_pcie(const VirtMachineState *vms, qemu_irq *pic)
+static void create_smmu(const VirtMachineState *vms, qemu_irq *pic,
+ PCIBus *bus)
+{
+ char *node;
+ const char compat[] = "arm,smmu-v3";
+ int irq = vms->irqmap[VIRT_SMMU];
+ int i;
+ hwaddr base = vms->memmap[VIRT_SMMU].base;
+ hwaddr size = vms->memmap[VIRT_SMMU].size;
+ const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
+ DeviceState *dev;
+
+ if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
+ return;
+ }
+
+ dev = qdev_create(NULL, "arm-smmuv3");
+
+ object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
+ &error_abort);
+ qdev_init_nofail(dev);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
+ for (i = 0; i < NUM_SMMU_IRQS; i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
+ }
+
+ node = g_strdup_printf("/smmuv3@%" PRIx64, base);
+ qemu_fdt_add_subnode(vms->fdt, node);
+ qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat));
+ qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size);
+
+ qemu_fdt_setprop_cells(vms->fdt, node, "interrupts",
+ GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
+ GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
+ GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
+ GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
+
+ qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names,
+ sizeof(irq_names));
+
+ qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle);
+ qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk");
+ qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0);
+
+ qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1);
+
+ qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle);
+ g_free(node);
+}
+
+static void create_pcie(VirtMachineState *vms, qemu_irq *pic)
{
hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
@@ -1114,6 +1167,15 @@ static void create_pcie(const VirtMachineState *vms, qemu_irq *pic)
qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1);
create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename);
+ if (vms->iommu) {
+ vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt);
+
+ create_smmu(vms, pic, pci->bus);
+
+ qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map",
+ 0x0, vms->iommu_phandle, 0x0, 0x10000);
+ }
+
g_free(nodename);
}
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 33b0ff3..13d3724 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -38,6 +38,7 @@
#define NUM_GICV2M_SPIS 64
#define NUM_VIRTIO_TRANSPORTS 32
+#define NUM_SMMU_IRQS 4
#define ARCH_GICV3_MAINT_IRQ 9
@@ -59,6 +60,7 @@ enum {
VIRT_GIC_V2M,
VIRT_GIC_ITS,
VIRT_GIC_REDIST,
+ VIRT_SMMU,
VIRT_UART,
VIRT_MMIO,
VIRT_RTC,
@@ -74,6 +76,12 @@ enum {
VIRT_SECURE_MEM,
};
+enum {
+ VIRT_IOMMU_NONE,
+ VIRT_IOMMU_SMMUV3,
+ VIRT_IOMMU_VIRTIO,
+};
+
typedef struct MemMapEntry {
hwaddr base;
hwaddr size;
@@ -96,6 +104,7 @@ typedef struct {
bool its;
bool virt;
int32_t gic_version;
+ int32_t iommu;
struct arm_boot_info bootinfo;
const MemMapEntry *memmap;
const int *irqmap;
@@ -105,6 +114,7 @@ typedef struct {
uint32_t clock_phandle;
uint32_t gic_phandle;
uint32_t msi_phandle;
+ uint32_t iommu_phandle;
int psci_conduit;
} VirtMachineState;
--
2.5.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v8 13/14] hw/arm/virt-acpi-build: Add smmuv3 node in IORT table
2018-02-05 13:39 [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support Eric Auger
` (11 preceding siblings ...)
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 12/14] hw/arm/virt: Add SMMUv3 to the virt board Eric Auger
@ 2018-02-05 13:39 ` Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 14/14] hw/arm/virt: Handle iommu in 2.12 machine type Eric Auger
2018-02-05 14:53 ` [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support no-reply
14 siblings, 0 replies; 18+ messages in thread
From: Eric Auger @ 2018-02-05 13:39 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, peter.maydell, qemu-arm, qemu-devel,
prem.mallappa, alex.williamson
Cc: tn, mst, christoffer.dall, bharat.bhushan, jean-philippe.brucker,
edgar.iglesias, linuc.decode, peterx
From: Prem Mallappa <prem.mallappa@broadcom.com>
This patch builds the smmuv3 node in the ACPI IORT table.
The RID space of the root complex, which spans 0x0-0x10000
maps to streamid space 0x0-0x10000 in smmuv3, which in turn
maps to deviceid space 0x0-0x10000 in the ITS group.
The guest must feature the IOMMU probe deferral series
(https://lkml.org/lkml/2017/4/10/214) which fixes streamid
multiple lookup. This bug is not related to the SMMU emulation.
Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v2 -> v3:
- integrate into the existing IORT table made up of ITS, RC nodes
- take into account vms->smmu
- match linux actbl2.h acpi_iort_smmu_v3 field names
---
hw/arm/virt-acpi-build.c | 56 +++++++++++++++++++++++++++++++++++++++------
include/hw/acpi/acpi-defs.h | 15 ++++++++++++
2 files changed, 64 insertions(+), 7 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index f7fa795..4b5ad91 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -393,19 +393,26 @@ build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned xsdt_tbl_offset)
}
static void
-build_iort(GArray *table_data, BIOSLinker *linker)
+build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
{
- int iort_start = table_data->len;
+ int nb_nodes, iort_start = table_data->len;
AcpiIortIdMapping *idmap;
AcpiIortItsGroup *its;
AcpiIortTable *iort;
- size_t node_size, iort_length;
+ AcpiIortSmmu3 *smmu;
+ size_t node_size, iort_length, smmu_offset = 0;
AcpiIortRC *rc;
iort = acpi_data_push(table_data, sizeof(*iort));
+ if (vms->iommu) {
+ nb_nodes = 3; /* RC, ITS, SMMUv3 */
+ } else {
+ nb_nodes = 2; /* RC, ITS */
+ }
+
iort_length = sizeof(*iort);
- iort->node_count = cpu_to_le32(2); /* RC and ITS nodes */
+ iort->node_count = cpu_to_le32(nb_nodes);
iort->node_offset = cpu_to_le32(sizeof(*iort));
/* ITS group node */
@@ -418,6 +425,35 @@ build_iort(GArray *table_data, BIOSLinker *linker)
its->its_count = cpu_to_le32(1);
its->identifiers[0] = 0; /* MADT translation_id */
+ if (vms->iommu == VIRT_IOMMU_SMMUV3) {
+ int irq = vms->irqmap[VIRT_SMMU];
+
+ /* SMMUv3 node */
+ smmu_offset = cpu_to_le32(iort->node_offset + node_size);
+ node_size = sizeof(*smmu) + sizeof(*idmap);
+ iort_length += node_size;
+ smmu = acpi_data_push(table_data, node_size);
+
+
+ smmu->type = ACPI_IORT_NODE_SMMU_V3;
+ smmu->length = cpu_to_le16(node_size);
+ smmu->mapping_count = cpu_to_le32(1);
+ smmu->mapping_offset = cpu_to_le32(sizeof(*smmu));
+ smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base);
+ smmu->event_gsiv = cpu_to_le32(irq);
+ smmu->pri_gsiv = cpu_to_le32(irq + 1);
+ smmu->gerr_gsiv = cpu_to_le32(irq + 2);
+ smmu->sync_gsiv = cpu_to_le32(irq + 3);
+
+ /* Identity RID mapping covering the whole input RID range */
+ idmap = &smmu->id_mapping_array[0];
+ idmap->input_base = 0;
+ idmap->id_count = cpu_to_le32(0xFFFF);
+ idmap->output_base = 0;
+ /* output IORT node is the ITS group node (the first node) */
+ idmap->output_reference = cpu_to_le32(iort->node_offset);
+ }
+
/* Root Complex Node */
node_size = sizeof(*rc) + sizeof(*idmap);
iort_length += node_size;
@@ -438,8 +474,14 @@ build_iort(GArray *table_data, BIOSLinker *linker)
idmap->input_base = 0;
idmap->id_count = cpu_to_le32(0xFFFF);
idmap->output_base = 0;
- /* output IORT node is the ITS group node (the first node) */
- idmap->output_reference = cpu_to_le32(iort->node_offset);
+
+ if (vms->iommu) {
+ /* output IORT node is the smmuv3 node */
+ idmap->output_reference = cpu_to_le32(smmu_offset);
+ } else {
+ /* output IORT node is the ITS group node (the first node) */
+ idmap->output_reference = cpu_to_le32(iort->node_offset);
+ }
iort->length = cpu_to_le32(iort_length);
@@ -786,7 +828,7 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
if (its_class_name() && !vmc->no_its) {
acpi_add_table(table_offsets, tables_blob);
- build_iort(tables_blob, tables->linker);
+ build_iort(tables_blob, tables->linker, vms);
}
/* XSDT is pointed to by RSDP */
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index 80c8099..068ce28 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -700,6 +700,21 @@ struct AcpiIortItsGroup {
} QEMU_PACKED;
typedef struct AcpiIortItsGroup AcpiIortItsGroup;
+struct AcpiIortSmmu3 {
+ ACPI_IORT_NODE_HEADER_DEF
+ uint64_t base_address;
+ uint32_t flags;
+ uint32_t reserved2;
+ uint64_t vatos_address;
+ uint32_t model;
+ uint32_t event_gsiv;
+ uint32_t pri_gsiv;
+ uint32_t gerr_gsiv;
+ uint32_t sync_gsiv;
+ AcpiIortIdMapping id_mapping_array[0];
+} QEMU_PACKED;
+typedef struct AcpiIortSmmu3 AcpiIortSmmu3;
+
struct AcpiIortRC {
ACPI_IORT_NODE_HEADER_DEF
AcpiIortMemoryAccess memory_properties;
--
2.5.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH v8 14/14] hw/arm/virt: Handle iommu in 2.12 machine type
2018-02-05 13:39 [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support Eric Auger
` (12 preceding siblings ...)
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 13/14] hw/arm/virt-acpi-build: Add smmuv3 node in IORT table Eric Auger
@ 2018-02-05 13:39 ` Eric Auger
2018-02-05 14:53 ` [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support no-reply
14 siblings, 0 replies; 18+ messages in thread
From: Eric Auger @ 2018-02-05 13:39 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, peter.maydell, qemu-arm, qemu-devel,
prem.mallappa, alex.williamson
Cc: tn, mst, christoffer.dall, bharat.bhushan, jean-philippe.brucker,
edgar.iglesias, linuc.decode, peterx
The new machine type exposes a new "iommu" virt machine option.
The SMMUv3 IOMMU is instantiated using -machine virt,iommu=smmuv3.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v7 -> v8:
- Revert to machine option, now dubbed "iommu", preparing for virtio
instantiation.
v5 -> v6: machine 2_11
Another alternative would be to use the -device option as
done on x86. As the smmu is a sysbus device, we would need to
use the platform bus framework.
---
hw/arm/virt.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
include/hw/arm/virt.h | 1 +
2 files changed, 46 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index a760a68..c88640f 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1608,6 +1608,34 @@ static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
}
}
+static char *virt_get_iommu(Object *obj, Error **errp)
+{
+ VirtMachineState *vms = VIRT_MACHINE(obj);
+
+ switch (vms->iommu) {
+ case VIRT_IOMMU_NONE:
+ return g_strdup("none");
+ case VIRT_IOMMU_SMMUV3:
+ return g_strdup("smmuv3");
+ default:
+ return g_strdup("none");
+ }
+}
+
+static void virt_set_iommu(Object *obj, const char *value, Error **errp)
+{
+ VirtMachineState *vms = VIRT_MACHINE(obj);
+
+ if (!strcmp(value, "smmuv3")) {
+ vms->iommu = VIRT_IOMMU_SMMUV3;
+ } else if (!strcmp(value, "none")) {
+ vms->iommu = VIRT_IOMMU_NONE;
+ } else {
+ error_setg(errp, "Invalid iommu value");
+ error_append_hint(errp, "Valid value are none, smmuv3\n");
+ }
+}
+
static CpuInstanceProperties
virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
{
@@ -1740,6 +1768,19 @@ static void virt_2_12_instance_init(Object *obj)
NULL);
}
+ if (vmc->no_iommu) {
+ vms->iommu = VIRT_IOMMU_NONE;
+ } else {
+ /* Default disallows smmu instantiation */
+ vms->iommu = VIRT_IOMMU_NONE;
+ object_property_add_str(obj, "iommu", virt_get_iommu,
+ virt_set_iommu, NULL);
+ object_property_set_description(obj, "iommu",
+ "Set the IOMMU model among "
+ "none, smmuv3 (default none)",
+ NULL);
+ }
+
vms->memmap = a15memmap;
vms->irqmap = a15irqmap;
}
@@ -1759,8 +1800,12 @@ static void virt_2_11_instance_init(Object *obj)
static void virt_machine_2_11_options(MachineClass *mc)
{
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
+
virt_machine_2_12_options(mc);
SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_11);
+
+ vmc->no_iommu = true;
}
DEFINE_VIRT_MACHINE(2, 11)
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 13d3724..3a92fc3 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -92,6 +92,7 @@ typedef struct {
bool disallow_affinity_adjustment;
bool no_its;
bool no_pmu;
+ bool no_iommu;
bool claim_edge_triggered_timers;
} VirtMachineClass;
--
2.5.5
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support
2018-02-05 13:39 [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support Eric Auger
` (13 preceding siblings ...)
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 14/14] hw/arm/virt: Handle iommu in 2.12 machine type Eric Auger
@ 2018-02-05 14:53 ` no-reply
2018-02-06 12:22 ` Auger Eric
14 siblings, 1 reply; 18+ messages in thread
From: no-reply @ 2018-02-05 14:53 UTC (permalink / raw)
To: eric.auger
Cc: famz, eric.auger.pro, peter.maydell, qemu-arm, qemu-devel,
prem.mallappa, alex.williamson, mst, jean-philippe.brucker, tn,
peterx, edgar.iglesias, linuc.decode, bharat.bhushan,
christoffer.dall
Hi,
This series failed docker-mingw@fedora build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 1517837972-1904-1-git-send-email-eric.auger@redhat.com
Subject: [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support
=== TEST SCRIPT BEGIN ===
#!/bin/bash
set -e
git submodule update --init dtc
# Let docker tests dump environment info
export SHOW_ENV=1
export J=8
time make docker-test-mingw@fedora
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
0de28f0913 hw/arm/virt: Handle iommu in 2.12 machine type
378fb2a110 hw/arm/virt-acpi-build: Add smmuv3 node in IORT table
1b05b53e57 hw/arm/virt: Add SMMUv3 to the virt board
b4d6a42305 target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route
c752d8b106 hw/arm/smmuv3: Abort on vfio or vhost case
6afc32e7e2 hw/arm/smmuv3: Implement translate callback
9742c3be12 hw/arm/smmuv3: Event queue recording helper
d081ee8e3a hw/arm/smmuv3: Implement MMIO write operations
cc76d86618 hw/arm/smmuv3: Queue helpers
da5755141c hw/arm/smmuv3: Wired IRQ and GERROR helpers
6ad76bdfc8 hw/arm/smmuv3: Skeleton
34f1fde2fe hw/arm/smmu-common: VMSAv8-64 page table walk
8c73cc5199 hw/arm/smmu-common: IOMMU memory region and address space setup
e523e3be5e hw/arm/smmu-common: smmu base device and datatypes
=== OUTPUT BEGIN ===
Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc'
Cloning into '/var/tmp/patchew-tester-tmp-iv9dq1c5/src/dtc'...
Submodule path 'dtc': checked out 'e54388015af1fb4bf04d0bca99caba1074d9cc42'
BUILD fedora
GEN /var/tmp/patchew-tester-tmp-iv9dq1c5/src/docker-src.2018-02-05-09.50.27.14305/qemu.tar
Cloning into '/var/tmp/patchew-tester-tmp-iv9dq1c5/src/docker-src.2018-02-05-09.50.27.14305/qemu.tar.vroot'...
done.
Your branch is up-to-date with 'origin/test'.
Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc'
Cloning into '/var/tmp/patchew-tester-tmp-iv9dq1c5/src/docker-src.2018-02-05-09.50.27.14305/qemu.tar.vroot/dtc'...
Submodule path 'dtc': checked out 'e54388015af1fb4bf04d0bca99caba1074d9cc42'
Submodule 'ui/keycodemapdb' (git://git.qemu.org/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into '/var/tmp/patchew-tester-tmp-iv9dq1c5/src/docker-src.2018-02-05-09.50.27.14305/qemu.tar.vroot/ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '10739aa26051a5d49d88132604539d3ed085e72e'
COPY RUNNER
RUN test-mingw in qemu:fedora
Packages installed:
PyYAML-3.11-13.fc25.x86_64
SDL-devel-1.2.15-21.fc24.x86_64
bc-1.06.95-16.fc24.x86_64
bison-3.0.4-4.fc24.x86_64
bzip2-1.0.6-21.fc25.x86_64
ccache-3.3.4-1.fc25.x86_64
clang-3.9.1-2.fc25.x86_64
findutils-4.6.0-8.fc25.x86_64
flex-2.6.0-3.fc25.x86_64
gcc-6.4.1-1.fc25.x86_64
gcc-c++-6.4.1-1.fc25.x86_64
gettext-0.19.8.1-3.fc25.x86_64
git-2.9.5-3.fc25.x86_64
glib2-devel-2.50.3-1.fc25.x86_64
hostname-3.15-8.fc25.x86_64
libaio-devel-0.3.110-6.fc24.x86_64
libasan-6.4.1-1.fc25.x86_64
libfdt-devel-1.4.2-1.fc25.x86_64
libubsan-6.4.1-1.fc25.x86_64
make-4.1-6.fc25.x86_64
mingw32-SDL-1.2.15-7.fc24.noarch
mingw32-bzip2-1.0.6-7.fc24.noarch
mingw32-curl-7.47.0-1.fc24.noarch
mingw32-glib2-2.50.3-1.fc25.noarch
mingw32-gmp-6.1.1-1.fc25.noarch
mingw32-gnutls-3.5.5-2.fc25.noarch
mingw32-gtk2-2.24.31-2.fc25.noarch
mingw32-gtk3-3.22.17-1.fc25.noarch
mingw32-libjpeg-turbo-1.5.1-1.fc25.noarch
mingw32-libpng-1.6.27-1.fc25.noarch
mingw32-libssh2-1.4.3-5.fc24.noarch
mingw32-libtasn1-4.9-1.fc25.noarch
mingw32-nettle-3.3-1.fc25.noarch
mingw32-pixman-0.34.0-1.fc25.noarch
mingw32-pkg-config-0.28-6.fc24.x86_64
mingw64-SDL-1.2.15-7.fc24.noarch
mingw64-bzip2-1.0.6-7.fc24.noarch
mingw64-curl-7.47.0-1.fc24.noarch
mingw64-glib2-2.50.3-1.fc25.noarch
mingw64-gmp-6.1.1-1.fc25.noarch
mingw64-gnutls-3.5.5-2.fc25.noarch
mingw64-gtk2-2.24.31-2.fc25.noarch
mingw64-gtk3-3.22.17-1.fc25.noarch
mingw64-libjpeg-turbo-1.5.1-1.fc25.noarch
mingw64-libpng-1.6.27-1.fc25.noarch
mingw64-libssh2-1.4.3-5.fc24.noarch
mingw64-libtasn1-4.9-1.fc25.noarch
mingw64-nettle-3.3-1.fc25.noarch
mingw64-pixman-0.34.0-1.fc25.noarch
mingw64-pkg-config-0.28-6.fc24.x86_64
nettle-devel-3.3-1.fc25.x86_64
package python2 is not installed
perl-5.24.3-389.fc25.x86_64
pixman-devel-0.34.0-2.fc24.x86_64
sparse-0.5.0-10.fc25.x86_64
tar-1.29-3.fc25.x86_64
which-2.21-1.fc25.x86_64
zlib-devel-1.2.8-10.fc24.x86_64
Environment variables:
PACKAGES=ccache gettext git tar PyYAML sparse flex bison python2 bzip2 hostname glib2-devel pixman-devel zlib-devel SDL-devel libfdt-devel gcc gcc-c++ clang make perl which bc findutils libaio-devel nettle-devel libasan libubsan mingw32-pixman mingw32-glib2 mingw32-gmp mingw32-SDL mingw32-pkg-config mingw32-gtk2 mingw32-gtk3 mingw32-gnutls mingw32-nettle mingw32-libtasn1 mingw32-libjpeg-turbo mingw32-libpng mingw32-curl mingw32-libssh2 mingw32-bzip2 mingw64-pixman mingw64-glib2 mingw64-gmp mingw64-SDL mingw64-pkg-config mingw64-gtk2 mingw64-gtk3 mingw64-gnutls mingw64-nettle mingw64-libtasn1 mingw64-libjpeg-turbo mingw64-libpng mingw64-curl mingw64-libssh2 mingw64-bzip2
HOSTNAME=25a43af2202b
MAKEFLAGS= -j8
J=8
CCACHE_DIR=/var/tmp/ccache
EXTRA_CONFIGURE_OPTS=
V=
SHOW_ENV=1
PATH=/usr/lib/ccache:/usr/lib64/ccache:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
PWD=/
TARGET_LIST=
FGC=f25
SHLVL=1
HOME=/root
TEST_DIR=/tmp/qemu-test
DISTTAG=f25container
FEATURES=mingw clang pyyaml asan dtc
DEBUG=
_=/usr/bin/env
Configure options:
--enable-werror --target-list=x86_64-softmmu,aarch64-softmmu --prefix=/tmp/qemu-test/install --cross-prefix=x86_64-w64-mingw32- --enable-trace-backends=simple --enable-gnutls --enable-nettle --enable-curl --enable-vnc --enable-bzip2 --enable-guest-agent --with-sdlabi=1.2 --with-gtkabi=2.0
Install prefix /tmp/qemu-test/install
BIOS directory /tmp/qemu-test/install
firmware path /tmp/qemu-test/install/share/qemu-firmware
binary directory /tmp/qemu-test/install
library directory /tmp/qemu-test/install/lib
module directory /tmp/qemu-test/install/lib
libexec directory /tmp/qemu-test/install/libexec
include directory /tmp/qemu-test/install/include
config directory /tmp/qemu-test/install
local state directory queried at runtime
Windows SDK no
Source path /tmp/qemu-test/src
GIT binary git
GIT submodules
C compiler x86_64-w64-mingw32-gcc
Host C compiler cc
C++ compiler x86_64-w64-mingw32-g++
Objective-C compiler clang
ARFLAGS rv
CFLAGS -O2 -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 -g
QEMU_CFLAGS -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/pixman-1 -I$(SRC_PATH)/dtc/libfdt -Werror -mms-bitfields -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/glib-2.0 -I/usr/x86_64-w64-mingw32/sys-root/mingw/lib/glib-2.0/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -m64 -mcx16 -mthreads -D__USE_MINGW_ANSI_STDIO=1 -DWIN32_LEAN_AND_MEAN -DWINVER=0x501 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -Wendif-labels -Wno-shift-negative-value -Wno-missing-include-dirs -Wempty-body -Wnested-externs -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wold-style-declaration -Wold-style-definition -Wtype-limits -fstack-protector-strong -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/p11-kit-1 -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/libpng16
LDFLAGS -Wl,--nxcompat -Wl,--no-seh -Wl,--dynamicbase -Wl,--warn-common -m64 -g
make make
install install
python python -B
smbd /usr/sbin/smbd
module support no
host CPU x86_64
host big endian no
target list x86_64-softmmu aarch64-softmmu
gprof enabled no
sparse enabled no
strip binaries yes
profiler no
static build no
SDL support yes (1.2.15)
GTK support yes (2.24.31)
GTK GL support no
VTE support no
TLS priority NORMAL
GNUTLS support yes
GNUTLS rnd yes
libgcrypt no
libgcrypt kdf no
nettle yes (3.3)
nettle kdf yes
libtasn1 yes
curses support no
virgl support no
curl support yes
mingw32 support yes
Audio drivers dsound
Block whitelist (rw)
Block whitelist (ro)
VirtFS support no
Multipath support no
VNC support yes
VNC SASL support no
VNC JPEG support yes
VNC PNG support yes
xen support no
brlapi support no
bluez support no
Documentation no
PIE no
vde support no
netmap support no
Linux AIO support no
ATTR/XATTR support no
Install blobs yes
KVM support no
HAX support yes
HVF support no
TCG support yes
TCG debug enabled no
TCG interpreter no
malloc trim support no
RDMA support no
fdt support yes
preadv support no
fdatasync no
madvise no
posix_madvise no
libcap-ng support no
vhost-net support no
vhost-scsi support no
vhost-vsock support no
vhost-user support no
Trace backends simple
Trace output file trace-<pid>
spice support no
rbd support no
xfsctl support no
smartcard support no
libusb no
usb net redir no
OpenGL support no
OpenGL dmabufs no
libiscsi support no
libnfs support no
build guest agent yes
QGA VSS support no
QGA w32 disk info yes
QGA MSI support no
seccomp support no
coroutine backend win32
coroutine pool yes
debug stack usage no
crypto afalg no
GlusterFS support no
gcov gcov
gcov enabled no
TPM support yes
libssh2 support yes
TPM passthrough no
TPM emulator no
QOM debugging yes
Live block migration yes
lzo support no
snappy support no
bzip2 support yes
NUMA host support no
libxml2 no
tcmalloc support no
jemalloc support no
avx2 optimization yes
replication support yes
VxHS block device no
capstone no
WARNING: Use of GTK 2.0 is deprecated and will be removed in
WARNING: future releases. Please switch to using GTK 3.0
WARNING: Use of SDL 1.2 is deprecated and will be removed in
WARNING: future releases. Please switch to using SDL 2.0
GEN x86_64-softmmu/config-devices.mak.tmp
GEN aarch64-softmmu/config-devices.mak.tmp
GEN config-host.h
GEN qemu-options.def
GEN qmp-commands.h
GEN qapi-types.h
GEN qapi-visit.h
GEN qapi-event.h
GEN x86_64-softmmu/config-devices.mak
GEN qmp-marshal.c
GEN aarch64-softmmu/config-devices.mak
GEN qapi-types.c
GEN qapi-visit.c
GEN qapi-event.c
GEN qmp-introspect.h
GEN qmp-introspect.c
GEN trace/generated-tcg-tracers.h
GEN trace/generated-helpers-wrappers.h
GEN trace/generated-helpers.h
GEN trace/generated-helpers.c
GEN module_block.h
GEN ui/input-keymap-atset1-to-qcode.c
GEN ui/input-keymap-linux-to-qcode.c
GEN ui/input-keymap-qcode-to-atset1.c
GEN ui/input-keymap-qcode-to-atset2.c
GEN ui/input-keymap-qcode-to-atset3.c
GEN ui/input-keymap-qcode-to-linux.c
GEN ui/input-keymap-qcode-to-qnum.c
GEN ui/input-keymap-qcode-to-sun.c
GEN ui/input-keymap-qnum-to-qcode.c
GEN ui/input-keymap-usb-to-qcode.c
GEN ui/input-keymap-win32-to-qcode.c
GEN ui/input-keymap-x11-to-qcode.c
GEN ui/input-keymap-xorgevdev-to-qcode.c
GEN ui/input-keymap-xorgkbd-to-qcode.c
GEN ui/input-keymap-xorgxquartz-to-qcode.c
GEN ui/input-keymap-xorgxwin-to-qcode.c
GEN tests/test-qapi-types.h
GEN tests/test-qapi-visit.h
GEN tests/test-qmp-commands.h
GEN tests/test-qapi-event.h
GEN tests/test-qmp-introspect.h
GEN trace-root.h
GEN util/trace.h
GEN crypto/trace.h
GEN io/trace.h
GEN migration/trace.h
GEN block/trace.h
GEN chardev/trace.h
GEN hw/block/trace.h
GEN hw/block/dataplane/trace.h
GEN hw/char/trace.h
GEN hw/intc/trace.h
GEN hw/net/trace.h
GEN hw/virtio/trace.h
GEN hw/audio/trace.h
GEN hw/misc/trace.h
GEN hw/usb/trace.h
GEN hw/scsi/trace.h
GEN hw/nvram/trace.h
GEN hw/display/trace.h
GEN hw/input/trace.h
GEN hw/timer/trace.h
GEN hw/dma/trace.h
GEN hw/sparc/trace.h
GEN hw/sparc64/trace.h
GEN hw/sd/trace.h
GEN hw/isa/trace.h
GEN hw/mem/trace.h
GEN hw/i386/trace.h
GEN hw/i386/xen/trace.h
GEN hw/9pfs/trace.h
GEN hw/ppc/trace.h
GEN hw/pci/trace.h
GEN hw/pci-host/trace.h
GEN hw/s390x/trace.h
GEN hw/vfio/trace.h
GEN hw/acpi/trace.h
GEN hw/arm/trace.h
GEN hw/alpha/trace.h
GEN hw/hppa/trace.h
GEN hw/xen/trace.h
GEN hw/ide/trace.h
GEN ui/trace.h
GEN audio/trace.h
GEN net/trace.h
GEN target/arm/trace.h
GEN target/i386/trace.h
GEN target/mips/trace.h
GEN target/sparc/trace.h
GEN target/s390x/trace.h
GEN target/ppc/trace.h
GEN qom/trace.h
GEN linux-user/trace.h
GEN qapi/trace.h
GEN accel/tcg/trace.h
GEN accel/kvm/trace.h
GEN nbd/trace.h
GEN scsi/trace.h
GEN trace-root.c
GEN util/trace.c
GEN crypto/trace.c
GEN io/trace.c
GEN migration/trace.c
GEN block/trace.c
GEN chardev/trace.c
GEN hw/block/trace.c
GEN hw/block/dataplane/trace.c
GEN hw/char/trace.c
GEN hw/intc/trace.c
GEN hw/net/trace.c
GEN hw/virtio/trace.c
GEN hw/audio/trace.c
GEN hw/misc/trace.c
GEN hw/usb/trace.c
GEN hw/scsi/trace.c
GEN hw/nvram/trace.c
GEN hw/display/trace.c
GEN hw/input/trace.c
GEN hw/timer/trace.c
GEN hw/dma/trace.c
GEN hw/sparc/trace.c
GEN hw/sparc64/trace.c
GEN hw/sd/trace.c
GEN hw/isa/trace.c
GEN hw/mem/trace.c
GEN hw/i386/trace.c
GEN hw/i386/xen/trace.c
GEN hw/9pfs/trace.c
GEN hw/ppc/trace.c
GEN hw/pci/trace.c
GEN hw/pci-host/trace.c
GEN hw/s390x/trace.c
GEN hw/vfio/trace.c
GEN hw/acpi/trace.c
GEN hw/arm/trace.c
GEN hw/hppa/trace.c
GEN hw/alpha/trace.c
GEN hw/xen/trace.c
GEN hw/ide/trace.c
GEN ui/trace.c
GEN audio/trace.c
GEN net/trace.c
GEN target/arm/trace.c
GEN target/i386/trace.c
GEN target/mips/trace.c
GEN target/sparc/trace.c
GEN target/s390x/trace.c
GEN target/ppc/trace.c
GEN qom/trace.c
GEN linux-user/trace.c
GEN qapi/trace.c
GEN accel/tcg/trace.c
GEN accel/kvm/trace.c
GEN nbd/trace.c
GEN scsi/trace.c
GEN config-all-devices.mak
DEP /tmp/qemu-test/src/dtc/tests/dumptrees.c
DEP /tmp/qemu-test/src/dtc/tests/value-labels.c
DEP /tmp/qemu-test/src/dtc/tests/trees.S
DEP /tmp/qemu-test/src/dtc/tests/testutils.c
DEP /tmp/qemu-test/src/dtc/tests/asm_tree_dump.c
DEP /tmp/qemu-test/src/dtc/tests/truncated_property.c
DEP /tmp/qemu-test/src/dtc/tests/check_path.c
DEP /tmp/qemu-test/src/dtc/tests/overlay_bad_fixup.c
DEP /tmp/qemu-test/src/dtc/tests/overlay.c
DEP /tmp/qemu-test/src/dtc/tests/property_iterate.c
DEP /tmp/qemu-test/src/dtc/tests/subnode_iterate.c
DEP /tmp/qemu-test/src/dtc/tests/integer-expressions.c
DEP /tmp/qemu-test/src/dtc/tests/add_subnode_with_nops.c
DEP /tmp/qemu-test/src/dtc/tests/path_offset_aliases.c
DEP /tmp/qemu-test/src/dtc/tests/utilfdt_test.c
DEP /tmp/qemu-test/src/dtc/tests/dtbs_equal_unordered.c
DEP /tmp/qemu-test/src/dtc/tests/dtb_reverse.c
DEP /tmp/qemu-test/src/dtc/tests/dtbs_equal_ordered.c
DEP /tmp/qemu-test/src/dtc/tests/extra-terminating-null.c
DEP /tmp/qemu-test/src/dtc/tests/incbin.c
DEP /tmp/qemu-test/src/dtc/tests/boot-cpuid.c
DEP /tmp/qemu-test/src/dtc/tests/phandle_format.c
DEP /tmp/qemu-test/src/dtc/tests/references.c
DEP /tmp/qemu-test/src/dtc/tests/string_escapes.c
DEP /tmp/qemu-test/src/dtc/tests/path-references.c
DEP /tmp/qemu-test/src/dtc/tests/propname_escapes.c
DEP /tmp/qemu-test/src/dtc/tests/appendprop2.c
DEP /tmp/qemu-test/src/dtc/tests/appendprop1.c
DEP /tmp/qemu-test/src/dtc/tests/del_property.c
DEP /tmp/qemu-test/src/dtc/tests/del_node.c
DEP /tmp/qemu-test/src/dtc/tests/setprop.c
DEP /tmp/qemu-test/src/dtc/tests/set_name.c
DEP /tmp/qemu-test/src/dtc/tests/rw_tree1.c
DEP /tmp/qemu-test/src/dtc/tests/open_pack.c
DEP /tmp/qemu-test/src/dtc/tests/nopulate.c
DEP /tmp/qemu-test/src/dtc/tests/mangle-layout.c
DEP /tmp/qemu-test/src/dtc/tests/move_and_save.c
DEP /tmp/qemu-test/src/dtc/tests/sw_tree1.c
DEP /tmp/qemu-test/src/dtc/tests/nop_node.c
DEP /tmp/qemu-test/src/dtc/tests/nop_property.c
DEP /tmp/qemu-test/src/dtc/tests/setprop_inplace.c
DEP /tmp/qemu-test/src/dtc/tests/stringlist.c
DEP /tmp/qemu-test/src/dtc/tests/addr_size_cells.c
DEP /tmp/qemu-test/src/dtc/tests/notfound.c
DEP /tmp/qemu-test/src/dtc/tests/sized_cells.c
DEP /tmp/qemu-test/src/dtc/tests/char_literal.c
DEP /tmp/qemu-test/src/dtc/tests/get_alias.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_compatible.c
DEP /tmp/qemu-test/src/dtc/tests/node_check_compatible.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_phandle.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_prop_value.c
DEP /tmp/qemu-test/src/dtc/tests/parent_offset.c
DEP /tmp/qemu-test/src/dtc/tests/supernode_atdepth_offset.c
DEP /tmp/qemu-test/src/dtc/tests/get_path.c
DEP /tmp/qemu-test/src/dtc/tests/get_phandle.c
DEP /tmp/qemu-test/src/dtc/tests/getprop.c
DEP /tmp/qemu-test/src/dtc/tests/get_name.c
DEP /tmp/qemu-test/src/dtc/tests/path_offset.c
DEP /tmp/qemu-test/src/dtc/tests/subnode_offset.c
DEP /tmp/qemu-test/src/dtc/tests/find_property.c
DEP /tmp/qemu-test/src/dtc/tests/root_node.c
DEP /tmp/qemu-test/src/dtc/tests/get_mem_rsv.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_overlay.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_addresses.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_empty_tree.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_strerror.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_rw.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_wip.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_sw.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_ro.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt.c
DEP /tmp/qemu-test/src/dtc/util.c
DEP /tmp/qemu-test/src/dtc/fdtoverlay.c
DEP /tmp/qemu-test/src/dtc/fdtput.c
DEP /tmp/qemu-test/src/dtc/fdtget.c
DEP /tmp/qemu-test/src/dtc/fdtdump.c
LEX convert-dtsv0-lexer.lex.c
DEP /tmp/qemu-test/src/dtc/srcpos.c
BISON dtc-parser.tab.c
LEX dtc-lexer.lex.c
DEP /tmp/qemu-test/src/dtc/treesource.c
DEP /tmp/qemu-test/src/dtc/livetree.c
DEP /tmp/qemu-test/src/dtc/fstree.c
DEP /tmp/qemu-test/src/dtc/flattree.c
DEP /tmp/qemu-test/src/dtc/dtc.c
DEP /tmp/qemu-test/src/dtc/data.c
DEP /tmp/qemu-test/src/dtc/checks.c
DEP convert-dtsv0-lexer.lex.c
DEP dtc-parser.tab.c
DEP dtc-lexer.lex.c
CHK version_gen.h
UPD version_gen.h
DEP /tmp/qemu-test/src/dtc/util.c
CC libfdt/fdt.o
CC libfdt/fdt_ro.o
CC libfdt/fdt_wip.o
CC libfdt/fdt_sw.o
CC libfdt/fdt_rw.o
CC libfdt/fdt_strerror.o
CC libfdt/fdt_empty_tree.o
CC libfdt/fdt_addresses.o
CC libfdt/fdt_overlay.o
AR libfdt/libfdt.a
x86_64-w64-mingw32-ar: creating libfdt/libfdt.a
a - libfdt/fdt.o
a - libfdt/fdt_ro.o
a - libfdt/fdt_wip.o
a - libfdt/fdt_sw.o
a - libfdt/fdt_rw.o
a - libfdt/fdt_strerror.o
a - libfdt/fdt_empty_tree.o
a - libfdt/fdt_addresses.o
a - libfdt/fdt_overlay.o
RC version.o
GEN qga/qapi-generated/qga-qapi-types.h
GEN qga/qapi-generated/qga-qmp-commands.h
GEN qga/qapi-generated/qga-qapi-types.c
GEN qga/qapi-generated/qga-qapi-visit.h
GEN qga/qapi-generated/qga-qmp-marshal.c
CC qmp-introspect.o
CC qapi-types.o
GEN qga/qapi-generated/qga-qapi-visit.c
CC qapi-visit.o
CC qapi-event.o
CC qapi/qapi-visit-core.o
CC qapi/qapi-dealloc-visitor.o
CC qapi/qobject-input-visitor.o
CC qapi/qobject-output-visitor.o
CC qapi/qmp-registry.o
CC qapi/qmp-dispatch.o
CC qapi/string-input-visitor.o
CC qapi/string-output-visitor.o
CC qapi/opts-visitor.o
CC qapi/qapi-clone-visitor.o
CC qapi/qmp-event.o
CC qapi/qapi-util.o
CC qobject/qnull.o
CC qobject/qnum.o
CC qobject/qstring.o
CC qobject/qdict.o
CC qobject/qlist.o
CC qobject/qbool.o
CC qobject/qlit.o
CC qobject/qjson.o
CC qobject/qobject.o
CC qobject/json-lexer.o
CC qobject/json-streamer.o
CC qobject/json-parser.o
CC trace/simple.o
CC trace/control.o
CC trace/qmp.o
CC util/osdep.o
CC util/cutils.o
CC util/unicode.o
CC util/qemu-timer-common.o
CC util/bufferiszero.o
CC util/lockcnt.o
CC util/aiocb.o
CC util/async.o
CC util/thread-pool.o
CC util/qemu-timer.o
CC util/main-loop.o
CC util/iohandler.o
CC util/aio-win32.o
CC util/event_notifier-win32.o
CC util/oslib-win32.o
CC util/qemu-thread-win32.o
CC util/envlist.o
CC util/path.o
CC util/module.o
CC util/host-utils.o
CC util/bitmap.o
CC util/bitops.o
CC util/hbitmap.o
CC util/fifo8.o
CC util/acl.o
CC util/cacheinfo.o
CC util/error.o
CC util/qemu-error.o
CC util/id.o
CC util/iov.o
CC util/qemu-sockets.o
CC util/qemu-config.o
CC util/uri.o
CC util/notify.o
CC util/qemu-option.o
CC util/qemu-progress.o
CC util/keyval.o
CC util/hexdump.o
CC util/crc32c.o
CC util/uuid.o
CC util/throttle.o
CC util/getauxval.o
CC util/readline.o
CC util/rcu.o
CC util/qemu-coroutine.o
CC util/qemu-coroutine-lock.o
CC util/qemu-coroutine-io.o
CC util/qemu-coroutine-sleep.o
CC util/coroutine-win32.o
CC util/buffer.o
CC util/timed-average.o
CC util/base64.o
CC util/log.o
CC util/pagesize.o
CC util/qht.o
CC util/qdist.o
CC util/range.o
CC util/stats64.o
CC util/systemd.o
CC trace-root.o
CC util/trace.o
CC crypto/trace.o
CC io/trace.o
CC migration/trace.o
CC block/trace.o
CC chardev/trace.o
CC hw/block/trace.o
CC hw/block/dataplane/trace.o
CC hw/char/trace.o
CC hw/intc/trace.o
CC hw/net/trace.o
CC hw/virtio/trace.o
CC hw/audio/trace.o
CC hw/misc/trace.o
CC hw/usb/trace.o
CC hw/scsi/trace.o
CC hw/nvram/trace.o
CC hw/display/trace.o
CC hw/input/trace.o
CC hw/timer/trace.o
CC hw/dma/trace.o
CC hw/sparc/trace.o
CC hw/sparc64/trace.o
CC hw/sd/trace.o
CC hw/isa/trace.o
CC hw/mem/trace.o
CC hw/i386/trace.o
CC hw/i386/xen/trace.o
CC hw/9pfs/trace.o
CC hw/ppc/trace.o
CC hw/pci/trace.o
CC hw/pci-host/trace.o
CC hw/s390x/trace.o
CC hw/vfio/trace.o
CC hw/acpi/trace.o
CC hw/arm/trace.o
CC hw/alpha/trace.o
CC hw/hppa/trace.o
CC hw/xen/trace.o
CC hw/ide/trace.o
CC ui/trace.o
CC audio/trace.o
CC net/trace.o
CC target/arm/trace.o
CC target/i386/trace.o
CC target/mips/trace.o
CC target/sparc/trace.o
CC target/s390x/trace.o
CC target/ppc/trace.o
CC qom/trace.o
CC linux-user/trace.o
CC qapi/trace.o
CC accel/tcg/trace.o
CC accel/kvm/trace.o
CC nbd/trace.o
CC scsi/trace.o
CC crypto/pbkdf-stub.o
CC stubs/arch-query-cpu-def.o
CC stubs/arch-query-cpu-model-expansion.o
CC stubs/arch-query-cpu-model-comparison.o
CC stubs/arch-query-cpu-model-baseline.o
CC stubs/bdrv-next-monitor-owned.o
CC stubs/blockdev-close-all-bdrv-states.o
CC stubs/blk-commit-all.o
CC stubs/clock-warp.o
CC stubs/cpu-get-clock.o
CC stubs/cpu-get-icount.o
CC stubs/dump.o
CC stubs/error-printf.o
CC stubs/fdset.o
CC stubs/gdbstub.o
CC stubs/get-vm-name.o
CC stubs/iothread.o
CC stubs/iothread-lock.o
CC stubs/is-daemonized.o
CC stubs/machine-init-done.o
CC stubs/migr-blocker.o
CC stubs/change-state-handler.o
CC stubs/monitor.o
CC stubs/notify-event.o
CC stubs/qtest.o
CC stubs/replay.o
CC stubs/runstate-check.o
CC stubs/set-fd-handler.o
CC stubs/slirp.o
CC stubs/sysbus.o
CC stubs/tpm.o
CC stubs/trace-control.o
CC stubs/uuid.o
CC stubs/vm-stop.o
CC stubs/vmstate.o
CC stubs/fd-register.o
CC stubs/qmp_pc_dimm.o
CC stubs/target-monitor-defs.o
CC stubs/target-get-monitor-def.o
CC stubs/pc_madt_cpu_entry.o
CC stubs/vmgenid.o
CC stubs/xen-common.o
CC stubs/xen-hvm.o
CC stubs/pci-host-piix.o
GEN qemu-img-cmds.h
CC block.o
CC blockjob.o
CC qemu-io-cmds.o
CC replication.o
CC block/raw-format.o
CC block/qcow.o
CC block/vdi.o
CC block/vmdk.o
CC block/cloop.o
CC block/bochs.o
CC block/vpc.o
CC block/vvfat.o
CC block/qcow2.o
CC block/dmg.o
CC block/qcow2-refcount.o
CC block/qcow2-cluster.o
CC block/qcow2-snapshot.o
CC block/qcow2-cache.o
CC block/qcow2-bitmap.o
CC block/qed.o
CC block/qed-l2-cache.o
CC block/qed-table.o
CC block/qed-cluster.o
CC block/qed-check.o
CC block/vhdx.o
CC block/vhdx-endian.o
CC block/vhdx-log.o
CC block/quorum.o
CC block/parallels.o
CC block/blkdebug.o
CC block/blkverify.o
CC block/blkreplay.o
CC block/block-backend.o
CC block/snapshot.o
CC block/qapi.o
CC block/file-win32.o
CC block/win32-aio.o
CC block/null.o
CC block/mirror.o
CC block/commit.o
CC block/io.o
CC block/throttle-groups.o
CC block/nbd.o
CC block/nbd-client.o
CC block/sheepdog.o
CC block/accounting.o
CC block/dirty-bitmap.o
CC block/write-threshold.o
CC block/backup.o
CC block/replication.o
CC block/throttle.o
CC block/crypto.o
CC nbd/server.o
CC nbd/client.o
CC nbd/common.o
CC scsi/utils.o
CC block/curl.o
CC block/ssh.o
CC block/dmg-bz2.o
CC crypto/init.o
CC crypto/hash.o
CC crypto/hash-nettle.o
CC crypto/hmac.o
CC crypto/hmac-nettle.o
CC crypto/aes.o
CC crypto/desrfb.o
CC crypto/cipher.o
CC crypto/tlscreds.o
CC crypto/tlscredsanon.o
CC crypto/pbkdf.o
CC crypto/secret.o
CC crypto/tlscredsx509.o
CC crypto/tlssession.o
CC crypto/pbkdf-nettle.o
CC crypto/random-gnutls.o
CC crypto/ivgen.o
CC crypto/ivgen-essiv.o
CC crypto/ivgen-plain.o
CC crypto/ivgen-plain64.o
CC crypto/afsplit.o
CC crypto/xts.o
CC crypto/block.o
CC crypto/block-qcow.o
CC crypto/block-luks.o
CC io/channel.o
CC io/channel-buffer.o
CC io/channel-command.o
CC io/channel-file.o
CC io/channel-socket.o
CC io/channel-tls.o
CC io/channel-watch.o
CC io/channel-websock.o
CC io/channel-util.o
CC io/dns-resolver.o
CC io/net-listener.o
CC io/task.o
CC qom/object.o
CC qom/container.o
CC qom/qom-qobject.o
CC qom/object_interfaces.o
CC qemu-io.o
CC blockdev.o
CC blockdev-nbd.o
CC bootdevice.o
CC iothread.o
CC qdev-monitor.o
CC device-hotplug.o
CC os-win32.o
CC bt-host.o
CC bt-vhci.o
CC dma-helpers.o
CC vl.o
CC tpm.o
CC device_tree.o
CC qmp-marshal.o
CC qmp.o
CC hmp.o
CC cpus-common.o
CC audio/audio.o
CC audio/noaudio.o
CC audio/wavaudio.o
CC audio/mixeng.o
CC audio/sdlaudio.o
CC audio/dsoundaudio.o
CC audio/audio_win_int.o
CC audio/wavcapture.o
CC backends/rng.o
CC backends/rng-egd.o
CC backends/tpm.o
CC backends/hostmem.o
CC backends/hostmem-ram.o
CC backends/cryptodev.o
CC backends/cryptodev-builtin.o
CC block/stream.o
CC chardev/msmouse.o
CC chardev/wctablet.o
CC chardev/testdev.o
CC disas/arm.o
CXX disas/arm-a64.o
CC disas/i386.o
CXX disas/libvixl/vixl/utils.o
CXX disas/libvixl/vixl/compiler-intrinsics.o
CXX disas/libvixl/vixl/a64/instructions-a64.o
CXX disas/libvixl/vixl/a64/decoder-a64.o
CXX disas/libvixl/vixl/a64/disasm-a64.o
CC hw/acpi/piix4.o
CC hw/acpi/core.o
CC hw/acpi/pcihp.o
CC hw/acpi/ich9.o
CC hw/acpi/tco.o
CC hw/acpi/cpu_hotplug.o
CC hw/acpi/memory_hotplug.o
CC hw/acpi/cpu.o
CC hw/acpi/nvdimm.o
CC hw/acpi/vmgenid.o
CC hw/acpi/acpi_interface.o
CC hw/acpi/bios-linker-loader.o
CC hw/acpi/aml-build.o
CC hw/acpi/ipmi.o
CC hw/acpi/acpi-stub.o
CC hw/acpi/ipmi-stub.o
CC hw/audio/sb16.o
CC hw/audio/es1370.o
CC hw/audio/ac97.o
CC hw/audio/fmopl.o
CC hw/audio/adlib.o
CC hw/audio/gus.o
CC hw/audio/gusemu_hal.o
CC hw/audio/gusemu_mixer.o
CC hw/audio/cs4231a.o
CC hw/audio/intel-hda.o
CC hw/audio/hda-codec.o
CC hw/audio/pcspk.o
CC hw/audio/wm8750.o
CC hw/audio/pl041.o
CC hw/audio/lm4549.o
CC hw/audio/marvell_88w8618.o
CC hw/audio/soundhw.o
CC hw/block/block.o
CC hw/block/cdrom.o
CC hw/block/hd-geometry.o
CC hw/block/fdc.o
CC hw/block/m25p80.o
CC hw/block/nand.o
CC hw/block/pflash_cfi01.o
CC hw/block/pflash_cfi02.o
CC hw/block/ecc.o
CC hw/block/onenand.o
CC hw/block/nvme.o
CC hw/bt/core.o
CC hw/bt/l2cap.o
CC hw/bt/sdp.o
CC hw/bt/hci.o
CC hw/bt/hid.o
CC hw/bt/hci-csr.o
CC hw/char/ipoctal232.o
CC hw/char/parallel.o
CC hw/char/pl011.o
CC hw/char/serial.o
CC hw/char/serial-isa.o
CC hw/char/serial-pci.o
CC hw/char/virtio-console.o
CC hw/char/cadence_uart.o
CC hw/char/cmsdk-apb-uart.o
CC hw/char/debugcon.o
CC hw/char/imx_serial.o
CC hw/core/qdev.o
CC hw/core/qdev-properties.o
CC hw/core/bus.o
CC hw/core/reset.o
CC hw/core/qdev-fw.o
CC hw/core/fw-path-provider.o
CC hw/core/irq.o
CC hw/core/hotplug.o
CC hw/core/nmi.o
CC hw/core/stream.o
CC hw/core/ptimer.o
CC hw/core/sysbus.o
CC hw/core/machine.o
CC hw/core/loader.o
CC hw/core/qdev-properties-system.o
CC hw/core/register.o
CC hw/core/or-irq.o
CC hw/core/platform-bus.o
CC hw/cpu/core.o
CC hw/display/ads7846.o
CC hw/display/cirrus_vga.o
CC hw/display/pl110.o
CC hw/display/ssd0303.o
CC hw/display/ssd0323.o
CC hw/display/vga-isa.o
CC hw/display/vga-pci.o
CC hw/display/vmware_vga.o
CC hw/display/blizzard.o
CC hw/display/exynos4210_fimd.o
CC hw/display/framebuffer.o
CC hw/display/tc6393xb.o
CC hw/dma/pl080.o
CC hw/dma/pl330.o
CC hw/dma/i8257.o
CC hw/dma/xilinx_axidma.o
CC hw/dma/xlnx-zynq-devcfg.o
CC hw/gpio/max7310.o
CC hw/gpio/pl061.o
CC hw/gpio/zaurus.o
CC hw/gpio/gpio_key.o
CC hw/i2c/core.o
CC hw/i2c/smbus.o
CC hw/i2c/smbus_eeprom.o
CC hw/i2c/i2c-ddc.o
CC hw/i2c/versatile_i2c.o
CC hw/i2c/smbus_ich9.o
CC hw/i2c/pm_smbus.o
CC hw/i2c/bitbang_i2c.o
CC hw/i2c/exynos4210_i2c.o
CC hw/i2c/imx_i2c.o
CC hw/i2c/aspeed_i2c.o
CC hw/ide/core.o
CC hw/ide/atapi.o
CC hw/ide/qdev.o
CC hw/ide/pci.o
CC hw/ide/isa.o
CC hw/ide/piix.o
CC hw/ide/microdrive.o
CC hw/ide/ahci.o
CC hw/ide/ich.o
CC hw/ide/ahci-allwinner.o
CC hw/input/hid.o
CC hw/input/lm832x.o
CC hw/input/pckbd.o
CC hw/input/pl050.o
CC hw/input/ps2.o
CC hw/input/stellaris_input.o
CC hw/input/tsc2005.o
CC hw/input/virtio-input.o
CC hw/input/virtio-input-hid.o
CC hw/intc/i8259_common.o
CC hw/intc/i8259.o
CC hw/intc/pl190.o
CC hw/intc/xlnx-pmu-iomod-intc.o
CC hw/intc/xlnx-zynqmp-ipi.o
CC hw/intc/imx_avic.o
CC hw/intc/realview_gic.o
CC hw/intc/ioapic_common.o
CC hw/intc/arm_gic_common.o
CC hw/intc/arm_gic.o
CC hw/intc/arm_gicv2m.o
CC hw/intc/arm_gicv3_common.o
CC hw/intc/arm_gicv3.o
CC hw/intc/arm_gicv3_dist.o
CC hw/intc/arm_gicv3_redist.o
CC hw/intc/arm_gicv3_its_common.o
CC hw/intc/intc.o
CC hw/ipack/ipack.o
CC hw/ipack/tpci200.o
CC hw/ipmi/ipmi.o
CC hw/ipmi/ipmi_bmc_sim.o
CC hw/ipmi/ipmi_bmc_extern.o
CC hw/ipmi/isa_ipmi_kcs.o
CC hw/isa/isa-bus.o
CC hw/ipmi/isa_ipmi_bt.o
CC hw/isa/apm.o
CC hw/mem/nvdimm.o
CC hw/mem/pc-dimm.o
CC hw/misc/applesmc.o
CC hw/misc/max111x.o
CC hw/misc/tmp105.o
CC hw/misc/tmp421.o
CC hw/misc/sga.o
CC hw/misc/debugexit.o
CC hw/misc/pc-testdev.o
CC hw/misc/pci-testdev.o
CC hw/misc/edu.o
CC hw/misc/unimp.o
CC hw/misc/vmcoreinfo.o
CC hw/misc/arm_l2x0.o
CC hw/misc/arm_integrator_debug.o
CC hw/misc/a9scu.o
CC hw/misc/arm11scu.o
CC hw/net/ne2000.o
CC hw/net/eepro100.o
CC hw/net/pcnet-pci.o
CC hw/net/pcnet.o
CC hw/net/e1000.o
CC hw/net/e1000x_common.o
CC hw/net/net_tx_pkt.o
CC hw/net/net_rx_pkt.o
CC hw/net/e1000e.o
CC hw/net/e1000e_core.o
CC hw/net/rtl8139.o
CC hw/net/vmxnet3.o
CC hw/net/smc91c111.o
CC hw/net/lan9118.o
CC hw/net/ne2000-isa.o
CC hw/net/xgmac.o
CC hw/net/xilinx_axienet.o
CC hw/net/allwinner_emac.o
CC hw/net/imx_fec.o
CC hw/net/cadence_gem.o
CC hw/net/stellaris_enet.o
CC hw/net/ftgmac100.o
CC hw/net/rocker/rocker.o
CC hw/net/rocker/rocker_fp.o
CC hw/net/rocker/rocker_desc.o
CC hw/net/rocker/rocker_world.o
CC hw/net/rocker/rocker_of_dpa.o
CC hw/nvram/eeprom93xx.o
CC hw/nvram/eeprom_at24c.o
CC hw/nvram/fw_cfg.o
CC hw/nvram/chrp_nvram.o
CC hw/pci-bridge/pci_bridge_dev.o
CC hw/pci-bridge/pcie_root_port.o
CC hw/pci-bridge/gen_pcie_root_port.o
CC hw/pci-bridge/pcie_pci_bridge.o
CC hw/pci-bridge/pci_expander_bridge.o
CC hw/pci-bridge/xio3130_upstream.o
CC hw/pci-bridge/xio3130_downstream.o
CC hw/pci-bridge/ioh3420.o
CC hw/pci-bridge/i82801b11.o
CC hw/pci-host/pam.o
CC hw/pci-host/versatile.o
CC hw/pci-host/piix.o
CC hw/pci-host/q35.o
CC hw/pci-host/gpex.o
CC hw/pci/pci.o
CC hw/pci/pci_bridge.o
CC hw/pci/msix.o
CC hw/pci/msi.o
CC hw/pci/shpc.o
CC hw/pci/slotid_cap.o
CC hw/pci/pci_host.o
CC hw/pci/pcie_host.o
CC hw/pci/pcie.o
CC hw/pci/pcie_aer.o
CC hw/pci/pcie_port.o
CC hw/pci/pci-stub.o
CC hw/pcmcia/pcmcia.o
CC hw/scsi/scsi-disk.o
CC hw/scsi/scsi-generic.o
CC hw/scsi/scsi-bus.o
CC hw/scsi/lsi53c895a.o
CC hw/scsi/mptsas.o
CC hw/scsi/mptconfig.o
CC hw/scsi/mptendian.o
CC hw/scsi/megasas.o
CC hw/scsi/vmw_pvscsi.o
CC hw/scsi/esp.o
CC hw/scsi/esp-pci.o
CC hw/sd/pl181.o
CC hw/sd/ssi-sd.o
CC hw/sd/sd.o
CC hw/sd/core.o
CC hw/sd/sdhci.o
CC hw/smbios/smbios.o
CC hw/smbios/smbios_type_38.o
CC hw/smbios/smbios-stub.o
CC hw/smbios/smbios_type_38-stub.o
CC hw/ssi/pl022.o
CC hw/ssi/ssi.o
CC hw/ssi/xilinx_spips.o
CC hw/ssi/aspeed_smc.o
CC hw/ssi/stm32f2xx_spi.o
CC hw/ssi/mss-spi.o
CC hw/timer/arm_timer.o
CC hw/timer/arm_mptimer.o
CC hw/timer/armv7m_systick.o
CC hw/timer/a9gtimer.o
CC hw/timer/cadence_ttc.o
CC hw/timer/ds1338.o
CC hw/timer/hpet.o
CC hw/timer/i8254_common.o
CC hw/timer/i8254.o
CC hw/timer/pl031.o
CC hw/timer/twl92230.o
CC hw/timer/imx_epit.o
CC hw/timer/imx_gpt.o
CC hw/timer/stm32f2xx_timer.o
CC hw/timer/aspeed_timer.o
CC hw/timer/cmsdk-apb-timer.o
CC hw/timer/mss-timer.o
CC hw/tpm/tpm_util.o
CC hw/tpm/tpm_tis.o
CC hw/tpm/tpm_crb.o
CC hw/usb/core.o
CC hw/usb/combined-packet.o
CC hw/usb/bus.o
CC hw/usb/libhw.o
CC hw/usb/desc.o
CC hw/usb/desc-msos.o
CC hw/usb/hcd-uhci.o
CC hw/usb/hcd-ohci.o
CC hw/usb/hcd-ehci.o
CC hw/usb/hcd-ehci-pci.o
CC hw/usb/hcd-ehci-sysbus.o
CC hw/usb/hcd-xhci.o
CC hw/usb/hcd-xhci-nec.o
CC hw/usb/hcd-musb.o
CC hw/usb/dev-hub.o
CC hw/usb/dev-hid.o
CC hw/usb/dev-wacom.o
CC hw/usb/dev-storage.o
CC hw/usb/dev-uas.o
CC hw/usb/dev-audio.o
CC hw/usb/dev-serial.o
CC hw/usb/dev-network.o
CC hw/usb/dev-bluetooth.o
CC hw/usb/dev-smartcard-reader.o
CC hw/usb/host-stub.o
CC hw/virtio/virtio-rng.o
CC hw/virtio/virtio-pci.o
CC hw/virtio/virtio-bus.o
CC hw/virtio/virtio-mmio.o
CC hw/virtio/vhost-stub.o
CC hw/watchdog/watchdog.o
CC hw/watchdog/wdt_i6300esb.o
CC hw/watchdog/wdt_ib700.o
CC hw/watchdog/wdt_aspeed.o
CC migration/migration.o
CC migration/socket.o
CC migration/fd.o
CC migration/exec.o
CC migration/tls.o
CC migration/channel.o
CC migration/savevm.o
CC migration/colo-comm.o
CC migration/colo.o
CC migration/colo-failover.o
CC migration/vmstate.o
CC migration/page_cache.o
CC migration/vmstate-types.o
CC migration/qemu-file.o
CC migration/global_state.o
CC migration/qemu-file-channel.o
CC migration/xbzrle.o
CC migration/postcopy-ram.o
CC migration/qjson.o
CC migration/block.o
CC net/net.o
CC net/queue.o
CC net/checksum.o
CC net/util.o
CC net/hub.o
CC net/socket.o
CC net/dump.o
CC net/eth.o
CC net/slirp.o
CC net/filter.o
CC net/filter-buffer.o
CC net/filter-mirror.o
CC net/colo-compare.o
CC net/colo.o
CC net/filter-rewriter.o
CC net/filter-replay.o
CC net/tap-win32.o
CC qom/cpu.o
CC replay/replay.o
CC replay/replay-internal.o
CC replay/replay-events.o
CC replay/replay-time.o
CC replay/replay-input.o
CC replay/replay-snapshot.o
CC replay/replay-char.o
CC replay/replay-audio.o
CC replay/replay-net.o
CC slirp/cksum.o
CC slirp/if.o
CC slirp/ip_icmp.o
CC slirp/ip6_icmp.o
CC slirp/ip6_input.o
CC slirp/ip_input.o
CC slirp/ip6_output.o
CC slirp/ip_output.o
CC slirp/dnssearch.o
CC slirp/dhcpv6.o
CC slirp/slirp.o
CC slirp/mbuf.o
CC slirp/misc.o
CC slirp/sbuf.o
CC slirp/socket.o
CC slirp/tcp_input.o
CC slirp/tcp_output.o
CC slirp/tcp_subr.o
CC slirp/tcp_timer.o
CC slirp/udp.o
CC slirp/udp6.o
CC slirp/bootp.o
CC slirp/tftp.o
CC slirp/arp_table.o
CC slirp/ndp_table.o
CC slirp/ncsi.o
CC ui/keymaps.o
CC ui/console.o
CC ui/cursor.o
CC ui/qemu-pixman.o
CC ui/input.o
CC ui/input-keymap.o
CC ui/input-legacy.o
CC ui/sdl.o
CC ui/sdl_zoom.o
CC ui/vnc.o
CC ui/vnc-enc-zlib.o
CC ui/vnc-enc-hextile.o
CC ui/vnc-enc-tight.o
CC ui/vnc-palette.o
CC ui/vnc-enc-zrle.o
CC ui/vnc-auth-vencrypt.o
CC ui/vnc-ws.o
CC ui/vnc-jobs.o
CC ui/gtk.o
CC chardev/char.o
CC chardev/char-console.o
CC chardev/char-fe.o
CC chardev/char-file.o
CC chardev/char-io.o
CC chardev/char-mux.o
CC chardev/char-null.o
CC chardev/char-pipe.o
CC chardev/char-ringbuf.o
CC chardev/char-serial.o
CC chardev/char-socket.o
CC chardev/char-stdio.o
CC chardev/char-udp.o
CC chardev/char-win.o
CC chardev/char-win-stdio.o
CC qga/commands.o
CC qga/guest-agent-command-state.o
CC qga/main.o
CC qga/commands-win32.o
CC qga/channel-win32.o
AS optionrom/multiboot.o
CC qga/service-win32.o
CC qga/vss-win32.o
AS optionrom/linuxboot.o
CC qga/qapi-generated/qga-qapi-types.o
CC optionrom/linuxboot_dma.o
CC qga/qapi-generated/qga-qapi-visit.o
AS optionrom/kvmvapic.o
BUILD optionrom/multiboot.img
BUILD optionrom/linuxboot.img
BUILD optionrom/kvmvapic.img
CC qga/qapi-generated/qga-qmp-marshal.o
BUILD optionrom/multiboot.raw
BUILD optionrom/linuxboot.raw
AR libqemuutil.a
CC qemu-img.o
BUILD optionrom/linuxboot_dma.img
BUILD optionrom/kvmvapic.raw
SIGN optionrom/multiboot.bin
SIGN optionrom/linuxboot.bin
BUILD optionrom/linuxboot_dma.raw
SIGN optionrom/kvmvapic.bin
SIGN optionrom/linuxboot_dma.bin
LINK qemu-io.exe
LINK qemu-ga.exe
LINK qemu-img.exe
GEN x86_64-softmmu/hmp-commands.h
GEN x86_64-softmmu/hmp-commands-info.h
GEN x86_64-softmmu/config-target.h
GEN aarch64-softmmu/hmp-commands-info.h
GEN aarch64-softmmu/hmp-commands.h
GEN aarch64-softmmu/config-target.h
CC x86_64-softmmu/tcg/tcg.o
CC x86_64-softmmu/exec.o
CC x86_64-softmmu/tcg/optimize.o
CC x86_64-softmmu/tcg/tcg-op.o
CC x86_64-softmmu/fpu/softfloat.o
CC x86_64-softmmu/disas.o
CC x86_64-softmmu/tcg/tcg-common.o
CC aarch64-softmmu/exec.o
GEN x86_64-softmmu/gdbstub-xml.c
CC x86_64-softmmu/arch_init.o
CC x86_64-softmmu/cpus.o
CC x86_64-softmmu/monitor.o
CC x86_64-softmmu/gdbstub.o
CC x86_64-softmmu/balloon.o
CC aarch64-softmmu/tcg/tcg.o
CC x86_64-softmmu/ioport.o
CC aarch64-softmmu/tcg/tcg-op.o
CC aarch64-softmmu/tcg/optimize.o
CC x86_64-softmmu/numa.o
CC x86_64-softmmu/qtest.o
CC aarch64-softmmu/tcg/tcg-common.o
CC aarch64-softmmu/fpu/softfloat.o
CC aarch64-softmmu/disas.o
CC x86_64-softmmu/memory.o
CC x86_64-softmmu/memory_mapping.o
GEN aarch64-softmmu/gdbstub-xml.c
CC aarch64-softmmu/arch_init.o
CC x86_64-softmmu/dump.o
CC aarch64-softmmu/cpus.o
CC x86_64-softmmu/migration/ram.o
CC x86_64-softmmu/accel/accel.o
CC x86_64-softmmu/accel/stubs/hvf-stub.o
CC aarch64-softmmu/monitor.o
CC aarch64-softmmu/gdbstub.o
CC x86_64-softmmu/accel/stubs/kvm-stub.o
CC aarch64-softmmu/balloon.o
CC aarch64-softmmu/ioport.o
CC x86_64-softmmu/accel/tcg/tcg-all.o
CC aarch64-softmmu/numa.o
CC aarch64-softmmu/qtest.o
CC x86_64-softmmu/accel/tcg/cputlb.o
CC aarch64-softmmu/memory.o
CC aarch64-softmmu/memory_mapping.o
CC x86_64-softmmu/accel/tcg/tcg-runtime.o
CC aarch64-softmmu/dump.o
CC aarch64-softmmu/migration/ram.o
CC aarch64-softmmu/accel/accel.o
CC aarch64-softmmu/accel/stubs/hax-stub.o
CC x86_64-softmmu/accel/tcg/cpu-exec.o
CC x86_64-softmmu/accel/tcg/cpu-exec-common.o
CC aarch64-softmmu/accel/stubs/hvf-stub.o
CC aarch64-softmmu/accel/stubs/kvm-stub.o
CC aarch64-softmmu/accel/tcg/tcg-all.o
CC x86_64-softmmu/accel/tcg/translate-all.o
CC aarch64-softmmu/accel/tcg/cputlb.o
CC aarch64-softmmu/accel/tcg/tcg-runtime.o
CC aarch64-softmmu/accel/tcg/cpu-exec.o
CC aarch64-softmmu/accel/tcg/cpu-exec-common.o
CC x86_64-softmmu/accel/tcg/translator.o
CC x86_64-softmmu/hw/block/virtio-blk.o
CC x86_64-softmmu/hw/block/dataplane/virtio-blk.o
CC x86_64-softmmu/hw/char/virtio-serial-bus.o
CC x86_64-softmmu/hw/core/generic-loader.o
CC aarch64-softmmu/accel/tcg/translate-all.o
CC aarch64-softmmu/accel/tcg/translator.o
CC aarch64-softmmu/hw/adc/stm32f2xx_adc.o
CC x86_64-softmmu/hw/core/null-machine.o
CC x86_64-softmmu/hw/display/vga.o
CC x86_64-softmmu/hw/display/virtio-gpu.o
CC aarch64-softmmu/hw/block/virtio-blk.o
CC x86_64-softmmu/hw/display/virtio-gpu-3d.o
CC x86_64-softmmu/hw/display/virtio-gpu-pci.o
CC aarch64-softmmu/hw/block/dataplane/virtio-blk.o
CC aarch64-softmmu/hw/char/exynos4210_uart.o
CC x86_64-softmmu/hw/display/virtio-vga.o
CC aarch64-softmmu/hw/char/omap_uart.o
CC aarch64-softmmu/hw/char/digic-uart.o
CC x86_64-softmmu/hw/intc/apic.o
CC x86_64-softmmu/hw/intc/apic_common.o
CC x86_64-softmmu/hw/intc/ioapic.o
CC aarch64-softmmu/hw/char/stm32f2xx_usart.o
CC x86_64-softmmu/hw/isa/lpc_ich9.o
CC aarch64-softmmu/hw/char/bcm2835_aux.o
CC x86_64-softmmu/hw/misc/pvpanic.o
CC aarch64-softmmu/hw/char/virtio-serial-bus.o
CC x86_64-softmmu/hw/misc/mmio_interface.o
CC aarch64-softmmu/hw/core/generic-loader.o
CC aarch64-softmmu/hw/core/null-machine.o
CC aarch64-softmmu/hw/cpu/arm11mpcore.o
CC x86_64-softmmu/hw/net/virtio-net.o
CC aarch64-softmmu/hw/cpu/realview_mpcore.o
CC aarch64-softmmu/hw/cpu/a9mpcore.o
CC x86_64-softmmu/hw/net/vhost_net.o
CC aarch64-softmmu/hw/cpu/a15mpcore.o
CC x86_64-softmmu/hw/scsi/virtio-scsi.o
CC aarch64-softmmu/hw/display/omap_dss.o
CC aarch64-softmmu/hw/display/omap_lcdc.o
CC x86_64-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC x86_64-softmmu/hw/timer/mc146818rtc.o
CC aarch64-softmmu/hw/display/pxa2xx_lcd.o
CC aarch64-softmmu/hw/display/bcm2835_fb.o
CC x86_64-softmmu/hw/virtio/virtio.o
CC x86_64-softmmu/hw/virtio/virtio-balloon.o
CC aarch64-softmmu/hw/display/vga.o
CC aarch64-softmmu/hw/display/virtio-gpu.o
CC aarch64-softmmu/hw/display/virtio-gpu-3d.o
CC x86_64-softmmu/hw/virtio/virtio-crypto.o
CC x86_64-softmmu/hw/virtio/virtio-crypto-pci.o
CC aarch64-softmmu/hw/display/virtio-gpu-pci.o
CC x86_64-softmmu/hw/i386/multiboot.o
CC aarch64-softmmu/hw/display/dpcd.o
CC x86_64-softmmu/hw/i386/pc.o
CC aarch64-softmmu/hw/display/xlnx_dp.o
CC aarch64-softmmu/hw/dma/xlnx_dpdma.o
CC aarch64-softmmu/hw/dma/omap_dma.o
CC x86_64-softmmu/hw/i386/pc_piix.o
CC x86_64-softmmu/hw/i386/pc_q35.o
CC aarch64-softmmu/hw/dma/soc_dma.o
CC x86_64-softmmu/hw/i386/pc_sysfw.o
CC aarch64-softmmu/hw/dma/pxa2xx_dma.o
CC aarch64-softmmu/hw/dma/bcm2835_dma.o
CC x86_64-softmmu/hw/i386/x86-iommu.o
CC x86_64-softmmu/hw/i386/intel_iommu.o
CC aarch64-softmmu/hw/gpio/omap_gpio.o
CC x86_64-softmmu/hw/i386/amd_iommu.o
CC x86_64-softmmu/hw/i386/vmport.o
CC x86_64-softmmu/hw/i386/vmmouse.o
CC aarch64-softmmu/hw/gpio/imx_gpio.o
CC aarch64-softmmu/hw/gpio/bcm2835_gpio.o
CC x86_64-softmmu/hw/i386/kvmvapic.o
CC x86_64-softmmu/hw/i386/acpi-build.o
CC x86_64-softmmu/target/i386/helper.o
CC aarch64-softmmu/hw/i2c/omap_i2c.o
CC x86_64-softmmu/target/i386/cpu.o
CC x86_64-softmmu/target/i386/gdbstub.o
CC aarch64-softmmu/hw/input/pxa2xx_keypad.o
CC aarch64-softmmu/hw/input/tsc210x.o
CC x86_64-softmmu/target/i386/xsave_helper.o
CC x86_64-softmmu/target/i386/translate.o
CC aarch64-softmmu/hw/intc/armv7m_nvic.o
CC aarch64-softmmu/hw/intc/exynos4210_gic.o
CC x86_64-softmmu/target/i386/bpt_helper.o
CC aarch64-softmmu/hw/intc/exynos4210_combiner.o
CC x86_64-softmmu/target/i386/cc_helper.o
CC aarch64-softmmu/hw/intc/omap_intc.o
CC aarch64-softmmu/hw/intc/bcm2835_ic.o
CC x86_64-softmmu/target/i386/excp_helper.o
CC x86_64-softmmu/target/i386/fpu_helper.o
CC aarch64-softmmu/hw/intc/bcm2836_control.o
CC aarch64-softmmu/hw/intc/allwinner-a10-pic.o
CC x86_64-softmmu/target/i386/int_helper.o
CC x86_64-softmmu/target/i386/mem_helper.o
CC aarch64-softmmu/hw/intc/aspeed_vic.o
CC aarch64-softmmu/hw/intc/arm_gicv3_cpuif.o
CC aarch64-softmmu/hw/misc/arm_sysctl.o
CC x86_64-softmmu/target/i386/misc_helper.o
CC aarch64-softmmu/hw/misc/cbus.o
CC aarch64-softmmu/hw/misc/exynos4210_pmu.o
CC aarch64-softmmu/hw/misc/exynos4210_clk.o
CC aarch64-softmmu/hw/misc/exynos4210_rng.o
CC x86_64-softmmu/target/i386/mpx_helper.o
CC aarch64-softmmu/hw/misc/imx_ccm.o
CC aarch64-softmmu/hw/misc/imx31_ccm.o
CC x86_64-softmmu/target/i386/seg_helper.o
CC aarch64-softmmu/hw/misc/imx25_ccm.o
CC x86_64-softmmu/target/i386/smm_helper.o
CC x86_64-softmmu/target/i386/svm_helper.o
CC x86_64-softmmu/target/i386/machine.o
CC aarch64-softmmu/hw/misc/imx6_ccm.o
CC x86_64-softmmu/target/i386/arch_memory_mapping.o
CC x86_64-softmmu/target/i386/arch_dump.o
CC aarch64-softmmu/hw/misc/imx6_src.o
CC x86_64-softmmu/target/i386/monitor.o
CC aarch64-softmmu/hw/misc/mst_fpga.o
CC x86_64-softmmu/target/i386/kvm-stub.o
CC x86_64-softmmu/target/i386/hax-all.o
CC aarch64-softmmu/hw/misc/omap_clk.o
CC aarch64-softmmu/hw/misc/omap_gpmc.o
CC x86_64-softmmu/target/i386/hax-mem.o
CC aarch64-softmmu/hw/misc/omap_l4.o
CC x86_64-softmmu/target/i386/hax-windows.o
CC aarch64-softmmu/hw/misc/omap_sdrc.o
GEN trace/generated-helpers.c
CC aarch64-softmmu/hw/misc/omap_tap.o
CC aarch64-softmmu/hw/misc/bcm2835_mbox.o
CC aarch64-softmmu/hw/misc/bcm2835_property.o
CC aarch64-softmmu/hw/misc/bcm2835_rng.o
CC x86_64-softmmu/trace/control-target.o
CC aarch64-softmmu/hw/misc/zynq_slcr.o
CC aarch64-softmmu/hw/misc/zynq-xadc.o
CC aarch64-softmmu/hw/misc/stm32f2xx_syscfg.o
CC aarch64-softmmu/hw/misc/mps2-scc.o
CC x86_64-softmmu/gdbstub-xml.o
CC aarch64-softmmu/hw/misc/auxbus.o
CC aarch64-softmmu/hw/misc/aspeed_scu.o
CC aarch64-softmmu/hw/misc/aspeed_sdmc.o
CC x86_64-softmmu/trace/generated-helpers.o
CC aarch64-softmmu/hw/misc/mmio_interface.o
CC aarch64-softmmu/hw/misc/msf2-sysreg.o
CC aarch64-softmmu/hw/net/virtio-net.o
CC aarch64-softmmu/hw/net/vhost_net.o
CC aarch64-softmmu/hw/pcmcia/pxa2xx.o
CC aarch64-softmmu/hw/scsi/virtio-scsi.o
CC aarch64-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC aarch64-softmmu/hw/sd/omap_mmc.o
CC aarch64-softmmu/hw/sd/pxa2xx_mmci.o
CC aarch64-softmmu/hw/sd/bcm2835_sdhost.o
LINK x86_64-softmmu/qemu-system-x86_64w.exe
CC aarch64-softmmu/hw/ssi/omap_spi.o
CC aarch64-softmmu/hw/ssi/imx_spi.o
CC aarch64-softmmu/hw/timer/exynos4210_mct.o
CC aarch64-softmmu/hw/timer/exynos4210_pwm.o
CC aarch64-softmmu/hw/timer/exynos4210_rtc.o
CC aarch64-softmmu/hw/timer/omap_gptimer.o
CC aarch64-softmmu/hw/timer/omap_synctimer.o
CC aarch64-softmmu/hw/timer/pxa2xx_timer.o
CC aarch64-softmmu/hw/timer/digic-timer.o
CC aarch64-softmmu/hw/timer/allwinner-a10-pit.o
CC aarch64-softmmu/hw/usb/tusb6010.o
CC aarch64-softmmu/hw/virtio/virtio.o
CC aarch64-softmmu/hw/virtio/virtio-balloon.o
CC aarch64-softmmu/hw/virtio/virtio-crypto.o
CC aarch64-softmmu/hw/virtio/virtio-crypto-pci.o
CC aarch64-softmmu/hw/arm/boot.o
CC aarch64-softmmu/hw/arm/collie.o
CC aarch64-softmmu/hw/arm/exynos4_boards.o
CC aarch64-softmmu/hw/arm/gumstix.o
CC aarch64-softmmu/hw/arm/highbank.o
CC aarch64-softmmu/hw/arm/digic_boards.o
CC aarch64-softmmu/hw/arm/integratorcp.o
CC aarch64-softmmu/hw/arm/mainstone.o
CC aarch64-softmmu/hw/arm/musicpal.o
CC aarch64-softmmu/hw/arm/nseries.o
CC aarch64-softmmu/hw/arm/omap_sx1.o
CC aarch64-softmmu/hw/arm/palm.o
CC aarch64-softmmu/hw/arm/realview.o
CC aarch64-softmmu/hw/arm/spitz.o
CC aarch64-softmmu/hw/arm/stellaris.o
CC aarch64-softmmu/hw/arm/tosa.o
CC aarch64-softmmu/hw/arm/versatilepb.o
CC aarch64-softmmu/hw/arm/vexpress.o
CC aarch64-softmmu/hw/arm/virt.o
CC aarch64-softmmu/hw/arm/xilinx_zynq.o
CC aarch64-softmmu/hw/arm/z2.o
CC aarch64-softmmu/hw/arm/virt-acpi-build.o
CC aarch64-softmmu/hw/arm/netduino2.o
CC aarch64-softmmu/hw/arm/sysbus-fdt.o
CC aarch64-softmmu/hw/arm/armv7m.o
CC aarch64-softmmu/hw/arm/exynos4210.o
CC aarch64-softmmu/hw/arm/pxa2xx.o
CC aarch64-softmmu/hw/arm/pxa2xx_gpio.o
CC aarch64-softmmu/hw/arm/pxa2xx_pic.o
CC aarch64-softmmu/hw/arm/digic.o
CC aarch64-softmmu/hw/arm/omap1.o
CC aarch64-softmmu/hw/arm/omap2.o
CC aarch64-softmmu/hw/arm/strongarm.o
CC aarch64-softmmu/hw/arm/allwinner-a10.o
CC aarch64-softmmu/hw/arm/cubieboard.o
CC aarch64-softmmu/hw/arm/bcm2835_peripherals.o
CC aarch64-softmmu/hw/arm/bcm2836.o
CC aarch64-softmmu/hw/arm/raspi.o
CC aarch64-softmmu/hw/arm/stm32f205_soc.o
CC aarch64-softmmu/hw/arm/xlnx-zynqmp.o
CC aarch64-softmmu/hw/arm/xlnx-zcu102.o
CC aarch64-softmmu/hw/arm/fsl-imx25.o
CC aarch64-softmmu/hw/arm/imx25_pdk.o
CC aarch64-softmmu/hw/arm/fsl-imx31.o
CC aarch64-softmmu/hw/arm/kzm.o
CC aarch64-softmmu/hw/arm/fsl-imx6.o
CC aarch64-softmmu/hw/arm/sabrelite.o
CC aarch64-softmmu/hw/arm/aspeed_soc.o
CC aarch64-softmmu/hw/arm/mps2.o
CC aarch64-softmmu/hw/arm/aspeed.o
CC aarch64-softmmu/hw/arm/msf2-soc.o
CC aarch64-softmmu/hw/arm/msf2-som.o
CC aarch64-softmmu/hw/arm/smmu-common.o
CC aarch64-softmmu/hw/arm/smmuv3.o
CC aarch64-softmmu/target/arm/machine.o
CC aarch64-softmmu/target/arm/arm-semi.o
CC aarch64-softmmu/target/arm/psci.o
CC aarch64-softmmu/target/arm/arch_dump.o
CC aarch64-softmmu/target/arm/monitor.o
CC aarch64-softmmu/target/arm/kvm-stub.o
CC aarch64-softmmu/target/arm/translate.o
CC aarch64-softmmu/target/arm/op_helper.o
CC aarch64-softmmu/target/arm/helper.o
CC aarch64-softmmu/target/arm/cpu.o
CC aarch64-softmmu/target/arm/neon_helper.o
CC aarch64-softmmu/target/arm/iwmmxt_helper.o
CC aarch64-softmmu/target/arm/gdbstub.o
CC aarch64-softmmu/target/arm/cpu64.o
CC aarch64-softmmu/target/arm/translate-a64.o
In file included from /tmp/qemu-test/src/hw/arm/smmuv3.c:31:0:
/tmp/qemu-test/src/hw/arm/smmuv3-internal.h: In function 'smmu_read64':
/tmp/qemu-test/src/hw/arm/smmuv3-internal.h:146:9: error: implicit declaration of function 'qemu_log_mask' [-Werror=implicit-function-declaration]
qemu_log_mask(LOG_GUEST_ERROR,
^~~~~~~~~~~~~
/tmp/qemu-test/src/hw/arm/smmuv3-internal.h:146:9: error: nested extern declaration of 'qemu_log_mask' [-Werror=nested-externs]
/tmp/qemu-test/src/hw/arm/smmuv3-internal.h:146:23: error: 'LOG_GUEST_ERROR' undeclared (first use in this function)
qemu_log_mask(LOG_GUEST_ERROR,
^~~~~~~~~~~~~~~
/tmp/qemu-test/src/hw/arm/smmuv3-internal.h:146:23: note: each undeclared identifier is reported only once for each function it appears in
/tmp/qemu-test/src/hw/arm/smmuv3-internal.h: In function 'smmu_write64':
/tmp/qemu-test/src/hw/arm/smmuv3-internal.h:165:23: error: 'LOG_GUEST_ERROR' undeclared (first use in this function)
qemu_log_mask(LOG_GUEST_ERROR,
^~~~~~~~~~~~~~~
/tmp/qemu-test/src/hw/arm/smmuv3.c: In function 'smmuv3_write_gerrorn':
/tmp/qemu-test/src/hw/arm/smmuv3.c:86:23: error: 'LOG_GUEST_ERROR' undeclared (first use in this function)
qemu_log_mask(LOG_GUEST_ERROR,
^~~~~~~~~~~~~~~
/tmp/qemu-test/src/hw/arm/smmuv3.c: In function 'smmu_get_ste':
/tmp/qemu-test/src/hw/arm/smmuv3.c:304:23: error: 'LOG_GUEST_ERROR' undeclared (first use in this function)
qemu_log_mask(LOG_GUEST_ERROR,
^~~~~~~~~~~~~~~
/tmp/qemu-test/src/hw/arm/smmuv3.c: In function 'smmu_get_cd':
/tmp/qemu-test/src/hw/arm/smmuv3.c:325:23: error: 'LOG_GUEST_ERROR' undeclared (first use in this function)
qemu_log_mask(LOG_GUEST_ERROR,
^~~~~~~~~~~~~~~
/tmp/qemu-test/src/hw/arm/smmuv3.c: In function 'smmu_write_mmio':
/tmp/qemu-test/src/hw/arm/smmuv3.c:710:23: error: 'LOG_GUEST_ERROR' undeclared (first use in this function)
qemu_log_mask(LOG_GUEST_ERROR,
^~~~~~~~~~~~~~~
/tmp/qemu-test/src/hw/arm/smmuv3.c: In function 'smmu_read_mmio':
/tmp/qemu-test/src/hw/arm/smmuv3.c:818:23: error: 'LOG_GUEST_ERROR' undeclared (first use in this function)
qemu_log_mask(LOG_GUEST_ERROR, "SMMUv3 MMIO read: bad size %u\n", size);
^~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
make[1]: *** [hw/arm/smmuv3.o] Error 1
make[1]: *** Waiting for unfinished jobs....
/tmp/qemu-test/src/rules.mak:66: recipe for target 'hw/arm/smmuv3.o' failed
/tmp/qemu-test/src/hw/arm/smmu-common.c: In function 'get_pte':
/tmp/qemu-test/src/hw/arm/smmu-common.c:52:9: error: implicit declaration of function 'qemu_log_mask' [-Werror=implicit-function-declaration]
qemu_log_mask(LOG_GUEST_ERROR,
^~~~~~~~~~~~~
/tmp/qemu-test/src/hw/arm/smmu-common.c:52:9: error: nested extern declaration of 'qemu_log_mask' [-Werror=nested-externs]
/tmp/qemu-test/src/hw/arm/smmu-common.c:52:23: error: 'LOG_GUEST_ERROR' undeclared (first use in this function)
qemu_log_mask(LOG_GUEST_ERROR,
^~~~~~~~~~~~~~~
/tmp/qemu-test/src/hw/arm/smmu-common.c:52:23: note: each undeclared identifier is reported only once for each function it appears in
cc1: all warnings being treated as errors
make[1]: *** [hw/arm/smmu-common.o] Error 1
/tmp/qemu-test/src/rules.mak:66: recipe for target 'hw/arm/smmu-common.o' failed
GEN x86_64-softmmu/qemu-system-x86_64.exe
Makefile:403: recipe for target 'subdir-aarch64-softmmu' failed
make: *** [subdir-aarch64-softmmu] Error 2
Traceback (most recent call last):
File "./tests/docker/docker.py", line 407, in <module>
sys.exit(main())
File "./tests/docker/docker.py", line 404, in main
return args.cmdobj.run(args, argv)
File "./tests/docker/docker.py", line 261, in run
return Docker().run(argv, args.keep, quiet=args.quiet)
File "./tests/docker/docker.py", line 229, in run
quiet=quiet)
File "./tests/docker/docker.py", line 147, in _do_check
return subprocess.check_call(self._command + cmd, **kwargs)
File "/usr/lib64/python2.7/subprocess.py", line 186, in check_call
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['docker', 'run', '--label', 'com.qemu.instance.uuid=ef6dda8c0a8311e8bac352540069c830', '-u', '0', '--security-opt', 'seccomp=unconfined', '--rm', '--net=none', '-e', 'TARGET_LIST=', '-e', 'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=8', '-e', 'DEBUG=', '-e', 'SHOW_ENV=1', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', '/root/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', '/var/tmp/patchew-tester-tmp-iv9dq1c5/src/docker-src.2018-02-05-09.50.27.14305:/var/tmp/qemu:z,ro', 'qemu:fedora', '/var/tmp/qemu/run', 'test-mingw']' returned non-zero exit status 2
make[1]: *** [tests/docker/Makefile.include:129: docker-run] Error 1
make: *** [tests/docker/Makefile.include:163: docker-run-test-mingw@fedora] Error 2
real 2m38.217s
user 0m5.050s
sys 0m3.655s
=== OUTPUT END ===
Test command exited with code: 2
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support
2018-02-05 14:53 ` [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support no-reply
@ 2018-02-06 12:22 ` Auger Eric
2018-02-06 12:45 ` Peter Maydell
0 siblings, 1 reply; 18+ messages in thread
From: Auger Eric @ 2018-02-06 12:22 UTC (permalink / raw)
To: qemu-devel
Cc: famz, eric.auger.pro, peter.maydell, qemu-arm, prem.mallappa,
alex.williamson, mst, jean-philippe.brucker, tn, peterx,
edgar.iglesias, linuc.decode, bharat.bhushan, christoffer.dall
Hi,
On 05/02/18 15:53, no-reply@patchew.org wrote:
> Hi,
>
> This series failed docker-mingw@fedora build test. Please find the testing commands and
> their output below. If you have Docker installed, you can probably reproduce it
> locally.
>
> Type: series
> Message-id: 1517837972-1904-1-git-send-email-eric.auger@redhat.com
> Subject: [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support
>
> === TEST SCRIPT BEGIN ===
> #!/bin/bash
> set -e
> git submodule update --init dtc
> # Let docker tests dump environment info
> export SHOW_ENV=1
> export J=8
> time make docker-test-mingw@fedora
> === TEST SCRIPT END ===
>
> Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
> Switched to a new branch 'test'
> 0de28f0913 hw/arm/virt: Handle iommu in 2.12 machine type
> 378fb2a110 hw/arm/virt-acpi-build: Add smmuv3 node in IORT table
> 1b05b53e57 hw/arm/virt: Add SMMUv3 to the virt board
> b4d6a42305 target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route
> c752d8b106 hw/arm/smmuv3: Abort on vfio or vhost case
> 6afc32e7e2 hw/arm/smmuv3: Implement translate callback
> 9742c3be12 hw/arm/smmuv3: Event queue recording helper
> d081ee8e3a hw/arm/smmuv3: Implement MMIO write operations
> cc76d86618 hw/arm/smmuv3: Queue helpers
> da5755141c hw/arm/smmuv3: Wired IRQ and GERROR helpers
> 6ad76bdfc8 hw/arm/smmuv3: Skeleton
> 34f1fde2fe hw/arm/smmu-common: VMSAv8-64 page table walk
> 8c73cc5199 hw/arm/smmu-common: IOMMU memory region and address space setup
> e523e3be5e hw/arm/smmu-common: smmu base device and datatypes
>
> === OUTPUT BEGIN ===
> Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc'
> Cloning into '/var/tmp/patchew-tester-tmp-iv9dq1c5/src/dtc'...
> Submodule path 'dtc': checked out 'e54388015af1fb4bf04d0bca99caba1074d9cc42'
> BUILD fedora
> GEN /var/tmp/patchew-tester-tmp-iv9dq1c5/src/docker-src.2018-02-05-09.50.27.14305/qemu.tar
> Cloning into '/var/tmp/patchew-tester-tmp-iv9dq1c5/src/docker-src.2018-02-05-09.50.27.14305/qemu.tar.vroot'...
> done.
> Your branch is up-to-date with 'origin/test'.
> Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc'
> Cloning into '/var/tmp/patchew-tester-tmp-iv9dq1c5/src/docker-src.2018-02-05-09.50.27.14305/qemu.tar.vroot/dtc'...
> Submodule path 'dtc': checked out 'e54388015af1fb4bf04d0bca99caba1074d9cc42'
> Submodule 'ui/keycodemapdb' (git://git.qemu.org/keycodemapdb.git) registered for path 'ui/keycodemapdb'
> Cloning into '/var/tmp/patchew-tester-tmp-iv9dq1c5/src/docker-src.2018-02-05-09.50.27.14305/qemu.tar.vroot/ui/keycodemapdb'...
> Submodule path 'ui/keycodemapdb': checked out '10739aa26051a5d49d88132604539d3ed085e72e'
> COPY RUNNER
> RUN test-mingw in qemu:fedora
> Packages installed:
> PyYAML-3.11-13.fc25.x86_64
> SDL-devel-1.2.15-21.fc24.x86_64
> bc-1.06.95-16.fc24.x86_64
> bison-3.0.4-4.fc24.x86_64
> bzip2-1.0.6-21.fc25.x86_64
> ccache-3.3.4-1.fc25.x86_64
> clang-3.9.1-2.fc25.x86_64
> findutils-4.6.0-8.fc25.x86_64
> flex-2.6.0-3.fc25.x86_64
> gcc-6.4.1-1.fc25.x86_64
> gcc-c++-6.4.1-1.fc25.x86_64
> gettext-0.19.8.1-3.fc25.x86_64
> git-2.9.5-3.fc25.x86_64
> glib2-devel-2.50.3-1.fc25.x86_64
> hostname-3.15-8.fc25.x86_64
> libaio-devel-0.3.110-6.fc24.x86_64
> libasan-6.4.1-1.fc25.x86_64
> libfdt-devel-1.4.2-1.fc25.x86_64
> libubsan-6.4.1-1.fc25.x86_64
> make-4.1-6.fc25.x86_64
> mingw32-SDL-1.2.15-7.fc24.noarch
> mingw32-bzip2-1.0.6-7.fc24.noarch
> mingw32-curl-7.47.0-1.fc24.noarch
> mingw32-glib2-2.50.3-1.fc25.noarch
> mingw32-gmp-6.1.1-1.fc25.noarch
> mingw32-gnutls-3.5.5-2.fc25.noarch
> mingw32-gtk2-2.24.31-2.fc25.noarch
> mingw32-gtk3-3.22.17-1.fc25.noarch
> mingw32-libjpeg-turbo-1.5.1-1.fc25.noarch
> mingw32-libpng-1.6.27-1.fc25.noarch
> mingw32-libssh2-1.4.3-5.fc24.noarch
> mingw32-libtasn1-4.9-1.fc25.noarch
> mingw32-nettle-3.3-1.fc25.noarch
> mingw32-pixman-0.34.0-1.fc25.noarch
> mingw32-pkg-config-0.28-6.fc24.x86_64
> mingw64-SDL-1.2.15-7.fc24.noarch
> mingw64-bzip2-1.0.6-7.fc24.noarch
> mingw64-curl-7.47.0-1.fc24.noarch
> mingw64-glib2-2.50.3-1.fc25.noarch
> mingw64-gmp-6.1.1-1.fc25.noarch
> mingw64-gnutls-3.5.5-2.fc25.noarch
> mingw64-gtk2-2.24.31-2.fc25.noarch
> mingw64-gtk3-3.22.17-1.fc25.noarch
> mingw64-libjpeg-turbo-1.5.1-1.fc25.noarch
> mingw64-libpng-1.6.27-1.fc25.noarch
> mingw64-libssh2-1.4.3-5.fc24.noarch
> mingw64-libtasn1-4.9-1.fc25.noarch
> mingw64-nettle-3.3-1.fc25.noarch
> mingw64-pixman-0.34.0-1.fc25.noarch
> mingw64-pkg-config-0.28-6.fc24.x86_64
> nettle-devel-3.3-1.fc25.x86_64
> package python2 is not installed
> perl-5.24.3-389.fc25.x86_64
> pixman-devel-0.34.0-2.fc24.x86_64
> sparse-0.5.0-10.fc25.x86_64
> tar-1.29-3.fc25.x86_64
> which-2.21-1.fc25.x86_64
> zlib-devel-1.2.8-10.fc24.x86_64
>
> Environment variables:
> PACKAGES=ccache gettext git tar PyYAML sparse flex bison python2 bzip2 hostname glib2-devel pixman-devel zlib-devel SDL-devel libfdt-devel gcc gcc-c++ clang make perl which bc findutils libaio-devel nettle-devel libasan libubsan mingw32-pixman mingw32-glib2 mingw32-gmp mingw32-SDL mingw32-pkg-config mingw32-gtk2 mingw32-gtk3 mingw32-gnutls mingw32-nettle mingw32-libtasn1 mingw32-libjpeg-turbo mingw32-libpng mingw32-curl mingw32-libssh2 mingw32-bzip2 mingw64-pixman mingw64-glib2 mingw64-gmp mingw64-SDL mingw64-pkg-config mingw64-gtk2 mingw64-gtk3 mingw64-gnutls mingw64-nettle mingw64-libtasn1 mingw64-libjpeg-turbo mingw64-libpng mingw64-curl mingw64-libssh2 mingw64-bzip2
> HOSTNAME=25a43af2202b
> MAKEFLAGS= -j8
> J=8
> CCACHE_DIR=/var/tmp/ccache
> EXTRA_CONFIGURE_OPTS=
> V=
> SHOW_ENV=1
> PATH=/usr/lib/ccache:/usr/lib64/ccache:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
> PWD=/
> TARGET_LIST=
> FGC=f25
> SHLVL=1
> HOME=/root
> TEST_DIR=/tmp/qemu-test
> DISTTAG=f25container
> FEATURES=mingw clang pyyaml asan dtc
> DEBUG=
> _=/usr/bin/env
>
> Configure options:
> --enable-werror --target-list=x86_64-softmmu,aarch64-softmmu --prefix=/tmp/qemu-test/install --cross-prefix=x86_64-w64-mingw32- --enable-trace-backends=simple --enable-gnutls --enable-nettle --enable-curl --enable-vnc --enable-bzip2 --enable-guest-agent --with-sdlabi=1.2 --with-gtkabi=2.0
> Install prefix /tmp/qemu-test/install
> BIOS directory /tmp/qemu-test/install
> firmware path /tmp/qemu-test/install/share/qemu-firmware
> binary directory /tmp/qemu-test/install
> library directory /tmp/qemu-test/install/lib
> module directory /tmp/qemu-test/install/lib
> libexec directory /tmp/qemu-test/install/libexec
> include directory /tmp/qemu-test/install/include
> config directory /tmp/qemu-test/install
> local state directory queried at runtime
> Windows SDK no
> Source path /tmp/qemu-test/src
> GIT binary git
> GIT submodules
> C compiler x86_64-w64-mingw32-gcc
> Host C compiler cc
> C++ compiler x86_64-w64-mingw32-g++
> Objective-C compiler clang
> ARFLAGS rv
> CFLAGS -O2 -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 -g
> QEMU_CFLAGS -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/pixman-1 -I$(SRC_PATH)/dtc/libfdt -Werror -mms-bitfields -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/glib-2.0 -I/usr/x86_64-w64-mingw32/sys-root/mingw/lib/glib-2.0/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -m64 -mcx16 -mthreads -D__USE_MINGW_ANSI_STDIO=1 -DWIN32_LEAN_AND_MEAN -DWINVER=0x501 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -Wendif-labels -Wno-shift-negative-value -Wno-missing-include-dirs -Wempty-body -Wnested-externs -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wold-style-declaration -Wold-style-definition -Wtype-limits -fstack-protector-strong -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/p11-kit-1 -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/libpng16
> LDFLAGS -Wl,--nxcompat -Wl,--no-seh -Wl,--dynamicbase -Wl,--warn-common -m64 -g
> make make
> install install
> python python -B
> smbd /usr/sbin/smbd
> module support no
> host CPU x86_64
> host big endian no
> target list x86_64-softmmu aarch64-softmmu
> gprof enabled no
> sparse enabled no
> strip binaries yes
> profiler no
> static build no
> SDL support yes (1.2.15)
> GTK support yes (2.24.31)
> GTK GL support no
> VTE support no
> TLS priority NORMAL
> GNUTLS support yes
> GNUTLS rnd yes
> libgcrypt no
> libgcrypt kdf no
> nettle yes (3.3)
> nettle kdf yes
> libtasn1 yes
> curses support no
> virgl support no
> curl support yes
> mingw32 support yes
> Audio drivers dsound
> Block whitelist (rw)
> Block whitelist (ro)
> VirtFS support no
> Multipath support no
> VNC support yes
> VNC SASL support no
> VNC JPEG support yes
> VNC PNG support yes
> xen support no
> brlapi support no
> bluez support no
> Documentation no
> PIE no
> vde support no
> netmap support no
> Linux AIO support no
> ATTR/XATTR support no
> Install blobs yes
> KVM support no
> HAX support yes
> HVF support no
> TCG support yes
> TCG debug enabled no
> TCG interpreter no
> malloc trim support no
> RDMA support no
> fdt support yes
> preadv support no
> fdatasync no
> madvise no
> posix_madvise no
> libcap-ng support no
> vhost-net support no
> vhost-scsi support no
> vhost-vsock support no
> vhost-user support no
> Trace backends simple
> Trace output file trace-<pid>
> spice support no
> rbd support no
> xfsctl support no
> smartcard support no
> libusb no
> usb net redir no
> OpenGL support no
> OpenGL dmabufs no
> libiscsi support no
> libnfs support no
> build guest agent yes
> QGA VSS support no
> QGA w32 disk info yes
> QGA MSI support no
> seccomp support no
> coroutine backend win32
> coroutine pool yes
> debug stack usage no
> crypto afalg no
> GlusterFS support no
> gcov gcov
> gcov enabled no
> TPM support yes
> libssh2 support yes
> TPM passthrough no
> TPM emulator no
> QOM debugging yes
> Live block migration yes
> lzo support no
> snappy support no
> bzip2 support yes
> NUMA host support no
> libxml2 no
> tcmalloc support no
> jemalloc support no
> avx2 optimization yes
> replication support yes
> VxHS block device no
> capstone no
>
> WARNING: Use of GTK 2.0 is deprecated and will be removed in
> WARNING: future releases. Please switch to using GTK 3.0
>
> WARNING: Use of SDL 1.2 is deprecated and will be removed in
> WARNING: future releases. Please switch to using SDL 2.0
> GEN x86_64-softmmu/config-devices.mak.tmp
> GEN aarch64-softmmu/config-devices.mak.tmp
> GEN config-host.h
> GEN qemu-options.def
> GEN qmp-commands.h
> GEN qapi-types.h
> GEN qapi-visit.h
> GEN qapi-event.h
> GEN x86_64-softmmu/config-devices.mak
> GEN qmp-marshal.c
> GEN aarch64-softmmu/config-devices.mak
> GEN qapi-types.c
> GEN qapi-visit.c
> GEN qapi-event.c
> GEN qmp-introspect.h
> GEN qmp-introspect.c
> GEN trace/generated-tcg-tracers.h
> GEN trace/generated-helpers-wrappers.h
> GEN trace/generated-helpers.h
> GEN trace/generated-helpers.c
> GEN module_block.h
> GEN ui/input-keymap-atset1-to-qcode.c
> GEN ui/input-keymap-linux-to-qcode.c
> GEN ui/input-keymap-qcode-to-atset1.c
> GEN ui/input-keymap-qcode-to-atset2.c
> GEN ui/input-keymap-qcode-to-atset3.c
> GEN ui/input-keymap-qcode-to-linux.c
> GEN ui/input-keymap-qcode-to-qnum.c
> GEN ui/input-keymap-qcode-to-sun.c
> GEN ui/input-keymap-qnum-to-qcode.c
> GEN ui/input-keymap-usb-to-qcode.c
> GEN ui/input-keymap-win32-to-qcode.c
> GEN ui/input-keymap-x11-to-qcode.c
> GEN ui/input-keymap-xorgevdev-to-qcode.c
> GEN ui/input-keymap-xorgkbd-to-qcode.c
> GEN ui/input-keymap-xorgxquartz-to-qcode.c
> GEN ui/input-keymap-xorgxwin-to-qcode.c
> GEN tests/test-qapi-types.h
> GEN tests/test-qapi-visit.h
> GEN tests/test-qmp-commands.h
> GEN tests/test-qapi-event.h
> GEN tests/test-qmp-introspect.h
> GEN trace-root.h
> GEN util/trace.h
> GEN crypto/trace.h
> GEN io/trace.h
> GEN migration/trace.h
> GEN block/trace.h
> GEN chardev/trace.h
> GEN hw/block/trace.h
> GEN hw/block/dataplane/trace.h
> GEN hw/char/trace.h
> GEN hw/intc/trace.h
> GEN hw/net/trace.h
> GEN hw/virtio/trace.h
> GEN hw/audio/trace.h
> GEN hw/misc/trace.h
> GEN hw/usb/trace.h
> GEN hw/scsi/trace.h
> GEN hw/nvram/trace.h
> GEN hw/display/trace.h
> GEN hw/input/trace.h
> GEN hw/timer/trace.h
> GEN hw/dma/trace.h
> GEN hw/sparc/trace.h
> GEN hw/sparc64/trace.h
> GEN hw/sd/trace.h
> GEN hw/isa/trace.h
> GEN hw/mem/trace.h
> GEN hw/i386/trace.h
> GEN hw/i386/xen/trace.h
> GEN hw/9pfs/trace.h
> GEN hw/ppc/trace.h
> GEN hw/pci/trace.h
> GEN hw/pci-host/trace.h
> GEN hw/s390x/trace.h
> GEN hw/vfio/trace.h
> GEN hw/acpi/trace.h
> GEN hw/arm/trace.h
> GEN hw/alpha/trace.h
> GEN hw/hppa/trace.h
> GEN hw/xen/trace.h
> GEN hw/ide/trace.h
> GEN ui/trace.h
> GEN audio/trace.h
> GEN net/trace.h
> GEN target/arm/trace.h
> GEN target/i386/trace.h
> GEN target/mips/trace.h
> GEN target/sparc/trace.h
> GEN target/s390x/trace.h
> GEN target/ppc/trace.h
> GEN qom/trace.h
> GEN linux-user/trace.h
> GEN qapi/trace.h
> GEN accel/tcg/trace.h
> GEN accel/kvm/trace.h
> GEN nbd/trace.h
> GEN scsi/trace.h
> GEN trace-root.c
> GEN util/trace.c
> GEN crypto/trace.c
> GEN io/trace.c
> GEN migration/trace.c
> GEN block/trace.c
> GEN chardev/trace.c
> GEN hw/block/trace.c
> GEN hw/block/dataplane/trace.c
> GEN hw/char/trace.c
> GEN hw/intc/trace.c
> GEN hw/net/trace.c
> GEN hw/virtio/trace.c
> GEN hw/audio/trace.c
> GEN hw/misc/trace.c
> GEN hw/usb/trace.c
> GEN hw/scsi/trace.c
> GEN hw/nvram/trace.c
> GEN hw/display/trace.c
> GEN hw/input/trace.c
> GEN hw/timer/trace.c
> GEN hw/dma/trace.c
> GEN hw/sparc/trace.c
> GEN hw/sparc64/trace.c
> GEN hw/sd/trace.c
> GEN hw/isa/trace.c
> GEN hw/mem/trace.c
> GEN hw/i386/trace.c
> GEN hw/i386/xen/trace.c
> GEN hw/9pfs/trace.c
> GEN hw/ppc/trace.c
> GEN hw/pci/trace.c
> GEN hw/pci-host/trace.c
> GEN hw/s390x/trace.c
> GEN hw/vfio/trace.c
> GEN hw/acpi/trace.c
> GEN hw/arm/trace.c
> GEN hw/hppa/trace.c
> GEN hw/alpha/trace.c
> GEN hw/xen/trace.c
> GEN hw/ide/trace.c
> GEN ui/trace.c
> GEN audio/trace.c
> GEN net/trace.c
> GEN target/arm/trace.c
> GEN target/i386/trace.c
> GEN target/mips/trace.c
> GEN target/sparc/trace.c
> GEN target/s390x/trace.c
> GEN target/ppc/trace.c
> GEN qom/trace.c
> GEN linux-user/trace.c
> GEN qapi/trace.c
> GEN accel/tcg/trace.c
> GEN accel/kvm/trace.c
> GEN nbd/trace.c
> GEN scsi/trace.c
> GEN config-all-devices.mak
> DEP /tmp/qemu-test/src/dtc/tests/dumptrees.c
> DEP /tmp/qemu-test/src/dtc/tests/value-labels.c
> DEP /tmp/qemu-test/src/dtc/tests/trees.S
> DEP /tmp/qemu-test/src/dtc/tests/testutils.c
> DEP /tmp/qemu-test/src/dtc/tests/asm_tree_dump.c
> DEP /tmp/qemu-test/src/dtc/tests/truncated_property.c
> DEP /tmp/qemu-test/src/dtc/tests/check_path.c
> DEP /tmp/qemu-test/src/dtc/tests/overlay_bad_fixup.c
> DEP /tmp/qemu-test/src/dtc/tests/overlay.c
> DEP /tmp/qemu-test/src/dtc/tests/property_iterate.c
> DEP /tmp/qemu-test/src/dtc/tests/subnode_iterate.c
> DEP /tmp/qemu-test/src/dtc/tests/integer-expressions.c
> DEP /tmp/qemu-test/src/dtc/tests/add_subnode_with_nops.c
> DEP /tmp/qemu-test/src/dtc/tests/path_offset_aliases.c
> DEP /tmp/qemu-test/src/dtc/tests/utilfdt_test.c
> DEP /tmp/qemu-test/src/dtc/tests/dtbs_equal_unordered.c
> DEP /tmp/qemu-test/src/dtc/tests/dtb_reverse.c
> DEP /tmp/qemu-test/src/dtc/tests/dtbs_equal_ordered.c
> DEP /tmp/qemu-test/src/dtc/tests/extra-terminating-null.c
> DEP /tmp/qemu-test/src/dtc/tests/incbin.c
> DEP /tmp/qemu-test/src/dtc/tests/boot-cpuid.c
> DEP /tmp/qemu-test/src/dtc/tests/phandle_format.c
> DEP /tmp/qemu-test/src/dtc/tests/references.c
> DEP /tmp/qemu-test/src/dtc/tests/string_escapes.c
> DEP /tmp/qemu-test/src/dtc/tests/path-references.c
> DEP /tmp/qemu-test/src/dtc/tests/propname_escapes.c
> DEP /tmp/qemu-test/src/dtc/tests/appendprop2.c
> DEP /tmp/qemu-test/src/dtc/tests/appendprop1.c
> DEP /tmp/qemu-test/src/dtc/tests/del_property.c
> DEP /tmp/qemu-test/src/dtc/tests/del_node.c
> DEP /tmp/qemu-test/src/dtc/tests/setprop.c
> DEP /tmp/qemu-test/src/dtc/tests/set_name.c
> DEP /tmp/qemu-test/src/dtc/tests/rw_tree1.c
> DEP /tmp/qemu-test/src/dtc/tests/open_pack.c
> DEP /tmp/qemu-test/src/dtc/tests/nopulate.c
> DEP /tmp/qemu-test/src/dtc/tests/mangle-layout.c
> DEP /tmp/qemu-test/src/dtc/tests/move_and_save.c
> DEP /tmp/qemu-test/src/dtc/tests/sw_tree1.c
> DEP /tmp/qemu-test/src/dtc/tests/nop_node.c
> DEP /tmp/qemu-test/src/dtc/tests/nop_property.c
> DEP /tmp/qemu-test/src/dtc/tests/setprop_inplace.c
> DEP /tmp/qemu-test/src/dtc/tests/stringlist.c
> DEP /tmp/qemu-test/src/dtc/tests/addr_size_cells.c
> DEP /tmp/qemu-test/src/dtc/tests/notfound.c
> DEP /tmp/qemu-test/src/dtc/tests/sized_cells.c
> DEP /tmp/qemu-test/src/dtc/tests/char_literal.c
> DEP /tmp/qemu-test/src/dtc/tests/get_alias.c
> DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_compatible.c
> DEP /tmp/qemu-test/src/dtc/tests/node_check_compatible.c
> DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_phandle.c
> DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_prop_value.c
> DEP /tmp/qemu-test/src/dtc/tests/parent_offset.c
> DEP /tmp/qemu-test/src/dtc/tests/supernode_atdepth_offset.c
> DEP /tmp/qemu-test/src/dtc/tests/get_path.c
> DEP /tmp/qemu-test/src/dtc/tests/get_phandle.c
> DEP /tmp/qemu-test/src/dtc/tests/getprop.c
> DEP /tmp/qemu-test/src/dtc/tests/get_name.c
> DEP /tmp/qemu-test/src/dtc/tests/path_offset.c
> DEP /tmp/qemu-test/src/dtc/tests/subnode_offset.c
> DEP /tmp/qemu-test/src/dtc/tests/find_property.c
> DEP /tmp/qemu-test/src/dtc/tests/root_node.c
> DEP /tmp/qemu-test/src/dtc/tests/get_mem_rsv.c
> DEP /tmp/qemu-test/src/dtc/libfdt/fdt_overlay.c
> DEP /tmp/qemu-test/src/dtc/libfdt/fdt_addresses.c
> DEP /tmp/qemu-test/src/dtc/libfdt/fdt_empty_tree.c
> DEP /tmp/qemu-test/src/dtc/libfdt/fdt_strerror.c
> DEP /tmp/qemu-test/src/dtc/libfdt/fdt_rw.c
> DEP /tmp/qemu-test/src/dtc/libfdt/fdt_wip.c
> DEP /tmp/qemu-test/src/dtc/libfdt/fdt_sw.c
> DEP /tmp/qemu-test/src/dtc/libfdt/fdt_ro.c
> DEP /tmp/qemu-test/src/dtc/libfdt/fdt.c
> DEP /tmp/qemu-test/src/dtc/util.c
> DEP /tmp/qemu-test/src/dtc/fdtoverlay.c
> DEP /tmp/qemu-test/src/dtc/fdtput.c
> DEP /tmp/qemu-test/src/dtc/fdtget.c
> DEP /tmp/qemu-test/src/dtc/fdtdump.c
> LEX convert-dtsv0-lexer.lex.c
> DEP /tmp/qemu-test/src/dtc/srcpos.c
> BISON dtc-parser.tab.c
> LEX dtc-lexer.lex.c
> DEP /tmp/qemu-test/src/dtc/treesource.c
> DEP /tmp/qemu-test/src/dtc/livetree.c
> DEP /tmp/qemu-test/src/dtc/fstree.c
> DEP /tmp/qemu-test/src/dtc/flattree.c
> DEP /tmp/qemu-test/src/dtc/dtc.c
> DEP /tmp/qemu-test/src/dtc/data.c
> DEP /tmp/qemu-test/src/dtc/checks.c
> DEP convert-dtsv0-lexer.lex.c
> DEP dtc-parser.tab.c
> DEP dtc-lexer.lex.c
> CHK version_gen.h
> UPD version_gen.h
> DEP /tmp/qemu-test/src/dtc/util.c
> CC libfdt/fdt.o
> CC libfdt/fdt_ro.o
> CC libfdt/fdt_wip.o
> CC libfdt/fdt_sw.o
> CC libfdt/fdt_rw.o
> CC libfdt/fdt_strerror.o
> CC libfdt/fdt_empty_tree.o
> CC libfdt/fdt_addresses.o
> CC libfdt/fdt_overlay.o
> AR libfdt/libfdt.a
> x86_64-w64-mingw32-ar: creating libfdt/libfdt.a
> a - libfdt/fdt.o
> a - libfdt/fdt_ro.o
> a - libfdt/fdt_wip.o
> a - libfdt/fdt_sw.o
> a - libfdt/fdt_rw.o
> a - libfdt/fdt_strerror.o
> a - libfdt/fdt_empty_tree.o
> a - libfdt/fdt_addresses.o
> a - libfdt/fdt_overlay.o
> RC version.o
> GEN qga/qapi-generated/qga-qapi-types.h
> GEN qga/qapi-generated/qga-qmp-commands.h
> GEN qga/qapi-generated/qga-qapi-types.c
> GEN qga/qapi-generated/qga-qapi-visit.h
> GEN qga/qapi-generated/qga-qmp-marshal.c
> CC qmp-introspect.o
> CC qapi-types.o
> GEN qga/qapi-generated/qga-qapi-visit.c
> CC qapi-visit.o
> CC qapi-event.o
> CC qapi/qapi-visit-core.o
> CC qapi/qapi-dealloc-visitor.o
> CC qapi/qobject-input-visitor.o
> CC qapi/qobject-output-visitor.o
> CC qapi/qmp-registry.o
> CC qapi/qmp-dispatch.o
> CC qapi/string-input-visitor.o
> CC qapi/string-output-visitor.o
> CC qapi/opts-visitor.o
> CC qapi/qapi-clone-visitor.o
> CC qapi/qmp-event.o
> CC qapi/qapi-util.o
> CC qobject/qnull.o
> CC qobject/qnum.o
> CC qobject/qstring.o
> CC qobject/qdict.o
> CC qobject/qlist.o
> CC qobject/qbool.o
> CC qobject/qlit.o
> CC qobject/qjson.o
> CC qobject/qobject.o
> CC qobject/json-lexer.o
> CC qobject/json-streamer.o
> CC qobject/json-parser.o
> CC trace/simple.o
> CC trace/control.o
> CC trace/qmp.o
> CC util/osdep.o
> CC util/cutils.o
> CC util/unicode.o
> CC util/qemu-timer-common.o
> CC util/bufferiszero.o
> CC util/lockcnt.o
> CC util/aiocb.o
> CC util/async.o
> CC util/thread-pool.o
> CC util/qemu-timer.o
> CC util/main-loop.o
> CC util/iohandler.o
> CC util/aio-win32.o
> CC util/event_notifier-win32.o
> CC util/oslib-win32.o
> CC util/qemu-thread-win32.o
> CC util/envlist.o
> CC util/path.o
> CC util/module.o
> CC util/host-utils.o
> CC util/bitmap.o
> CC util/bitops.o
> CC util/hbitmap.o
> CC util/fifo8.o
> CC util/acl.o
> CC util/cacheinfo.o
> CC util/error.o
> CC util/qemu-error.o
> CC util/id.o
> CC util/iov.o
> CC util/qemu-sockets.o
> CC util/qemu-config.o
> CC util/uri.o
> CC util/notify.o
> CC util/qemu-option.o
> CC util/qemu-progress.o
> CC util/keyval.o
> CC util/hexdump.o
> CC util/crc32c.o
> CC util/uuid.o
> CC util/throttle.o
> CC util/getauxval.o
> CC util/readline.o
> CC util/rcu.o
> CC util/qemu-coroutine.o
> CC util/qemu-coroutine-lock.o
> CC util/qemu-coroutine-io.o
> CC util/qemu-coroutine-sleep.o
> CC util/coroutine-win32.o
> CC util/buffer.o
> CC util/timed-average.o
> CC util/base64.o
> CC util/log.o
> CC util/pagesize.o
> CC util/qht.o
> CC util/qdist.o
> CC util/range.o
> CC util/stats64.o
> CC util/systemd.o
> CC trace-root.o
> CC util/trace.o
> CC crypto/trace.o
> CC io/trace.o
> CC migration/trace.o
> CC block/trace.o
> CC chardev/trace.o
> CC hw/block/trace.o
> CC hw/block/dataplane/trace.o
> CC hw/char/trace.o
> CC hw/intc/trace.o
> CC hw/net/trace.o
> CC hw/virtio/trace.o
> CC hw/audio/trace.o
> CC hw/misc/trace.o
> CC hw/usb/trace.o
> CC hw/scsi/trace.o
> CC hw/nvram/trace.o
> CC hw/display/trace.o
> CC hw/input/trace.o
> CC hw/timer/trace.o
> CC hw/dma/trace.o
> CC hw/sparc/trace.o
> CC hw/sparc64/trace.o
> CC hw/sd/trace.o
> CC hw/isa/trace.o
> CC hw/mem/trace.o
> CC hw/i386/trace.o
> CC hw/i386/xen/trace.o
> CC hw/9pfs/trace.o
> CC hw/ppc/trace.o
> CC hw/pci/trace.o
> CC hw/pci-host/trace.o
> CC hw/s390x/trace.o
> CC hw/vfio/trace.o
> CC hw/acpi/trace.o
> CC hw/arm/trace.o
> CC hw/alpha/trace.o
> CC hw/hppa/trace.o
> CC hw/xen/trace.o
> CC hw/ide/trace.o
> CC ui/trace.o
> CC audio/trace.o
> CC net/trace.o
> CC target/arm/trace.o
> CC target/i386/trace.o
> CC target/mips/trace.o
> CC target/sparc/trace.o
> CC target/s390x/trace.o
> CC target/ppc/trace.o
> CC qom/trace.o
> CC linux-user/trace.o
> CC qapi/trace.o
> CC accel/tcg/trace.o
> CC accel/kvm/trace.o
> CC nbd/trace.o
> CC scsi/trace.o
> CC crypto/pbkdf-stub.o
> CC stubs/arch-query-cpu-def.o
> CC stubs/arch-query-cpu-model-expansion.o
> CC stubs/arch-query-cpu-model-comparison.o
> CC stubs/arch-query-cpu-model-baseline.o
> CC stubs/bdrv-next-monitor-owned.o
> CC stubs/blockdev-close-all-bdrv-states.o
> CC stubs/blk-commit-all.o
> CC stubs/clock-warp.o
> CC stubs/cpu-get-clock.o
> CC stubs/cpu-get-icount.o
> CC stubs/dump.o
> CC stubs/error-printf.o
> CC stubs/fdset.o
> CC stubs/gdbstub.o
> CC stubs/get-vm-name.o
> CC stubs/iothread.o
> CC stubs/iothread-lock.o
> CC stubs/is-daemonized.o
> CC stubs/machine-init-done.o
> CC stubs/migr-blocker.o
> CC stubs/change-state-handler.o
> CC stubs/monitor.o
> CC stubs/notify-event.o
> CC stubs/qtest.o
> CC stubs/replay.o
> CC stubs/runstate-check.o
> CC stubs/set-fd-handler.o
> CC stubs/slirp.o
> CC stubs/sysbus.o
> CC stubs/tpm.o
> CC stubs/trace-control.o
> CC stubs/uuid.o
> CC stubs/vm-stop.o
> CC stubs/vmstate.o
> CC stubs/fd-register.o
> CC stubs/qmp_pc_dimm.o
> CC stubs/target-monitor-defs.o
> CC stubs/target-get-monitor-def.o
> CC stubs/pc_madt_cpu_entry.o
> CC stubs/vmgenid.o
> CC stubs/xen-common.o
> CC stubs/xen-hvm.o
> CC stubs/pci-host-piix.o
> GEN qemu-img-cmds.h
> CC block.o
> CC blockjob.o
> CC qemu-io-cmds.o
> CC replication.o
> CC block/raw-format.o
> CC block/qcow.o
> CC block/vdi.o
> CC block/vmdk.o
> CC block/cloop.o
> CC block/bochs.o
> CC block/vpc.o
> CC block/vvfat.o
> CC block/qcow2.o
> CC block/dmg.o
> CC block/qcow2-refcount.o
> CC block/qcow2-cluster.o
> CC block/qcow2-snapshot.o
> CC block/qcow2-cache.o
> CC block/qcow2-bitmap.o
> CC block/qed.o
> CC block/qed-l2-cache.o
> CC block/qed-table.o
> CC block/qed-cluster.o
> CC block/qed-check.o
> CC block/vhdx.o
> CC block/vhdx-endian.o
> CC block/vhdx-log.o
> CC block/quorum.o
> CC block/parallels.o
> CC block/blkdebug.o
> CC block/blkverify.o
> CC block/blkreplay.o
> CC block/block-backend.o
> CC block/snapshot.o
> CC block/qapi.o
> CC block/file-win32.o
> CC block/win32-aio.o
> CC block/null.o
> CC block/mirror.o
> CC block/commit.o
> CC block/io.o
> CC block/throttle-groups.o
> CC block/nbd.o
> CC block/nbd-client.o
> CC block/sheepdog.o
> CC block/accounting.o
> CC block/dirty-bitmap.o
> CC block/write-threshold.o
> CC block/backup.o
> CC block/replication.o
> CC block/throttle.o
> CC block/crypto.o
> CC nbd/server.o
> CC nbd/client.o
> CC nbd/common.o
> CC scsi/utils.o
> CC block/curl.o
> CC block/ssh.o
> CC block/dmg-bz2.o
> CC crypto/init.o
> CC crypto/hash.o
> CC crypto/hash-nettle.o
> CC crypto/hmac.o
> CC crypto/hmac-nettle.o
> CC crypto/aes.o
> CC crypto/desrfb.o
> CC crypto/cipher.o
> CC crypto/tlscreds.o
> CC crypto/tlscredsanon.o
> CC crypto/pbkdf.o
> CC crypto/secret.o
> CC crypto/tlscredsx509.o
> CC crypto/tlssession.o
> CC crypto/pbkdf-nettle.o
> CC crypto/random-gnutls.o
> CC crypto/ivgen.o
> CC crypto/ivgen-essiv.o
> CC crypto/ivgen-plain.o
> CC crypto/ivgen-plain64.o
> CC crypto/afsplit.o
> CC crypto/xts.o
> CC crypto/block.o
> CC crypto/block-qcow.o
> CC crypto/block-luks.o
> CC io/channel.o
> CC io/channel-buffer.o
> CC io/channel-command.o
> CC io/channel-file.o
> CC io/channel-socket.o
> CC io/channel-tls.o
> CC io/channel-watch.o
> CC io/channel-websock.o
> CC io/channel-util.o
> CC io/dns-resolver.o
> CC io/net-listener.o
> CC io/task.o
> CC qom/object.o
> CC qom/container.o
> CC qom/qom-qobject.o
> CC qom/object_interfaces.o
> CC qemu-io.o
> CC blockdev.o
> CC blockdev-nbd.o
> CC bootdevice.o
> CC iothread.o
> CC qdev-monitor.o
> CC device-hotplug.o
> CC os-win32.o
> CC bt-host.o
> CC bt-vhci.o
> CC dma-helpers.o
> CC vl.o
> CC tpm.o
> CC device_tree.o
> CC qmp-marshal.o
> CC qmp.o
> CC hmp.o
> CC cpus-common.o
> CC audio/audio.o
> CC audio/noaudio.o
> CC audio/wavaudio.o
> CC audio/mixeng.o
> CC audio/sdlaudio.o
> CC audio/dsoundaudio.o
> CC audio/audio_win_int.o
> CC audio/wavcapture.o
> CC backends/rng.o
> CC backends/rng-egd.o
> CC backends/tpm.o
> CC backends/hostmem.o
> CC backends/hostmem-ram.o
> CC backends/cryptodev.o
> CC backends/cryptodev-builtin.o
> CC block/stream.o
> CC chardev/msmouse.o
> CC chardev/wctablet.o
> CC chardev/testdev.o
> CC disas/arm.o
> CXX disas/arm-a64.o
> CC disas/i386.o
> CXX disas/libvixl/vixl/utils.o
> CXX disas/libvixl/vixl/compiler-intrinsics.o
> CXX disas/libvixl/vixl/a64/instructions-a64.o
> CXX disas/libvixl/vixl/a64/decoder-a64.o
> CXX disas/libvixl/vixl/a64/disasm-a64.o
> CC hw/acpi/piix4.o
> CC hw/acpi/core.o
> CC hw/acpi/pcihp.o
> CC hw/acpi/ich9.o
> CC hw/acpi/tco.o
> CC hw/acpi/cpu_hotplug.o
> CC hw/acpi/memory_hotplug.o
> CC hw/acpi/cpu.o
> CC hw/acpi/nvdimm.o
> CC hw/acpi/vmgenid.o
> CC hw/acpi/acpi_interface.o
> CC hw/acpi/bios-linker-loader.o
> CC hw/acpi/aml-build.o
> CC hw/acpi/ipmi.o
> CC hw/acpi/acpi-stub.o
> CC hw/acpi/ipmi-stub.o
> CC hw/audio/sb16.o
> CC hw/audio/es1370.o
> CC hw/audio/ac97.o
> CC hw/audio/fmopl.o
> CC hw/audio/adlib.o
> CC hw/audio/gus.o
> CC hw/audio/gusemu_hal.o
> CC hw/audio/gusemu_mixer.o
> CC hw/audio/cs4231a.o
> CC hw/audio/intel-hda.o
> CC hw/audio/hda-codec.o
> CC hw/audio/pcspk.o
> CC hw/audio/wm8750.o
> CC hw/audio/pl041.o
> CC hw/audio/lm4549.o
> CC hw/audio/marvell_88w8618.o
> CC hw/audio/soundhw.o
> CC hw/block/block.o
> CC hw/block/cdrom.o
> CC hw/block/hd-geometry.o
> CC hw/block/fdc.o
> CC hw/block/m25p80.o
> CC hw/block/nand.o
> CC hw/block/pflash_cfi01.o
> CC hw/block/pflash_cfi02.o
> CC hw/block/ecc.o
> CC hw/block/onenand.o
> CC hw/block/nvme.o
> CC hw/bt/core.o
> CC hw/bt/l2cap.o
> CC hw/bt/sdp.o
> CC hw/bt/hci.o
> CC hw/bt/hid.o
> CC hw/bt/hci-csr.o
> CC hw/char/ipoctal232.o
> CC hw/char/parallel.o
> CC hw/char/pl011.o
> CC hw/char/serial.o
> CC hw/char/serial-isa.o
> CC hw/char/serial-pci.o
> CC hw/char/virtio-console.o
> CC hw/char/cadence_uart.o
> CC hw/char/cmsdk-apb-uart.o
> CC hw/char/debugcon.o
> CC hw/char/imx_serial.o
> CC hw/core/qdev.o
> CC hw/core/qdev-properties.o
> CC hw/core/bus.o
> CC hw/core/reset.o
> CC hw/core/qdev-fw.o
> CC hw/core/fw-path-provider.o
> CC hw/core/irq.o
> CC hw/core/hotplug.o
> CC hw/core/nmi.o
> CC hw/core/stream.o
> CC hw/core/ptimer.o
> CC hw/core/sysbus.o
> CC hw/core/machine.o
> CC hw/core/loader.o
> CC hw/core/qdev-properties-system.o
> CC hw/core/register.o
> CC hw/core/or-irq.o
> CC hw/core/platform-bus.o
> CC hw/cpu/core.o
> CC hw/display/ads7846.o
> CC hw/display/cirrus_vga.o
> CC hw/display/pl110.o
> CC hw/display/ssd0303.o
> CC hw/display/ssd0323.o
> CC hw/display/vga-isa.o
> CC hw/display/vga-pci.o
> CC hw/display/vmware_vga.o
> CC hw/display/blizzard.o
> CC hw/display/exynos4210_fimd.o
> CC hw/display/framebuffer.o
> CC hw/display/tc6393xb.o
> CC hw/dma/pl080.o
> CC hw/dma/pl330.o
> CC hw/dma/i8257.o
> CC hw/dma/xilinx_axidma.o
> CC hw/dma/xlnx-zynq-devcfg.o
> CC hw/gpio/max7310.o
> CC hw/gpio/pl061.o
> CC hw/gpio/zaurus.o
> CC hw/gpio/gpio_key.o
> CC hw/i2c/core.o
> CC hw/i2c/smbus.o
> CC hw/i2c/smbus_eeprom.o
> CC hw/i2c/i2c-ddc.o
> CC hw/i2c/versatile_i2c.o
> CC hw/i2c/smbus_ich9.o
> CC hw/i2c/pm_smbus.o
> CC hw/i2c/bitbang_i2c.o
> CC hw/i2c/exynos4210_i2c.o
> CC hw/i2c/imx_i2c.o
> CC hw/i2c/aspeed_i2c.o
> CC hw/ide/core.o
> CC hw/ide/atapi.o
> CC hw/ide/qdev.o
> CC hw/ide/pci.o
> CC hw/ide/isa.o
> CC hw/ide/piix.o
> CC hw/ide/microdrive.o
> CC hw/ide/ahci.o
> CC hw/ide/ich.o
> CC hw/ide/ahci-allwinner.o
> CC hw/input/hid.o
> CC hw/input/lm832x.o
> CC hw/input/pckbd.o
> CC hw/input/pl050.o
> CC hw/input/ps2.o
> CC hw/input/stellaris_input.o
> CC hw/input/tsc2005.o
> CC hw/input/virtio-input.o
> CC hw/input/virtio-input-hid.o
> CC hw/intc/i8259_common.o
> CC hw/intc/i8259.o
> CC hw/intc/pl190.o
> CC hw/intc/xlnx-pmu-iomod-intc.o
> CC hw/intc/xlnx-zynqmp-ipi.o
> CC hw/intc/imx_avic.o
> CC hw/intc/realview_gic.o
> CC hw/intc/ioapic_common.o
> CC hw/intc/arm_gic_common.o
> CC hw/intc/arm_gic.o
> CC hw/intc/arm_gicv2m.o
> CC hw/intc/arm_gicv3_common.o
> CC hw/intc/arm_gicv3.o
> CC hw/intc/arm_gicv3_dist.o
> CC hw/intc/arm_gicv3_redist.o
> CC hw/intc/arm_gicv3_its_common.o
> CC hw/intc/intc.o
> CC hw/ipack/ipack.o
> CC hw/ipack/tpci200.o
> CC hw/ipmi/ipmi.o
> CC hw/ipmi/ipmi_bmc_sim.o
> CC hw/ipmi/ipmi_bmc_extern.o
> CC hw/ipmi/isa_ipmi_kcs.o
> CC hw/isa/isa-bus.o
> CC hw/ipmi/isa_ipmi_bt.o
> CC hw/isa/apm.o
> CC hw/mem/nvdimm.o
> CC hw/mem/pc-dimm.o
> CC hw/misc/applesmc.o
> CC hw/misc/max111x.o
> CC hw/misc/tmp105.o
> CC hw/misc/tmp421.o
> CC hw/misc/sga.o
> CC hw/misc/debugexit.o
> CC hw/misc/pc-testdev.o
> CC hw/misc/pci-testdev.o
> CC hw/misc/edu.o
> CC hw/misc/unimp.o
> CC hw/misc/vmcoreinfo.o
> CC hw/misc/arm_l2x0.o
> CC hw/misc/arm_integrator_debug.o
> CC hw/misc/a9scu.o
> CC hw/misc/arm11scu.o
> CC hw/net/ne2000.o
> CC hw/net/eepro100.o
> CC hw/net/pcnet-pci.o
> CC hw/net/pcnet.o
> CC hw/net/e1000.o
> CC hw/net/e1000x_common.o
> CC hw/net/net_tx_pkt.o
> CC hw/net/net_rx_pkt.o
> CC hw/net/e1000e.o
> CC hw/net/e1000e_core.o
> CC hw/net/rtl8139.o
> CC hw/net/vmxnet3.o
> CC hw/net/smc91c111.o
> CC hw/net/lan9118.o
> CC hw/net/ne2000-isa.o
> CC hw/net/xgmac.o
> CC hw/net/xilinx_axienet.o
> CC hw/net/allwinner_emac.o
> CC hw/net/imx_fec.o
> CC hw/net/cadence_gem.o
> CC hw/net/stellaris_enet.o
> CC hw/net/ftgmac100.o
> CC hw/net/rocker/rocker.o
> CC hw/net/rocker/rocker_fp.o
> CC hw/net/rocker/rocker_desc.o
> CC hw/net/rocker/rocker_world.o
> CC hw/net/rocker/rocker_of_dpa.o
> CC hw/nvram/eeprom93xx.o
> CC hw/nvram/eeprom_at24c.o
> CC hw/nvram/fw_cfg.o
> CC hw/nvram/chrp_nvram.o
> CC hw/pci-bridge/pci_bridge_dev.o
> CC hw/pci-bridge/pcie_root_port.o
> CC hw/pci-bridge/gen_pcie_root_port.o
> CC hw/pci-bridge/pcie_pci_bridge.o
> CC hw/pci-bridge/pci_expander_bridge.o
> CC hw/pci-bridge/xio3130_upstream.o
> CC hw/pci-bridge/xio3130_downstream.o
> CC hw/pci-bridge/ioh3420.o
> CC hw/pci-bridge/i82801b11.o
> CC hw/pci-host/pam.o
> CC hw/pci-host/versatile.o
> CC hw/pci-host/piix.o
> CC hw/pci-host/q35.o
> CC hw/pci-host/gpex.o
> CC hw/pci/pci.o
> CC hw/pci/pci_bridge.o
> CC hw/pci/msix.o
> CC hw/pci/msi.o
> CC hw/pci/shpc.o
> CC hw/pci/slotid_cap.o
> CC hw/pci/pci_host.o
> CC hw/pci/pcie_host.o
> CC hw/pci/pcie.o
> CC hw/pci/pcie_aer.o
> CC hw/pci/pcie_port.o
> CC hw/pci/pci-stub.o
> CC hw/pcmcia/pcmcia.o
> CC hw/scsi/scsi-disk.o
> CC hw/scsi/scsi-generic.o
> CC hw/scsi/scsi-bus.o
> CC hw/scsi/lsi53c895a.o
> CC hw/scsi/mptsas.o
> CC hw/scsi/mptconfig.o
> CC hw/scsi/mptendian.o
> CC hw/scsi/megasas.o
> CC hw/scsi/vmw_pvscsi.o
> CC hw/scsi/esp.o
> CC hw/scsi/esp-pci.o
> CC hw/sd/pl181.o
> CC hw/sd/ssi-sd.o
> CC hw/sd/sd.o
> CC hw/sd/core.o
> CC hw/sd/sdhci.o
> CC hw/smbios/smbios.o
> CC hw/smbios/smbios_type_38.o
> CC hw/smbios/smbios-stub.o
> CC hw/smbios/smbios_type_38-stub.o
> CC hw/ssi/pl022.o
> CC hw/ssi/ssi.o
> CC hw/ssi/xilinx_spips.o
> CC hw/ssi/aspeed_smc.o
> CC hw/ssi/stm32f2xx_spi.o
> CC hw/ssi/mss-spi.o
> CC hw/timer/arm_timer.o
> CC hw/timer/arm_mptimer.o
> CC hw/timer/armv7m_systick.o
> CC hw/timer/a9gtimer.o
> CC hw/timer/cadence_ttc.o
> CC hw/timer/ds1338.o
> CC hw/timer/hpet.o
> CC hw/timer/i8254_common.o
> CC hw/timer/i8254.o
> CC hw/timer/pl031.o
> CC hw/timer/twl92230.o
> CC hw/timer/imx_epit.o
> CC hw/timer/imx_gpt.o
> CC hw/timer/stm32f2xx_timer.o
> CC hw/timer/aspeed_timer.o
> CC hw/timer/cmsdk-apb-timer.o
> CC hw/timer/mss-timer.o
> CC hw/tpm/tpm_util.o
> CC hw/tpm/tpm_tis.o
> CC hw/tpm/tpm_crb.o
> CC hw/usb/core.o
> CC hw/usb/combined-packet.o
> CC hw/usb/bus.o
> CC hw/usb/libhw.o
> CC hw/usb/desc.o
> CC hw/usb/desc-msos.o
> CC hw/usb/hcd-uhci.o
> CC hw/usb/hcd-ohci.o
> CC hw/usb/hcd-ehci.o
> CC hw/usb/hcd-ehci-pci.o
> CC hw/usb/hcd-ehci-sysbus.o
> CC hw/usb/hcd-xhci.o
> CC hw/usb/hcd-xhci-nec.o
> CC hw/usb/hcd-musb.o
> CC hw/usb/dev-hub.o
> CC hw/usb/dev-hid.o
> CC hw/usb/dev-wacom.o
> CC hw/usb/dev-storage.o
> CC hw/usb/dev-uas.o
> CC hw/usb/dev-audio.o
> CC hw/usb/dev-serial.o
> CC hw/usb/dev-network.o
> CC hw/usb/dev-bluetooth.o
> CC hw/usb/dev-smartcard-reader.o
> CC hw/usb/host-stub.o
> CC hw/virtio/virtio-rng.o
> CC hw/virtio/virtio-pci.o
> CC hw/virtio/virtio-bus.o
> CC hw/virtio/virtio-mmio.o
> CC hw/virtio/vhost-stub.o
> CC hw/watchdog/watchdog.o
> CC hw/watchdog/wdt_i6300esb.o
> CC hw/watchdog/wdt_ib700.o
> CC hw/watchdog/wdt_aspeed.o
> CC migration/migration.o
> CC migration/socket.o
> CC migration/fd.o
> CC migration/exec.o
> CC migration/tls.o
> CC migration/channel.o
> CC migration/savevm.o
> CC migration/colo-comm.o
> CC migration/colo.o
> CC migration/colo-failover.o
> CC migration/vmstate.o
> CC migration/page_cache.o
> CC migration/vmstate-types.o
> CC migration/qemu-file.o
> CC migration/global_state.o
> CC migration/qemu-file-channel.o
> CC migration/xbzrle.o
> CC migration/postcopy-ram.o
> CC migration/qjson.o
> CC migration/block.o
> CC net/net.o
> CC net/queue.o
> CC net/checksum.o
> CC net/util.o
> CC net/hub.o
> CC net/socket.o
> CC net/dump.o
> CC net/eth.o
> CC net/slirp.o
> CC net/filter.o
> CC net/filter-buffer.o
> CC net/filter-mirror.o
> CC net/colo-compare.o
> CC net/colo.o
> CC net/filter-rewriter.o
> CC net/filter-replay.o
> CC net/tap-win32.o
> CC qom/cpu.o
> CC replay/replay.o
> CC replay/replay-internal.o
> CC replay/replay-events.o
> CC replay/replay-time.o
> CC replay/replay-input.o
> CC replay/replay-snapshot.o
> CC replay/replay-char.o
> CC replay/replay-audio.o
> CC replay/replay-net.o
> CC slirp/cksum.o
> CC slirp/if.o
> CC slirp/ip_icmp.o
> CC slirp/ip6_icmp.o
> CC slirp/ip6_input.o
> CC slirp/ip_input.o
> CC slirp/ip6_output.o
> CC slirp/ip_output.o
> CC slirp/dnssearch.o
> CC slirp/dhcpv6.o
> CC slirp/slirp.o
> CC slirp/mbuf.o
> CC slirp/misc.o
> CC slirp/sbuf.o
> CC slirp/socket.o
> CC slirp/tcp_input.o
> CC slirp/tcp_output.o
> CC slirp/tcp_subr.o
> CC slirp/tcp_timer.o
> CC slirp/udp.o
> CC slirp/udp6.o
> CC slirp/bootp.o
> CC slirp/tftp.o
> CC slirp/arp_table.o
> CC slirp/ndp_table.o
> CC slirp/ncsi.o
> CC ui/keymaps.o
> CC ui/console.o
> CC ui/cursor.o
> CC ui/qemu-pixman.o
> CC ui/input.o
> CC ui/input-keymap.o
> CC ui/input-legacy.o
> CC ui/sdl.o
> CC ui/sdl_zoom.o
> CC ui/vnc.o
> CC ui/vnc-enc-zlib.o
> CC ui/vnc-enc-hextile.o
> CC ui/vnc-enc-tight.o
> CC ui/vnc-palette.o
> CC ui/vnc-enc-zrle.o
> CC ui/vnc-auth-vencrypt.o
> CC ui/vnc-ws.o
> CC ui/vnc-jobs.o
> CC ui/gtk.o
> CC chardev/char.o
> CC chardev/char-console.o
> CC chardev/char-fe.o
> CC chardev/char-file.o
> CC chardev/char-io.o
> CC chardev/char-mux.o
> CC chardev/char-null.o
> CC chardev/char-pipe.o
> CC chardev/char-ringbuf.o
> CC chardev/char-serial.o
> CC chardev/char-socket.o
> CC chardev/char-stdio.o
> CC chardev/char-udp.o
> CC chardev/char-win.o
> CC chardev/char-win-stdio.o
> CC qga/commands.o
> CC qga/guest-agent-command-state.o
> CC qga/main.o
> CC qga/commands-win32.o
> CC qga/channel-win32.o
> AS optionrom/multiboot.o
> CC qga/service-win32.o
> CC qga/vss-win32.o
> AS optionrom/linuxboot.o
> CC qga/qapi-generated/qga-qapi-types.o
> CC optionrom/linuxboot_dma.o
> CC qga/qapi-generated/qga-qapi-visit.o
> AS optionrom/kvmvapic.o
> BUILD optionrom/multiboot.img
> BUILD optionrom/linuxboot.img
> BUILD optionrom/kvmvapic.img
> CC qga/qapi-generated/qga-qmp-marshal.o
> BUILD optionrom/multiboot.raw
> BUILD optionrom/linuxboot.raw
> AR libqemuutil.a
> CC qemu-img.o
> BUILD optionrom/linuxboot_dma.img
> BUILD optionrom/kvmvapic.raw
> SIGN optionrom/multiboot.bin
> SIGN optionrom/linuxboot.bin
> BUILD optionrom/linuxboot_dma.raw
> SIGN optionrom/kvmvapic.bin
> SIGN optionrom/linuxboot_dma.bin
> LINK qemu-io.exe
> LINK qemu-ga.exe
> LINK qemu-img.exe
> GEN x86_64-softmmu/hmp-commands.h
> GEN x86_64-softmmu/hmp-commands-info.h
> GEN x86_64-softmmu/config-target.h
> GEN aarch64-softmmu/hmp-commands-info.h
> GEN aarch64-softmmu/hmp-commands.h
> GEN aarch64-softmmu/config-target.h
> CC x86_64-softmmu/tcg/tcg.o
> CC x86_64-softmmu/exec.o
> CC x86_64-softmmu/tcg/optimize.o
> CC x86_64-softmmu/tcg/tcg-op.o
> CC x86_64-softmmu/fpu/softfloat.o
> CC x86_64-softmmu/disas.o
> CC x86_64-softmmu/tcg/tcg-common.o
> CC aarch64-softmmu/exec.o
> GEN x86_64-softmmu/gdbstub-xml.c
> CC x86_64-softmmu/arch_init.o
> CC x86_64-softmmu/cpus.o
> CC x86_64-softmmu/monitor.o
> CC x86_64-softmmu/gdbstub.o
> CC x86_64-softmmu/balloon.o
> CC aarch64-softmmu/tcg/tcg.o
> CC x86_64-softmmu/ioport.o
> CC aarch64-softmmu/tcg/tcg-op.o
> CC aarch64-softmmu/tcg/optimize.o
> CC x86_64-softmmu/numa.o
> CC x86_64-softmmu/qtest.o
> CC aarch64-softmmu/tcg/tcg-common.o
> CC aarch64-softmmu/fpu/softfloat.o
> CC aarch64-softmmu/disas.o
> CC x86_64-softmmu/memory.o
> CC x86_64-softmmu/memory_mapping.o
> GEN aarch64-softmmu/gdbstub-xml.c
> CC aarch64-softmmu/arch_init.o
> CC x86_64-softmmu/dump.o
> CC aarch64-softmmu/cpus.o
> CC x86_64-softmmu/migration/ram.o
> CC x86_64-softmmu/accel/accel.o
> CC x86_64-softmmu/accel/stubs/hvf-stub.o
> CC aarch64-softmmu/monitor.o
> CC aarch64-softmmu/gdbstub.o
> CC x86_64-softmmu/accel/stubs/kvm-stub.o
> CC aarch64-softmmu/balloon.o
> CC aarch64-softmmu/ioport.o
> CC x86_64-softmmu/accel/tcg/tcg-all.o
> CC aarch64-softmmu/numa.o
> CC aarch64-softmmu/qtest.o
> CC x86_64-softmmu/accel/tcg/cputlb.o
> CC aarch64-softmmu/memory.o
> CC aarch64-softmmu/memory_mapping.o
> CC x86_64-softmmu/accel/tcg/tcg-runtime.o
> CC aarch64-softmmu/dump.o
> CC aarch64-softmmu/migration/ram.o
> CC aarch64-softmmu/accel/accel.o
> CC aarch64-softmmu/accel/stubs/hax-stub.o
> CC x86_64-softmmu/accel/tcg/cpu-exec.o
> CC x86_64-softmmu/accel/tcg/cpu-exec-common.o
> CC aarch64-softmmu/accel/stubs/hvf-stub.o
> CC aarch64-softmmu/accel/stubs/kvm-stub.o
> CC aarch64-softmmu/accel/tcg/tcg-all.o
> CC x86_64-softmmu/accel/tcg/translate-all.o
> CC aarch64-softmmu/accel/tcg/cputlb.o
> CC aarch64-softmmu/accel/tcg/tcg-runtime.o
> CC aarch64-softmmu/accel/tcg/cpu-exec.o
> CC aarch64-softmmu/accel/tcg/cpu-exec-common.o
> CC x86_64-softmmu/accel/tcg/translator.o
> CC x86_64-softmmu/hw/block/virtio-blk.o
> CC x86_64-softmmu/hw/block/dataplane/virtio-blk.o
> CC x86_64-softmmu/hw/char/virtio-serial-bus.o
> CC x86_64-softmmu/hw/core/generic-loader.o
> CC aarch64-softmmu/accel/tcg/translate-all.o
> CC aarch64-softmmu/accel/tcg/translator.o
> CC aarch64-softmmu/hw/adc/stm32f2xx_adc.o
> CC x86_64-softmmu/hw/core/null-machine.o
> CC x86_64-softmmu/hw/display/vga.o
> CC x86_64-softmmu/hw/display/virtio-gpu.o
> CC aarch64-softmmu/hw/block/virtio-blk.o
> CC x86_64-softmmu/hw/display/virtio-gpu-3d.o
> CC x86_64-softmmu/hw/display/virtio-gpu-pci.o
> CC aarch64-softmmu/hw/block/dataplane/virtio-blk.o
> CC aarch64-softmmu/hw/char/exynos4210_uart.o
> CC x86_64-softmmu/hw/display/virtio-vga.o
> CC aarch64-softmmu/hw/char/omap_uart.o
> CC aarch64-softmmu/hw/char/digic-uart.o
> CC x86_64-softmmu/hw/intc/apic.o
> CC x86_64-softmmu/hw/intc/apic_common.o
> CC x86_64-softmmu/hw/intc/ioapic.o
> CC aarch64-softmmu/hw/char/stm32f2xx_usart.o
> CC x86_64-softmmu/hw/isa/lpc_ich9.o
> CC aarch64-softmmu/hw/char/bcm2835_aux.o
> CC x86_64-softmmu/hw/misc/pvpanic.o
> CC aarch64-softmmu/hw/char/virtio-serial-bus.o
> CC x86_64-softmmu/hw/misc/mmio_interface.o
> CC aarch64-softmmu/hw/core/generic-loader.o
> CC aarch64-softmmu/hw/core/null-machine.o
> CC aarch64-softmmu/hw/cpu/arm11mpcore.o
> CC x86_64-softmmu/hw/net/virtio-net.o
> CC aarch64-softmmu/hw/cpu/realview_mpcore.o
> CC aarch64-softmmu/hw/cpu/a9mpcore.o
> CC x86_64-softmmu/hw/net/vhost_net.o
> CC aarch64-softmmu/hw/cpu/a15mpcore.o
> CC x86_64-softmmu/hw/scsi/virtio-scsi.o
> CC aarch64-softmmu/hw/display/omap_dss.o
> CC aarch64-softmmu/hw/display/omap_lcdc.o
> CC x86_64-softmmu/hw/scsi/virtio-scsi-dataplane.o
> CC x86_64-softmmu/hw/timer/mc146818rtc.o
> CC aarch64-softmmu/hw/display/pxa2xx_lcd.o
> CC aarch64-softmmu/hw/display/bcm2835_fb.o
> CC x86_64-softmmu/hw/virtio/virtio.o
> CC x86_64-softmmu/hw/virtio/virtio-balloon.o
> CC aarch64-softmmu/hw/display/vga.o
> CC aarch64-softmmu/hw/display/virtio-gpu.o
> CC aarch64-softmmu/hw/display/virtio-gpu-3d.o
> CC x86_64-softmmu/hw/virtio/virtio-crypto.o
> CC x86_64-softmmu/hw/virtio/virtio-crypto-pci.o
> CC aarch64-softmmu/hw/display/virtio-gpu-pci.o
> CC x86_64-softmmu/hw/i386/multiboot.o
> CC aarch64-softmmu/hw/display/dpcd.o
> CC x86_64-softmmu/hw/i386/pc.o
> CC aarch64-softmmu/hw/display/xlnx_dp.o
> CC aarch64-softmmu/hw/dma/xlnx_dpdma.o
> CC aarch64-softmmu/hw/dma/omap_dma.o
> CC x86_64-softmmu/hw/i386/pc_piix.o
> CC x86_64-softmmu/hw/i386/pc_q35.o
> CC aarch64-softmmu/hw/dma/soc_dma.o
> CC x86_64-softmmu/hw/i386/pc_sysfw.o
> CC aarch64-softmmu/hw/dma/pxa2xx_dma.o
> CC aarch64-softmmu/hw/dma/bcm2835_dma.o
> CC x86_64-softmmu/hw/i386/x86-iommu.o
> CC x86_64-softmmu/hw/i386/intel_iommu.o
> CC aarch64-softmmu/hw/gpio/omap_gpio.o
> CC x86_64-softmmu/hw/i386/amd_iommu.o
> CC x86_64-softmmu/hw/i386/vmport.o
> CC x86_64-softmmu/hw/i386/vmmouse.o
> CC aarch64-softmmu/hw/gpio/imx_gpio.o
> CC aarch64-softmmu/hw/gpio/bcm2835_gpio.o
> CC x86_64-softmmu/hw/i386/kvmvapic.o
> CC x86_64-softmmu/hw/i386/acpi-build.o
> CC x86_64-softmmu/target/i386/helper.o
> CC aarch64-softmmu/hw/i2c/omap_i2c.o
> CC x86_64-softmmu/target/i386/cpu.o
> CC x86_64-softmmu/target/i386/gdbstub.o
> CC aarch64-softmmu/hw/input/pxa2xx_keypad.o
> CC aarch64-softmmu/hw/input/tsc210x.o
> CC x86_64-softmmu/target/i386/xsave_helper.o
> CC x86_64-softmmu/target/i386/translate.o
> CC aarch64-softmmu/hw/intc/armv7m_nvic.o
> CC aarch64-softmmu/hw/intc/exynos4210_gic.o
> CC x86_64-softmmu/target/i386/bpt_helper.o
> CC aarch64-softmmu/hw/intc/exynos4210_combiner.o
> CC x86_64-softmmu/target/i386/cc_helper.o
> CC aarch64-softmmu/hw/intc/omap_intc.o
> CC aarch64-softmmu/hw/intc/bcm2835_ic.o
> CC x86_64-softmmu/target/i386/excp_helper.o
> CC x86_64-softmmu/target/i386/fpu_helper.o
> CC aarch64-softmmu/hw/intc/bcm2836_control.o
> CC aarch64-softmmu/hw/intc/allwinner-a10-pic.o
> CC x86_64-softmmu/target/i386/int_helper.o
> CC x86_64-softmmu/target/i386/mem_helper.o
> CC aarch64-softmmu/hw/intc/aspeed_vic.o
> CC aarch64-softmmu/hw/intc/arm_gicv3_cpuif.o
> CC aarch64-softmmu/hw/misc/arm_sysctl.o
> CC x86_64-softmmu/target/i386/misc_helper.o
> CC aarch64-softmmu/hw/misc/cbus.o
> CC aarch64-softmmu/hw/misc/exynos4210_pmu.o
> CC aarch64-softmmu/hw/misc/exynos4210_clk.o
> CC aarch64-softmmu/hw/misc/exynos4210_rng.o
> CC x86_64-softmmu/target/i386/mpx_helper.o
> CC aarch64-softmmu/hw/misc/imx_ccm.o
> CC aarch64-softmmu/hw/misc/imx31_ccm.o
> CC x86_64-softmmu/target/i386/seg_helper.o
> CC aarch64-softmmu/hw/misc/imx25_ccm.o
> CC x86_64-softmmu/target/i386/smm_helper.o
> CC x86_64-softmmu/target/i386/svm_helper.o
> CC x86_64-softmmu/target/i386/machine.o
> CC aarch64-softmmu/hw/misc/imx6_ccm.o
> CC x86_64-softmmu/target/i386/arch_memory_mapping.o
> CC x86_64-softmmu/target/i386/arch_dump.o
> CC aarch64-softmmu/hw/misc/imx6_src.o
> CC x86_64-softmmu/target/i386/monitor.o
> CC aarch64-softmmu/hw/misc/mst_fpga.o
> CC x86_64-softmmu/target/i386/kvm-stub.o
> CC x86_64-softmmu/target/i386/hax-all.o
> CC aarch64-softmmu/hw/misc/omap_clk.o
> CC aarch64-softmmu/hw/misc/omap_gpmc.o
> CC x86_64-softmmu/target/i386/hax-mem.o
> CC aarch64-softmmu/hw/misc/omap_l4.o
> CC x86_64-softmmu/target/i386/hax-windows.o
> CC aarch64-softmmu/hw/misc/omap_sdrc.o
> GEN trace/generated-helpers.c
> CC aarch64-softmmu/hw/misc/omap_tap.o
> CC aarch64-softmmu/hw/misc/bcm2835_mbox.o
> CC aarch64-softmmu/hw/misc/bcm2835_property.o
> CC aarch64-softmmu/hw/misc/bcm2835_rng.o
> CC x86_64-softmmu/trace/control-target.o
> CC aarch64-softmmu/hw/misc/zynq_slcr.o
> CC aarch64-softmmu/hw/misc/zynq-xadc.o
> CC aarch64-softmmu/hw/misc/stm32f2xx_syscfg.o
> CC aarch64-softmmu/hw/misc/mps2-scc.o
> CC x86_64-softmmu/gdbstub-xml.o
> CC aarch64-softmmu/hw/misc/auxbus.o
> CC aarch64-softmmu/hw/misc/aspeed_scu.o
> CC aarch64-softmmu/hw/misc/aspeed_sdmc.o
> CC x86_64-softmmu/trace/generated-helpers.o
> CC aarch64-softmmu/hw/misc/mmio_interface.o
> CC aarch64-softmmu/hw/misc/msf2-sysreg.o
> CC aarch64-softmmu/hw/net/virtio-net.o
> CC aarch64-softmmu/hw/net/vhost_net.o
> CC aarch64-softmmu/hw/pcmcia/pxa2xx.o
> CC aarch64-softmmu/hw/scsi/virtio-scsi.o
> CC aarch64-softmmu/hw/scsi/virtio-scsi-dataplane.o
> CC aarch64-softmmu/hw/sd/omap_mmc.o
> CC aarch64-softmmu/hw/sd/pxa2xx_mmci.o
> CC aarch64-softmmu/hw/sd/bcm2835_sdhost.o
> LINK x86_64-softmmu/qemu-system-x86_64w.exe
> CC aarch64-softmmu/hw/ssi/omap_spi.o
> CC aarch64-softmmu/hw/ssi/imx_spi.o
> CC aarch64-softmmu/hw/timer/exynos4210_mct.o
> CC aarch64-softmmu/hw/timer/exynos4210_pwm.o
> CC aarch64-softmmu/hw/timer/exynos4210_rtc.o
> CC aarch64-softmmu/hw/timer/omap_gptimer.o
> CC aarch64-softmmu/hw/timer/omap_synctimer.o
> CC aarch64-softmmu/hw/timer/pxa2xx_timer.o
> CC aarch64-softmmu/hw/timer/digic-timer.o
> CC aarch64-softmmu/hw/timer/allwinner-a10-pit.o
> CC aarch64-softmmu/hw/usb/tusb6010.o
> CC aarch64-softmmu/hw/virtio/virtio.o
> CC aarch64-softmmu/hw/virtio/virtio-balloon.o
> CC aarch64-softmmu/hw/virtio/virtio-crypto.o
> CC aarch64-softmmu/hw/virtio/virtio-crypto-pci.o
> CC aarch64-softmmu/hw/arm/boot.o
> CC aarch64-softmmu/hw/arm/collie.o
> CC aarch64-softmmu/hw/arm/exynos4_boards.o
> CC aarch64-softmmu/hw/arm/gumstix.o
> CC aarch64-softmmu/hw/arm/highbank.o
> CC aarch64-softmmu/hw/arm/digic_boards.o
> CC aarch64-softmmu/hw/arm/integratorcp.o
> CC aarch64-softmmu/hw/arm/mainstone.o
> CC aarch64-softmmu/hw/arm/musicpal.o
> CC aarch64-softmmu/hw/arm/nseries.o
> CC aarch64-softmmu/hw/arm/omap_sx1.o
> CC aarch64-softmmu/hw/arm/palm.o
> CC aarch64-softmmu/hw/arm/realview.o
> CC aarch64-softmmu/hw/arm/spitz.o
> CC aarch64-softmmu/hw/arm/stellaris.o
> CC aarch64-softmmu/hw/arm/tosa.o
> CC aarch64-softmmu/hw/arm/versatilepb.o
> CC aarch64-softmmu/hw/arm/vexpress.o
> CC aarch64-softmmu/hw/arm/virt.o
> CC aarch64-softmmu/hw/arm/xilinx_zynq.o
> CC aarch64-softmmu/hw/arm/z2.o
> CC aarch64-softmmu/hw/arm/virt-acpi-build.o
> CC aarch64-softmmu/hw/arm/netduino2.o
> CC aarch64-softmmu/hw/arm/sysbus-fdt.o
> CC aarch64-softmmu/hw/arm/armv7m.o
> CC aarch64-softmmu/hw/arm/exynos4210.o
> CC aarch64-softmmu/hw/arm/pxa2xx.o
> CC aarch64-softmmu/hw/arm/pxa2xx_gpio.o
> CC aarch64-softmmu/hw/arm/pxa2xx_pic.o
> CC aarch64-softmmu/hw/arm/digic.o
> CC aarch64-softmmu/hw/arm/omap1.o
> CC aarch64-softmmu/hw/arm/omap2.o
> CC aarch64-softmmu/hw/arm/strongarm.o
> CC aarch64-softmmu/hw/arm/allwinner-a10.o
> CC aarch64-softmmu/hw/arm/cubieboard.o
> CC aarch64-softmmu/hw/arm/bcm2835_peripherals.o
> CC aarch64-softmmu/hw/arm/bcm2836.o
> CC aarch64-softmmu/hw/arm/raspi.o
> CC aarch64-softmmu/hw/arm/stm32f205_soc.o
> CC aarch64-softmmu/hw/arm/xlnx-zynqmp.o
> CC aarch64-softmmu/hw/arm/xlnx-zcu102.o
> CC aarch64-softmmu/hw/arm/fsl-imx25.o
> CC aarch64-softmmu/hw/arm/imx25_pdk.o
> CC aarch64-softmmu/hw/arm/fsl-imx31.o
> CC aarch64-softmmu/hw/arm/kzm.o
> CC aarch64-softmmu/hw/arm/fsl-imx6.o
> CC aarch64-softmmu/hw/arm/sabrelite.o
> CC aarch64-softmmu/hw/arm/aspeed_soc.o
> CC aarch64-softmmu/hw/arm/mps2.o
> CC aarch64-softmmu/hw/arm/aspeed.o
> CC aarch64-softmmu/hw/arm/msf2-soc.o
> CC aarch64-softmmu/hw/arm/msf2-som.o
> CC aarch64-softmmu/hw/arm/smmu-common.o
> CC aarch64-softmmu/hw/arm/smmuv3.o
> CC aarch64-softmmu/target/arm/machine.o
> CC aarch64-softmmu/target/arm/arm-semi.o
> CC aarch64-softmmu/target/arm/psci.o
> CC aarch64-softmmu/target/arm/arch_dump.o
> CC aarch64-softmmu/target/arm/monitor.o
> CC aarch64-softmmu/target/arm/kvm-stub.o
> CC aarch64-softmmu/target/arm/translate.o
> CC aarch64-softmmu/target/arm/op_helper.o
> CC aarch64-softmmu/target/arm/helper.o
> CC aarch64-softmmu/target/arm/cpu.o
> CC aarch64-softmmu/target/arm/neon_helper.o
> CC aarch64-softmmu/target/arm/iwmmxt_helper.o
> CC aarch64-softmmu/target/arm/gdbstub.o
> CC aarch64-softmmu/target/arm/cpu64.o
> CC aarch64-softmmu/target/arm/translate-a64.o
> In file included from /tmp/qemu-test/src/hw/arm/smmuv3.c:31:0:
> /tmp/qemu-test/src/hw/arm/smmuv3-internal.h: In function 'smmu_read64':
> /tmp/qemu-test/src/hw/arm/smmuv3-internal.h:146:9: error: implicit declaration of function 'qemu_log_mask' [-Werror=implicit-function-declaration]
> qemu_log_mask(LOG_GUEST_ERROR,
> ^~~~~~~~~~~~~
> /tmp/qemu-test/src/hw/arm/smmuv3-internal.h:146:9: error: nested extern declaration of 'qemu_log_mask' [-Werror=nested-externs]
> /tmp/qemu-test/src/hw/arm/smmuv3-internal.h:146:23: error: 'LOG_GUEST_ERROR' undeclared (first use in this function)
> qemu_log_mask(LOG_GUEST_ERROR,
> ^~~~~~~~~~~~~~~
> /tmp/qemu-test/src/hw/arm/smmuv3-internal.h:146:23: note: each undeclared identifier is reported only once for each function it appears in
> /tmp/qemu-test/src/hw/arm/smmuv3-internal.h: In function 'smmu_write64':
> /tmp/qemu-test/src/hw/arm/smmuv3-internal.h:165:23: error: 'LOG_GUEST_ERROR' undeclared (first use in this function)
> qemu_log_mask(LOG_GUEST_ERROR,
> ^~~~~~~~~~~~~~~
> /tmp/qemu-test/src/hw/arm/smmuv3.c: In function 'smmuv3_write_gerrorn':
> /tmp/qemu-test/src/hw/arm/smmuv3.c:86:23: error: 'LOG_GUEST_ERROR' undeclared (first use in this function)
> qemu_log_mask(LOG_GUEST_ERROR,
> ^~~~~~~~~~~~~~~
> /tmp/qemu-test/src/hw/arm/smmuv3.c: In function 'smmu_get_ste':
> /tmp/qemu-test/src/hw/arm/smmuv3.c:304:23: error: 'LOG_GUEST_ERROR' undeclared (first use in this function)
> qemu_log_mask(LOG_GUEST_ERROR,
> ^~~~~~~~~~~~~~~
> /tmp/qemu-test/src/hw/arm/smmuv3.c: In function 'smmu_get_cd':
> /tmp/qemu-test/src/hw/arm/smmuv3.c:325:23: error: 'LOG_GUEST_ERROR' undeclared (first use in this function)
> qemu_log_mask(LOG_GUEST_ERROR,
> ^~~~~~~~~~~~~~~
> /tmp/qemu-test/src/hw/arm/smmuv3.c: In function 'smmu_write_mmio':
> /tmp/qemu-test/src/hw/arm/smmuv3.c:710:23: error: 'LOG_GUEST_ERROR' undeclared (first use in this function)
> qemu_log_mask(LOG_GUEST_ERROR,
> ^~~~~~~~~~~~~~~
> /tmp/qemu-test/src/hw/arm/smmuv3.c: In function 'smmu_read_mmio':
> /tmp/qemu-test/src/hw/arm/smmuv3.c:818:23: error: 'LOG_GUEST_ERROR' undeclared (first use in this function)
> qemu_log_mask(LOG_GUEST_ERROR, "SMMUv3 MMIO read: bad size %u\n", size);
> ^~~~~~~~~~~~~~~
> cc1: all warnings being treated as errors
> make[1]: *** [hw/arm/smmuv3.o] Error 1
> make[1]: *** Waiting for unfinished jobs....
> /tmp/qemu-test/src/rules.mak:66: recipe for target 'hw/arm/smmuv3.o' failed
> /tmp/qemu-test/src/hw/arm/smmu-common.c: In function 'get_pte':
> /tmp/qemu-test/src/hw/arm/smmu-common.c:52:9: error: implicit declaration of function 'qemu_log_mask' [-Werror=implicit-function-declaration]
> qemu_log_mask(LOG_GUEST_ERROR,
> ^~~~~~~~~~~~~
> /tmp/qemu-test/src/hw/arm/smmu-common.c:52:9: error: nested extern declaration of 'qemu_log_mask' [-Werror=nested-externs]
> /tmp/qemu-test/src/hw/arm/smmu-common.c:52:23: error: 'LOG_GUEST_ERROR' undeclared (first use in this function)
> qemu_log_mask(LOG_GUEST_ERROR,
> ^~~~~~~~~~~~~~~
> /tmp/qemu-test/src/hw/arm/smmu-common.c:52:23: note: each undeclared identifier is reported only once for each function it appears in
> cc1: all warnings being treated as errors
> make[1]: *** [hw/arm/smmu-common.o] Error 1
> /tmp/qemu-test/src/rules.mak:66: recipe for target 'hw/arm/smmu-common.o' failed
> GEN x86_64-softmmu/qemu-system-x86_64.exe
> Makefile:403: recipe for target 'subdir-aarch64-softmmu' failed
> make: *** [subdir-aarch64-softmmu] Error 2
> Traceback (most recent call last):
> File "./tests/docker/docker.py", line 407, in <module>
> sys.exit(main())
> File "./tests/docker/docker.py", line 404, in main
> return args.cmdobj.run(args, argv)
> File "./tests/docker/docker.py", line 261, in run
> return Docker().run(argv, args.keep, quiet=args.quiet)
> File "./tests/docker/docker.py", line 229, in run
> quiet=quiet)
> File "./tests/docker/docker.py", line 147, in _do_check
> return subprocess.check_call(self._command + cmd, **kwargs)
> File "/usr/lib64/python2.7/subprocess.py", line 186, in check_call
> raise CalledProcessError(retcode, cmd)
> subprocess.CalledProcessError: Command '['docker', 'run', '--label', 'com.qemu.instance.uuid=ef6dda8c0a8311e8bac352540069c830', '-u', '0', '--security-opt', 'seccomp=unconfined', '--rm', '--net=none', '-e', 'TARGET_LIST=', '-e', 'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=8', '-e', 'DEBUG=', '-e', 'SHOW_ENV=1', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', '/root/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', '/var/tmp/patchew-tester-tmp-iv9dq1c5/src/docker-src.2018-02-05-09.50.27.14305:/var/tmp/qemu:z,ro', 'qemu:fedora', '/var/tmp/qemu/run', 'test-mingw']' returned non-zero exit status 2
> make[1]: *** [tests/docker/Makefile.include:129: docker-run] Error 1
> make: *** [tests/docker/Makefile.include:163: docker-run-test-mingw@fedora] Error 2
I will add
#include "qemu/log.h" in smmuv3-internal.h in next release, to fix this
mingw compilation issue.
Thanks
Eric
>
> real 2m38.217s
> user 0m5.050s
> sys 0m3.655s
> === OUTPUT END ===
>
> Test command exited with code: 2
>
>
> ---
> Email generated automatically by Patchew [http://patchew.org/].
> Please send your feedback to patchew-devel@freelists.org
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support
2018-02-06 12:22 ` Auger Eric
@ 2018-02-06 12:45 ` Peter Maydell
0 siblings, 0 replies; 18+ messages in thread
From: Peter Maydell @ 2018-02-06 12:45 UTC (permalink / raw)
To: Auger Eric
Cc: QEMU Developers, Fam Zheng, eric.auger.pro, qemu-arm,
Prem Mallappa, Alex Williamson, Michael S. Tsirkin,
Jean-Philippe Brucker, Tomasz Nowicki, Peter Xu,
Edgar E. Iglesias, linuc.decode, Bharat Bhushan, Christoffer Dall
On 6 February 2018 at 12:22, Auger Eric <eric.auger@redhat.com> wrote:
> I will add
> #include "qemu/log.h" in smmuv3-internal.h in next release, to fix this
> mingw compilation issue.
It's an issue with configs that don't use the 'log' trace
backend, rather than mingw specifically. (It just happens
that patchew's mingw backend is the one that's configured
with a different trace backend.) The default backend means
trace.h includes log.h.
I really ought to write some patches to make this be an
error always rather than only if you configured a different
trace backend...
thanks
-- PMM
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2018-02-06 12:46 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-02-05 13:39 [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 01/14] hw/arm/smmu-common: smmu base device and datatypes Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 02/14] hw/arm/smmu-common: IOMMU memory region and address space setup Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 03/14] hw/arm/smmu-common: VMSAv8-64 page table walk Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 04/14] hw/arm/smmuv3: Skeleton Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 05/14] hw/arm/smmuv3: Wired IRQ and GERROR helpers Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 06/14] hw/arm/smmuv3: Queue helpers Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 07/14] hw/arm/smmuv3: Implement MMIO write operations Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 08/14] hw/arm/smmuv3: Event queue recording helper Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 09/14] hw/arm/smmuv3: Implement translate callback Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 10/14] hw/arm/smmuv3: Abort on vfio or vhost case Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 11/14] target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 12/14] hw/arm/virt: Add SMMUv3 to the virt board Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 13/14] hw/arm/virt-acpi-build: Add smmuv3 node in IORT table Eric Auger
2018-02-05 13:39 ` [Qemu-devel] [PATCH v8 14/14] hw/arm/virt: Handle iommu in 2.12 machine type Eric Auger
2018-02-05 14:53 ` [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support no-reply
2018-02-06 12:22 ` Auger Eric
2018-02-06 12:45 ` Peter Maydell
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