From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32821) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ejb2b-0002vI-Ul for qemu-devel@nongnu.org; Wed, 07 Feb 2018 20:30:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ejb2a-0001OW-R3 for qemu-devel@nongnu.org; Wed, 07 Feb 2018 20:30:21 -0500 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:43169) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ejb2a-0001NM-Km for qemu-devel@nongnu.org; Wed, 07 Feb 2018 20:30:20 -0500 Received: by mail-pf0-x243.google.com with SMTP id b62so1129773pfk.10 for ; Wed, 07 Feb 2018 17:30:20 -0800 (PST) From: Michael Clark Date: Thu, 8 Feb 2018 14:28:27 +1300 Message-Id: <1518053328-34687-3-git-send-email-mjc@sifive.com> In-Reply-To: <1518053328-34687-1-git-send-email-mjc@sifive.com> References: <1518053328-34687-1-git-send-email-mjc@sifive.com> Subject: [Qemu-devel] [PATCH v5 02/23] RISC-V ELF Machine Definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann , RISC-V Patches Define RISC-V ELF machine EM_RISCV 243 Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Michael Clark --- include/elf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/elf.h b/include/elf.h index e8a515c..8e457fc 100644 --- a/include/elf.h +++ b/include/elf.h @@ -112,6 +112,8 @@ typedef int64_t Elf64_Sxword; #define EM_UNICORE32 110 /* UniCore32 */ +#define EM_RISCV 243 /* RISC-V */ + /* * This is an interim value that we will use until the committee comes * up with a final number. -- 2.7.0