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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [Qemu-devel] [PULL 20/48] sdhci: add a 'spec_version property' (default to v2)
Date: Tue, 13 Feb 2018 13:00:24 +0100	[thread overview]
Message-ID: <1518523252-49106-21-git-send-email-pbonzini@redhat.com> (raw)
In-Reply-To: <1518523252-49106-1-git-send-email-pbonzini@redhat.com>

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Message-Id: <20180208164818.7961-8-f4bug@amsat.org>
---
 hw/sd/sdhci-internal.h |  4 ++--
 hw/sd/sdhci.c          | 27 +++++++++++++++++++++++----
 include/hw/sd/sdhci.h  |  2 ++
 3 files changed, 27 insertions(+), 6 deletions(-)

diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index 0991acd..6455648 100644
--- a/hw/sd/sdhci-internal.h
+++ b/hw/sd/sdhci-internal.h
@@ -216,9 +216,9 @@
 /* Slot interrupt status */
 #define SDHC_SLOT_INT_STATUS            0xFC
 
-/* HWInit Host Controller Version Register 0x0401 */
+/* HWInit Host Controller Version Register */
 #define SDHC_HCVER                      0xFE
-#define SD_HOST_SPECv2_VERS             0x2401
+#define SDHC_HCVER_VENDOR               0x24
 
 #define SDHC_REGISTERS_MAP_SIZE         0x100
 #define SDHC_INSERTION_DELAY            (NANOSECONDS_PER_SECOND)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 3602286..17a1348 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -173,7 +173,8 @@ static void sdhci_reset(SDHCIState *s)
 
     timer_del(s->insert_timer);
     timer_del(s->transfer_timer);
-    /* Set all registers to 0. Capabilities registers are not cleared
+
+    /* Set all registers to 0. Capabilities/Version registers are not cleared
      * and assumed to always preserve their value, given to them during
      * initialization */
     memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad);
@@ -918,7 +919,7 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
         ret = (uint32_t)(s->admasysaddr >> 32);
         break;
     case SDHC_SLOT_INT_STATUS:
-        ret = (SD_HOST_SPECv2_VERS << 16) | sdhci_slotint(s);
+        ret = (s->version << 16) | sdhci_slotint(s);
         break;
     default:
         qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " "
@@ -1174,11 +1175,22 @@ static inline unsigned int sdhci_get_fifolen(SDHCIState *s)
     }
 }
 
+static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp)
+{
+    if (s->sd_spec_version != 2) {
+        error_setg(errp, "Only Spec v2 is supported");
+        return;
+    }
+    s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1);
+}
+
 /* --- qdev common --- */
 
 #define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \
-    /* Capabilities registers provide information on supported features
-     * of this specific host controller implementation */ \
+    DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \
+    \
+    /* Capabilities registers provide information on supported
+     * features of this specific host controller implementation */ \
     DEFINE_PROP_UINT64("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \
     DEFINE_PROP_UINT64("maxcurr", _state, maxcurr, 0)
 
@@ -1206,6 +1218,13 @@ static void sdhci_uninitfn(SDHCIState *s)
 
 static void sdhci_common_realize(SDHCIState *s, Error **errp)
 {
+    Error *local_err = NULL;
+
+    sdhci_init_readonly_registers(s, &local_err);
+    if (local_err) {
+        error_propagate(errp, local_err);
+        return;
+    }
     s->buf_maxsz = sdhci_get_fifolen(s);
     s->fifo_buffer = g_malloc0(s->buf_maxsz);
 
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index f8d1ba3..2a26b46 100644
--- a/include/hw/sd/sdhci.h
+++ b/include/hw/sd/sdhci.h
@@ -78,6 +78,7 @@ typedef struct SDHCIState {
     /* Read-only registers */
     uint64_t capareg;      /* Capabilities Register */
     uint64_t maxcurr;      /* Maximum Current Capabilities Register */
+    uint16_t version;      /* Host Controller Version Register */
 
     uint8_t  *fifo_buffer; /* SD host i/o FIFO buffer */
     uint32_t buf_maxsz;
@@ -93,6 +94,7 @@ typedef struct SDHCIState {
     /* Configurable properties */
     bool pending_insert_quirk; /* Quirk for Raspberry Pi card insert int */
     uint32_t quirks;
+    uint8_t sd_spec_version;
 } SDHCIState;
 
 /*
-- 
1.8.3.1

  parent reply	other threads:[~2018-02-13 12:02 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-13 12:00 [Qemu-devel] [PULL 00/48] Misc patches for 2018-02-13 Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 01/48] Revert "build-sys: silence make by default or V=0" Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 02/48] make: fix help message reference to bogus V=0 variable Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 03/48] hax: Support guest RAM sizes of 4GB or more Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 04/48] net/can: simple messages transport implementation for QEMU Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 05/48] net/can: support for connecting to Linux host SocketCAN interface Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 06/48] hw/net/can: SJA1000 chip register level emulation for QEMU Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 07/48] hw/net/can: Kvaser PCI CAN-S (single SJA1000 channel) emulation Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 08/48] hw/net/can: PCM-3680I PCI (dual " Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 09/48] hw/net/can: MIOe-3680 " Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 10/48] net/can: documentation Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 11/48] hw/net/can: interrupt cleanup Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 12/48] build-sys: remove useless extra*flags variables Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 13/48] build-sys: check static linking of UBSAN Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 14/48] sdhci: use error_propagate(local_err) in realize() Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 15/48] sdhci: add qtest to check the SD capabilities register Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 16/48] sdhci: add check_capab_readonly() qtest Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 17/48] sdhci: add a check_capab_baseclock() qtest Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 18/48] sdhci: add a check_capab_sdma() qtest Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 19/48] sdhci: add qtest to check the SD Spec version Paolo Bonzini
2018-02-13 12:00 ` Paolo Bonzini [this message]
2018-02-13 12:00 ` [Qemu-devel] [PULL 21/48] sdhci: use a numeric value for the default CAPAB register Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 22/48] sdhci: simplify sdhci_get_fifolen() Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 23/48] sdhci: check the Spec v1 capabilities correctness Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 25/48] sdhci: Fix 64-bit ADMA2 Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 27/48] hw/arm/exynos4210: access the 64-bit capareg with qdev_prop_set_uint64() Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 28/48] hw/arm/exynos4210: add a comment about a very similar SDHCI (Spec. v2) Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 29/48] hw/arm/xilinx_zynq: fix the capabilities register to match the datasheet Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 31/48] sdhci: rename the hostctl1 register Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 32/48] sdhci: implement the Host Control 2 register (tuning sequence) Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 33/48] sdbus: add trace events Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 34/48] sdhci: implement UHS-I voltage switch Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 35/48] sdhci: implement CMD/DAT[] fields in the Present State register Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 36/48] hw/arm/bcm2835_peripherals: implement SDHCI Spec v3 Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 37/48] hw/arm/bcm2835_peripherals: change maximum block size to 1kB Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 38/48] hw/arm/fsl-imx6: implement SDHCI Spec. v3 Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 39/48] hw/arm/xilinx_zynqmp: fix the capabilities/spec version to match the datasheet Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 40/48] hw/arm/xilinx_zynqmp: enable the UHS-I mode Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 41/48] sdhci: check Spec v3 capabilities qtest Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 42/48] sdhci: add a check_capab_v3() qtest Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 43/48] sdhci: add Spec v4.2 register definitions Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 44/48] g364fb: switch to using DirtyBitmapSnapshot Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 45/48] memory: remove memory_region_test_and_clear_dirty Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 46/48] memory: hide memory_region_sync_dirty_bitmap behind DirtyBitmapSnapshot Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 47/48] memory: unify loops to sync dirty log bitmap Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 48/48] travis: use libgcc-4.8-dev (libgcc-6-dev is not available on Ubuntu 14.04) Paolo Bonzini
2018-02-13 14:37 ` [Qemu-devel] [PULL 00/48] Misc patches for 2018-02-13 Peter Maydell
2018-02-13 15:10   ` Paolo Bonzini

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