From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [Qemu-devel] [PULL 21/48] sdhci: use a numeric value for the default CAPAB register
Date: Tue, 13 Feb 2018 13:00:25 +0100 [thread overview]
Message-ID: <1518523252-49106-22-git-send-email-pbonzini@redhat.com> (raw)
In-Reply-To: <1518523252-49106-1-git-send-email-pbonzini@redhat.com>
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
using many #defines is not portable when scaling to different HCI.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Message-Id: <20180208164818.7961-9-f4bug@amsat.org>
---
hw/sd/sdhci.c | 74 +++++++++++++----------------------------------------------
1 file changed, 16 insertions(+), 58 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 17a1348..491e624 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -38,67 +38,25 @@
#define TYPE_SDHCI_BUS "sdhci-bus"
#define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS)
+#define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
+
/* Default SD/MMC host controller features information, which will be
* presented in CAPABILITIES register of generic SD host controller at reset.
- * If not stated otherwise:
- * 0 - not supported, 1 - supported, other - prohibited.
+ *
+ * support:
+ * - 3.3v and 1.8v voltages
+ * - SDMA/ADMA1/ADMA2
+ * - high-speed
+ * max host controller R/W buffers size: 512B
+ * max clock frequency for SDclock: 52 MHz
+ * timeout clock frequency: 52 MHz
+ *
+ * does not support:
+ * - 3.0v voltage
+ * - 64-bit system bus
+ * - suspend/resume
*/
-#define SDHC_CAPAB_64BITBUS 0ul /* 64-bit System Bus Support */
-#define SDHC_CAPAB_18V 1ul /* Voltage support 1.8v */
-#define SDHC_CAPAB_30V 0ul /* Voltage support 3.0v */
-#define SDHC_CAPAB_33V 1ul /* Voltage support 3.3v */
-#define SDHC_CAPAB_SUSPRESUME 0ul /* Suspend/resume support */
-#define SDHC_CAPAB_SDMA 1ul /* SDMA support */
-#define SDHC_CAPAB_HIGHSPEED 1ul /* High speed support */
-#define SDHC_CAPAB_ADMA1 1ul /* ADMA1 support */
-#define SDHC_CAPAB_ADMA2 1ul /* ADMA2 support */
-/* Maximum host controller R/W buffers size
- * Possible values: 512, 1024, 2048 bytes */
-#define SDHC_CAPAB_MAXBLOCKLENGTH 512ul
-/* Maximum clock frequency for SDclock in MHz
- * value in range 10-63 MHz, 0 - not defined */
-#define SDHC_CAPAB_BASECLKFREQ 52ul
-#define SDHC_CAPAB_TOUNIT 1ul /* Timeout clock unit 0 - kHz, 1 - MHz */
-/* Timeout clock frequency 1-63, 0 - not defined */
-#define SDHC_CAPAB_TOCLKFREQ 52ul
-
-/* Now check all parameters and calculate CAPABILITIES REGISTER value */
-#if SDHC_CAPAB_64BITBUS > 1 || SDHC_CAPAB_18V > 1 || SDHC_CAPAB_30V > 1 || \
- SDHC_CAPAB_33V > 1 || SDHC_CAPAB_SUSPRESUME > 1 || SDHC_CAPAB_SDMA > 1 || \
- SDHC_CAPAB_HIGHSPEED > 1 || SDHC_CAPAB_ADMA2 > 1 || SDHC_CAPAB_ADMA1 > 1 ||\
- SDHC_CAPAB_TOUNIT > 1
-#error Capabilities features can have value 0 or 1 only!
-#endif
-
-#if SDHC_CAPAB_MAXBLOCKLENGTH == 512
-#define MAX_BLOCK_LENGTH 0ul
-#elif SDHC_CAPAB_MAXBLOCKLENGTH == 1024
-#define MAX_BLOCK_LENGTH 1ul
-#elif SDHC_CAPAB_MAXBLOCKLENGTH == 2048
-#define MAX_BLOCK_LENGTH 2ul
-#else
-#error Max host controller block size can have value 512, 1024 or 2048 only!
-#endif
-
-#if (SDHC_CAPAB_BASECLKFREQ > 0 && SDHC_CAPAB_BASECLKFREQ < 10) || \
- SDHC_CAPAB_BASECLKFREQ > 63
-#error SDclock frequency can have value in range 0, 10-63 only!
-#endif
-
-#if SDHC_CAPAB_TOCLKFREQ > 63
-#error Timeout clock frequency can have value in range 0-63 only!
-#endif
-
-#define SDHC_CAPAB_REG_DEFAULT \
- ((SDHC_CAPAB_64BITBUS << 28) | (SDHC_CAPAB_18V << 26) | \
- (SDHC_CAPAB_30V << 25) | (SDHC_CAPAB_33V << 24) | \
- (SDHC_CAPAB_SUSPRESUME << 23) | (SDHC_CAPAB_SDMA << 22) | \
- (SDHC_CAPAB_HIGHSPEED << 21) | (SDHC_CAPAB_ADMA1 << 20) | \
- (SDHC_CAPAB_ADMA2 << 19) | (MAX_BLOCK_LENGTH << 16) | \
- (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \
- (SDHC_CAPAB_TOCLKFREQ))
-
-#define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
+#define SDHC_CAPAB_REG_DEFAULT 0x057834b4
static uint8_t sdhci_slotint(SDHCIState *s)
{
--
1.8.3.1
next prev parent reply other threads:[~2018-02-13 12:02 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-13 12:00 [Qemu-devel] [PULL 00/48] Misc patches for 2018-02-13 Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 01/48] Revert "build-sys: silence make by default or V=0" Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 02/48] make: fix help message reference to bogus V=0 variable Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 03/48] hax: Support guest RAM sizes of 4GB or more Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 04/48] net/can: simple messages transport implementation for QEMU Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 05/48] net/can: support for connecting to Linux host SocketCAN interface Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 06/48] hw/net/can: SJA1000 chip register level emulation for QEMU Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 07/48] hw/net/can: Kvaser PCI CAN-S (single SJA1000 channel) emulation Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 08/48] hw/net/can: PCM-3680I PCI (dual " Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 09/48] hw/net/can: MIOe-3680 " Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 10/48] net/can: documentation Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 11/48] hw/net/can: interrupt cleanup Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 12/48] build-sys: remove useless extra*flags variables Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 13/48] build-sys: check static linking of UBSAN Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 14/48] sdhci: use error_propagate(local_err) in realize() Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 15/48] sdhci: add qtest to check the SD capabilities register Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 16/48] sdhci: add check_capab_readonly() qtest Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 17/48] sdhci: add a check_capab_baseclock() qtest Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 18/48] sdhci: add a check_capab_sdma() qtest Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 19/48] sdhci: add qtest to check the SD Spec version Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 20/48] sdhci: add a 'spec_version property' (default to v2) Paolo Bonzini
2018-02-13 12:00 ` Paolo Bonzini [this message]
2018-02-13 12:00 ` [Qemu-devel] [PULL 22/48] sdhci: simplify sdhci_get_fifolen() Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 23/48] sdhci: check the Spec v1 capabilities correctness Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 25/48] sdhci: Fix 64-bit ADMA2 Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 27/48] hw/arm/exynos4210: access the 64-bit capareg with qdev_prop_set_uint64() Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 28/48] hw/arm/exynos4210: add a comment about a very similar SDHCI (Spec. v2) Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 29/48] hw/arm/xilinx_zynq: fix the capabilities register to match the datasheet Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 31/48] sdhci: rename the hostctl1 register Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 32/48] sdhci: implement the Host Control 2 register (tuning sequence) Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 33/48] sdbus: add trace events Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 34/48] sdhci: implement UHS-I voltage switch Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 35/48] sdhci: implement CMD/DAT[] fields in the Present State register Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 36/48] hw/arm/bcm2835_peripherals: implement SDHCI Spec v3 Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 37/48] hw/arm/bcm2835_peripherals: change maximum block size to 1kB Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 38/48] hw/arm/fsl-imx6: implement SDHCI Spec. v3 Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 39/48] hw/arm/xilinx_zynqmp: fix the capabilities/spec version to match the datasheet Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 40/48] hw/arm/xilinx_zynqmp: enable the UHS-I mode Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 41/48] sdhci: check Spec v3 capabilities qtest Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 42/48] sdhci: add a check_capab_v3() qtest Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 43/48] sdhci: add Spec v4.2 register definitions Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 44/48] g364fb: switch to using DirtyBitmapSnapshot Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 45/48] memory: remove memory_region_test_and_clear_dirty Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 46/48] memory: hide memory_region_sync_dirty_bitmap behind DirtyBitmapSnapshot Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 47/48] memory: unify loops to sync dirty log bitmap Paolo Bonzini
2018-02-13 12:00 ` [Qemu-devel] [PULL 48/48] travis: use libgcc-4.8-dev (libgcc-6-dev is not available on Ubuntu 14.04) Paolo Bonzini
2018-02-13 14:37 ` [Qemu-devel] [PULL 00/48] Misc patches for 2018-02-13 Peter Maydell
2018-02-13 15:10 ` Paolo Bonzini
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