* [Qemu-devel] [PATCHv2 1/2] translator: merge max_insns into DisasContextBase
2018-02-20 2:26 [Qemu-devel] [PATCHv2 0/2] target/sh4: translator loop conversion Emilio G. Cota
@ 2018-02-20 2:26 ` Emilio G. Cota
2018-02-21 18:19 ` Richard Henderson
2018-02-20 2:26 ` [Qemu-devel] [PATCHv2 2/2] target/sh4: convert to TranslatorOps Emilio G. Cota
1 sibling, 1 reply; 6+ messages in thread
From: Emilio G. Cota @ 2018-02-20 2:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Aurelien Jarno
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
accel/tcg/translator.c | 21 ++++++++++-----------
include/exec/translator.h | 6 +++---
target/alpha/translate.c | 6 ++----
target/arm/translate-a64.c | 8 +++-----
target/arm/translate.c | 9 +++------
target/hppa/translate.c | 7 ++-----
target/i386/translate.c | 5 +----
target/ppc/translate.c | 5 ++---
8 files changed, 26 insertions(+), 41 deletions(-)
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index 23c6602..0f9dca9 100644
--- a/accel/tcg/translator.c
+++ b/accel/tcg/translator.c
@@ -34,8 +34,6 @@ void translator_loop_temp_check(DisasContextBase *db)
void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
CPUState *cpu, TranslationBlock *tb)
{
- int max_insns;
-
/* Initialize DisasContext */
db->tb = tb;
db->pc_first = tb->pc;
@@ -45,18 +43,18 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
db->singlestep_enabled = cpu->singlestep_enabled;
/* Instruction counting */
- max_insns = tb_cflags(db->tb) & CF_COUNT_MASK;
- if (max_insns == 0) {
- max_insns = CF_COUNT_MASK;
+ db->max_insns = tb_cflags(db->tb) & CF_COUNT_MASK;
+ if (db->max_insns == 0) {
+ db->max_insns = CF_COUNT_MASK;
}
- if (max_insns > TCG_MAX_INSNS) {
- max_insns = TCG_MAX_INSNS;
+ if (db->max_insns > TCG_MAX_INSNS) {
+ db->max_insns = TCG_MAX_INSNS;
}
if (db->singlestep_enabled || singlestep) {
- max_insns = 1;
+ db->max_insns = 1;
}
- max_insns = ops->init_disas_context(db, cpu, max_insns);
+ ops->init_disas_context(db, cpu);
tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */
/* Reset the temp count so that we can identify leaks */
@@ -95,7 +93,8 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
update db->pc_next and db->is_jmp to indicate what should be
done next -- either exiting this loop or locate the start of
the next instruction. */
- if (db->num_insns == max_insns && (tb_cflags(db->tb) & CF_LAST_IO)) {
+ if (db->num_insns == db->max_insns
+ && (tb_cflags(db->tb) & CF_LAST_IO)) {
/* Accept I/O on the last instruction. */
gen_io_start();
ops->translate_insn(db, cpu);
@@ -111,7 +110,7 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
/* Stop translation if the output buffer is full,
or we have executed all of the allowed instructions. */
- if (tcg_op_buf_full() || db->num_insns >= max_insns) {
+ if (tcg_op_buf_full() || db->num_insns >= db->max_insns) {
db->is_jmp = DISAS_TOO_MANY;
break;
}
diff --git a/include/exec/translator.h b/include/exec/translator.h
index e2dc2a0..6d7412a 100644
--- a/include/exec/translator.h
+++ b/include/exec/translator.h
@@ -58,6 +58,7 @@ typedef enum DisasJumpType {
* disassembly).
* @is_jmp: What instruction to disassemble next.
* @num_insns: Number of translated instructions (including current).
+ * @max_insns: Maximum number of instructions to be translated in this TB.
* @singlestep_enabled: "Hardware" single stepping enabled.
*
* Architecture-agnostic disassembly context.
@@ -68,6 +69,7 @@ typedef struct DisasContextBase {
target_ulong pc_next;
DisasJumpType is_jmp;
unsigned int num_insns;
+ int max_insns;
bool singlestep_enabled;
} DisasContextBase;
@@ -76,7 +78,6 @@ typedef struct DisasContextBase {
* @init_disas_context:
* Initialize the target-specific portions of DisasContext struct.
* The generic DisasContextBase has already been initialized.
- * Return max_insns, modified as necessary by db->tb->flags.
*
* @tb_start:
* Emit any code required before the start of the main loop,
@@ -106,8 +107,7 @@ typedef struct DisasContextBase {
* Print instruction disassembly to log.
*/
typedef struct TranslatorOps {
- int (*init_disas_context)(DisasContextBase *db, CPUState *cpu,
- int max_insns);
+ void (*init_disas_context)(DisasContextBase *db, CPUState *cpu);
void (*tb_start)(DisasContextBase *db, CPUState *cpu);
void (*insn_start)(DisasContextBase *db, CPUState *cpu);
bool (*breakpoint_check)(DisasContextBase *db, CPUState *cpu,
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 73a1b5e..15eca71 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -2919,8 +2919,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
return ret;
}
-static int alpha_tr_init_disas_context(DisasContextBase *dcbase,
- CPUState *cpu, int max_insns)
+static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPUAlphaState *env = cpu->env_ptr;
@@ -2959,8 +2958,7 @@ static int alpha_tr_init_disas_context(DisasContextBase *dcbase,
mask = TARGET_PAGE_MASK;
}
bound = -(ctx->base.pc_first | mask) / 4;
-
- return MIN(max_insns, bound);
+ ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
}
static void alpha_tr_tb_start(DisasContextBase *db, CPUState *cpu)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 1c88539..55f00a6 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -12009,8 +12009,8 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
free_tmp_a64(s);
}
-static int aarch64_tr_init_disas_context(DisasContextBase *dcbase,
- CPUState *cpu, int max_insns)
+static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
+ CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
CPUARMState *env = cpu->env_ptr;
@@ -12073,11 +12073,9 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase,
if (dc->ss_active) {
bound = 1;
}
- max_insns = MIN(max_insns, bound);
+ dc->base.max_insns = MIN(dc->base.max_insns, bound);
init_tmp_a64_array(dc);
-
- return max_insns;
}
static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 1270022..9284975 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -11975,8 +11975,7 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
return !thumb_insn_is_16bit(s, insn);
}
-static int arm_tr_init_disas_context(DisasContextBase *dcbase,
- CPUState *cs, int max_insns)
+static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
CPUARMState *env = cs->env_ptr;
@@ -12038,14 +12037,14 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase,
/* If architectural single step active, limit to 1. */
if (is_singlestepping(dc)) {
- max_insns = 1;
+ dc->base.max_insns = 1;
}
/* ARM is a fixed-length ISA. Bound the number of insns to execute
to those left on the page. */
if (!dc->thumb) {
int bound = (dc->next_page_start - dc->base.pc_first) / 4;
- max_insns = MIN(max_insns, bound);
+ dc->base.max_insns = MIN(dc->base.max_insns, bound);
}
cpu_F0s = tcg_temp_new_i32();
@@ -12056,8 +12055,6 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase,
cpu_V1 = cpu_F1d;
/* FIXME: cpu_M0 can probably be the same as cpu_V0. */
cpu_M0 = tcg_temp_new_i64();
-
- return max_insns;
}
static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 6499b39..1afca76 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -4685,8 +4685,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
return gen_illegal(ctx);
}
-static int hppa_tr_init_disas_context(DisasContextBase *dcbase,
- CPUState *cs, int max_insns)
+static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
int bound;
@@ -4716,14 +4715,12 @@ static int hppa_tr_init_disas_context(DisasContextBase *dcbase,
/* Bound the number of instructions by those left on the page. */
bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
- bound = MIN(max_insns, bound);
+ ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
ctx->ntempr = 0;
ctx->ntempl = 0;
memset(ctx->tempr, 0, sizeof(ctx->tempr));
memset(ctx->templ, 0, sizeof(ctx->templ));
-
- return bound;
}
static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 0135415..a462913 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -8400,8 +8400,7 @@ void tcg_x86_init(void)
}
}
-static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu,
- int max_insns)
+static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
CPUX86State *env = cpu->env_ptr;
@@ -8468,8 +8467,6 @@ static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu,
cpu_ptr0 = tcg_temp_new_ptr();
cpu_ptr1 = tcg_temp_new_ptr();
cpu_cc_srcT = tcg_temp_local_new();
-
- return max_insns;
}
static void i386_tr_tb_start(DisasContextBase *db, CPUState *cpu)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 0a0c090..b5a0dd7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7207,8 +7207,7 @@ void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
#endif
}
-static int ppc_tr_init_disas_context(DisasContextBase *dcbase,
- CPUState *cs, int max_insns)
+static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPUPPCState *env = cs->env_ptr;
@@ -7274,7 +7273,7 @@ static int ppc_tr_init_disas_context(DisasContextBase *dcbase,
#endif
bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
- return MIN(max_insns, bound);
+ ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
}
static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [Qemu-devel] [PATCHv2 2/2] target/sh4: convert to TranslatorOps
2018-02-20 2:26 [Qemu-devel] [PATCHv2 0/2] target/sh4: translator loop conversion Emilio G. Cota
2018-02-20 2:26 ` [Qemu-devel] [PATCHv2 1/2] translator: merge max_insns into DisasContextBase Emilio G. Cota
@ 2018-02-20 2:26 ` Emilio G. Cota
1 sibling, 0 replies; 6+ messages in thread
From: Emilio G. Cota @ 2018-02-20 2:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Aurelien Jarno
This was fairly straightforward since it had already been converted
to DisasContextBase; just had to add TARGET_TOO_MANY to the switch
in tb_stop.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
target/sh4/translate.c | 171 +++++++++++++++++++++++++------------------------
1 file changed, 86 insertions(+), 85 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 012156b..58bdfeb 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -2258,126 +2258,127 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State *env, int *pmax_insns)
}
#endif
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
+static void sh4_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
+ DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPUSH4State *env = cs->env_ptr;
- DisasContext ctx;
- target_ulong pc_start;
- int num_insns;
- int max_insns;
-
- pc_start = tb->pc;
- ctx.base.pc_next = pc_start;
- ctx.tbflags = (uint32_t)tb->flags;
- ctx.envflags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
- ctx.base.is_jmp = DISAS_NEXT;
- ctx.memidx = (ctx.tbflags & (1u << SR_MD)) == 0 ? 1 : 0;
+ int bound;
+
+ ctx->tbflags = (uint32_t)ctx->base.tb->flags;
+ ctx->envflags = ctx->base.tb->flags & TB_FLAG_ENVFLAGS_MASK;
+ ctx->memidx = (ctx->tbflags & (1u << SR_MD)) == 0 ? 1 : 0;
/* We don't know if the delayed pc came from a dynamic or static branch,
so assume it is a dynamic branch. */
- ctx.delayed_pc = -1; /* use delayed pc from env pointer */
- ctx.base.tb = tb;
- ctx.base.singlestep_enabled = cs->singlestep_enabled;
- ctx.features = env->features;
- ctx.has_movcal = (ctx.tbflags & TB_FLAG_PENDING_MOVCA);
- ctx.gbank = ((ctx.tbflags & (1 << SR_MD)) &&
- (ctx.tbflags & (1 << SR_RB))) * 0x10;
- ctx.fbank = ctx.tbflags & FPSCR_FR ? 0x10 : 0;
-
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
- if (max_insns == 0) {
- max_insns = CF_COUNT_MASK;
- }
- max_insns = MIN(max_insns, TCG_MAX_INSNS);
+ ctx->delayed_pc = -1; /* use delayed pc from env pointer */
+ ctx->features = env->features;
+ ctx->has_movcal = (ctx->tbflags & TB_FLAG_PENDING_MOVCA);
+ ctx->gbank = ((ctx->tbflags & (1 << SR_MD)) &&
+ (ctx->tbflags & (1 << SR_RB))) * 0x10;
+ ctx->fbank = ctx->tbflags & FPSCR_FR ? 0x10 : 0;
/* Since the ISA is fixed-width, we can bound by the number
of instructions remaining on the page. */
- num_insns = -(ctx.base.pc_next | TARGET_PAGE_MASK) / 2;
- max_insns = MIN(max_insns, num_insns);
-
- /* Single stepping means just that. */
- if (ctx.base.singlestep_enabled || singlestep) {
- max_insns = 1;
- }
-
- gen_tb_start(tb);
- num_insns = 0;
+ bound = -(ctx->base.pc_next | TARGET_PAGE_MASK) / 2;
+ ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
+}
+static void sh4_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
+{
#ifdef CONFIG_USER_ONLY
- if (ctx.tbflags & GUSA_MASK) {
- num_insns = decode_gusa(&ctx, env, &max_insns);
+ DisasContext *ctx = container_of(dcbase, DisasContext, base);
+ CPUSH4State *env = cs->env_ptr;
+
+ if (ctx->tbflags & GUSA_MASK) {
+ ctx->base.num_insns = decode_gusa(ctx, env, &ctx->base.max_insns);
}
#endif
+}
- while (ctx.base.is_jmp == DISAS_NEXT
- && num_insns < max_insns
- && !tcg_op_buf_full()) {
- tcg_gen_insn_start(ctx.base.pc_next, ctx.envflags);
- num_insns++;
+static void sh4_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *ctx = container_of(dcbase, DisasContext, base);
- if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) {
- /* We have hit a breakpoint - make sure PC is up-to-date */
- gen_save_cpu_state(&ctx, true);
- gen_helper_debug(cpu_env);
- ctx.base.is_jmp = DISAS_NORETURN;
- /* The address covered by the breakpoint must be included in
- [tb->pc, tb->pc + tb->size) in order to for it to be
- properly cleared -- thus we increment the PC here so that
- the logic setting tb->size below does the right thing. */
- ctx.base.pc_next += 2;
- break;
- }
+ tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags);
+}
- if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
- gen_io_start();
- }
+static bool sh4_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
+ const CPUBreakpoint *bp)
+{
+ DisasContext *ctx = container_of(dcbase, DisasContext, base);
- ctx.opcode = cpu_lduw_code(env, ctx.base.pc_next);
- decode_opc(&ctx);
- ctx.base.pc_next += 2;
- }
- if (tb_cflags(tb) & CF_LAST_IO) {
- gen_io_end();
- }
+ /* We have hit a breakpoint - make sure PC is up-to-date */
+ gen_save_cpu_state(ctx, true);
+ gen_helper_debug(cpu_env);
+ ctx->base.is_jmp = DISAS_NORETURN;
+ /* The address covered by the breakpoint must be included in
+ [tb->pc, tb->pc + tb->size) in order to for it to be
+ properly cleared -- thus we increment the PC here so that
+ the logic setting tb->size below does the right thing. */
+ ctx->base.pc_next += 2;
+ return true;
+}
+
+static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
+{
+ CPUSH4State *env = cs->env_ptr;
+ DisasContext *ctx = container_of(dcbase, DisasContext, base);
- if (ctx.tbflags & GUSA_EXCLUSIVE) {
+ ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
+ decode_opc(ctx);
+ ctx->base.pc_next += 2;
+}
+
+static void sh4_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *ctx = container_of(dcbase, DisasContext, base);
+
+ if (ctx->tbflags & GUSA_EXCLUSIVE) {
/* Ending the region of exclusivity. Clear the bits. */
- ctx.envflags &= ~GUSA_MASK;
+ ctx->envflags &= ~GUSA_MASK;
}
- switch (ctx.base.is_jmp) {
+ switch (ctx->base.is_jmp) {
case DISAS_STOP:
- gen_save_cpu_state(&ctx, true);
- if (ctx.base.singlestep_enabled) {
+ gen_save_cpu_state(ctx, true);
+ if (ctx->base.singlestep_enabled) {
gen_helper_debug(cpu_env);
} else {
tcg_gen_exit_tb(0);
}
break;
case DISAS_NEXT:
- gen_save_cpu_state(&ctx, false);
- gen_goto_tb(&ctx, 0, ctx.base.pc_next);
+ case DISAS_TOO_MANY:
+ gen_save_cpu_state(ctx, false);
+ gen_goto_tb(ctx, 0, ctx->base.pc_next);
break;
case DISAS_NORETURN:
break;
default:
g_assert_not_reached();
}
+}
- gen_tb_end(tb, num_insns);
+static void sh4_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
+{
+ qemu_log("IN:\n"); /* , lookup_symbol(dcbase->pc_first)); */
+ log_target_disas(cs, dcbase->pc_first, dcbase->tb->size);
+}
- tb->size = ctx.base.pc_next - pc_start;
- tb->icount = num_insns;
+static const TranslatorOps sh4_tr_ops = {
+ .init_disas_context = sh4_tr_init_disas_context,
+ .tb_start = sh4_tr_tb_start,
+ .insn_start = sh4_tr_insn_start,
+ .breakpoint_check = sh4_tr_breakpoint_check,
+ .translate_insn = sh4_tr_translate_insn,
+ .tb_stop = sh4_tr_tb_stop,
+ .disas_log = sh4_tr_disas_log,
+};
+
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
+{
+ DisasContext ctx;
-#ifdef DEBUG_DISAS
- if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
- && qemu_log_in_addr_range(pc_start)) {
- qemu_log_lock();
- qemu_log("IN:\n"); /* , lookup_symbol(pc_start)); */
- log_target_disas(cs, pc_start, ctx.base.pc_next - pc_start);
- qemu_log("\n");
- qemu_log_unlock();
- }
-#endif
+ translator_loop(&sh4_tr_ops, &ctx.base, cs, tb);
}
void restore_state_to_opc(CPUSH4State *env, TranslationBlock *tb,
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread