From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49316) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eqR7T-0006GK-Pq for qemu-devel@nongnu.org; Mon, 26 Feb 2018 17:19:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eqR7S-00053O-KV for qemu-devel@nongnu.org; Mon, 26 Feb 2018 17:19:39 -0500 Received: from mail-pl0-x244.google.com ([2607:f8b0:400e:c01::244]:43214) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eqR7S-00051c-Ef for qemu-devel@nongnu.org; Mon, 26 Feb 2018 17:19:38 -0500 Received: by mail-pl0-x244.google.com with SMTP id f23so10125806plr.10 for ; Mon, 26 Feb 2018 14:19:38 -0800 (PST) From: Michael Clark Date: Tue, 27 Feb 2018 11:17:44 +1300 Message-Id: <1519683480-33201-8-git-send-email-mjc@sifive.com> In-Reply-To: <1519683480-33201-1-git-send-email-mjc@sifive.com> References: <1519683480-33201-1-git-send-email-mjc@sifive.com> Subject: [Qemu-devel] [PATCH v7 07/23] RISC-V GDB Stub List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann , RISC-V Patches GDB Register read and write routines. Reviewed-by: Richard Henderson Signed-off-by: Michael Clark --- target/riscv/gdbstub.c | 62 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 target/riscv/gdbstub.c diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c new file mode 100644 index 0000000..4f919b6 --- /dev/null +++ b/target/riscv/gdbstub.c @@ -0,0 +1,62 @@ +/* + * RISC-V GDB Server Stub + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "exec/gdbstub.h" +#include "cpu.h" + +int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + + if (n < 32) { + return gdb_get_regl(mem_buf, env->gpr[n]); + } else if (n == 32) { + return gdb_get_regl(mem_buf, env->pc); + } else if (n < 65) { + return gdb_get_reg64(mem_buf, env->fpr[n - 33]); + } else if (n < 4096 + 65) { + return gdb_get_regl(mem_buf, csr_read_helper(env, n - 65)); + } + return 0; +} + +int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + + if (n == 0) { + /* discard writes to x0 */ + return sizeof(target_ulong); + } else if (n < 32) { + env->gpr[n] = ldtul_p(mem_buf); + return sizeof(target_ulong); + } else if (n == 32) { + env->pc = ldtul_p(mem_buf); + return sizeof(target_ulong); + } else if (n < 65) { + env->fpr[n - 33] = ldq_p(mem_buf); /* always 64-bit */ + return sizeof(uint64_t); + } else if (n < 4096 + 65) { + csr_write_helper(env, ldtul_p(mem_buf), n - 65); + } + return 0; +} -- 2.7.0