From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49094) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erRLC-0006AG-7K for qemu-devel@nongnu.org; Thu, 01 Mar 2018 11:45:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1erRLB-0000ku-5X for qemu-devel@nongnu.org; Thu, 01 Mar 2018 11:45:58 -0500 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:52422 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1erRLA-0000kS-W5 for qemu-devel@nongnu.org; Thu, 01 Mar 2018 11:45:57 -0500 Date: Thu, 1 Mar 2018 18:45:55 +0200 From: "Michael S. Tsirkin" Message-ID: <1519922735-29054-4-git-send-email-mst@redhat.com> References: <1519922735-29054-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1519922735-29054-1-git-send-email-mst@redhat.com> Subject: [Qemu-devel] [PULL 03/13] intel-iommu: Accept 64-bit writes to FEADDR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Jan Kiszka , Luis Lloret , Peter Xu , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost From: Jan Kiszka Xen is doing this [1] and currently triggers an abort. [1] http://xenbits.xenproject.org/gitweb/?p=xen.git;a=blob;f=xen/drivers/passthrough/vtd/iommu.c;h=daaed0abbdd06b6ba3d948ea103aadf02651e83c;hb=refs/heads/master#l1108 Reported-by: Luis Lloret Signed-off-by: Jan Kiszka Reviewed-by: Peter Xu Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/intel_iommu.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 2e841cd..fb31de9 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2129,8 +2129,15 @@ static void vtd_mem_write(void *opaque, hwaddr addr, /* Fault Event Address Register, 32-bit */ case DMAR_FEADDR_REG: - assert(size == 4); - vtd_set_long(s, addr, val); + if (size == 4) { + vtd_set_long(s, addr, val); + } else { + /* + * While the register is 32-bit only, some guests (Xen...) write to + * it with 64-bit. + */ + vtd_set_quad(s, addr, val); + } break; /* Fault Event Upper Address Register, 32-bit */ -- MST