From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58345) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erl7b-0006oV-Bz for qemu-devel@nongnu.org; Fri, 02 Mar 2018 08:53:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1erl7a-00022X-Hb for qemu-devel@nongnu.org; Fri, 02 Mar 2018 08:53:15 -0500 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:40526) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1erl7a-00022J-C4 for qemu-devel@nongnu.org; Fri, 02 Mar 2018 08:53:14 -0500 Received: by mail-pg0-x243.google.com with SMTP id g2so3803629pgn.7 for ; Fri, 02 Mar 2018 05:53:14 -0800 (PST) From: Michael Clark Date: Sat, 3 Mar 2018 02:51:30 +1300 Message-Id: <1519998711-73430-3-git-send-email-mjc@sifive.com> In-Reply-To: <1519998711-73430-1-git-send-email-mjc@sifive.com> References: <1519998711-73430-1-git-send-email-mjc@sifive.com> Subject: [Qemu-devel] [PATCH v8 02/23] RISC-V ELF Machine Definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann , RISC-V Patches Define RISC-V ELF machine EM_RISCV 243 Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Sagar Karandikar Signed-off-by: Michael Clark --- include/elf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/elf.h b/include/elf.h index 943ee21..c0dc9bb 100644 --- a/include/elf.h +++ b/include/elf.h @@ -119,6 +119,8 @@ typedef int64_t Elf64_Sxword; #define EM_UNICORE32 110 /* UniCore32 */ +#define EM_RISCV 243 /* RISC-V */ + /* * This is an interim value that we will use until the committee comes * up with a final number. -- 2.7.0