From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Subject: Re: [PATCH v4 029/163] tcg: Convert sub to TCGOutOpSubtract
Date: Tue, 15 Apr 2025 14:00:07 -0700 [thread overview]
Message-ID: <151ac78f-dd97-454a-95ce-3cf761c035d9@linaro.org> (raw)
In-Reply-To: <20250415192515.232910-30-richard.henderson@linaro.org>
On 4/15/25 12:23, Richard Henderson wrote:
> Create a special subclass for sub, because two backends can
> support "subtract from immediate". Drop all backend support
> for an immediate as the second operand, as we transform sub
> to add during optimize.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/mips/tcg-target-con-set.h | 1 -
> tcg/ppc/tcg-target-con-set.h | 3 +-
> tcg/riscv/tcg-target-con-set.h | 1 -
> tcg/riscv/tcg-target-con-str.h | 1 -
> tcg/tcg.c | 30 ++++++++++++++++--
> tcg/aarch64/tcg-target.c.inc | 24 +++++++--------
> tcg/arm/tcg-target.c.inc | 29 +++++++++++-------
> tcg/i386/tcg-target.c.inc | 23 +++++++-------
> tcg/loongarch64/tcg-target.c.inc | 32 +++++++++-----------
> tcg/mips/tcg-target.c.inc | 31 ++++++++-----------
> tcg/ppc/tcg-target.c.inc | 52 +++++++++++---------------------
> tcg/riscv/tcg-target.c.inc | 45 +++++++++------------------
> tcg/s390x/tcg-target.c.inc | 41 +++++++++++--------------
> tcg/sparc64/tcg-target.c.inc | 16 +++++++---
> tcg/tci/tcg-target.c.inc | 14 +++++++--
> 15 files changed, 169 insertions(+), 174 deletions(-)
>
> diff --git a/tcg/mips/tcg-target-con-set.h b/tcg/mips/tcg-target-con-set.h
> index 06ab04cc4d..248bc95d9b 100644
> --- a/tcg/mips/tcg-target-con-set.h
> +++ b/tcg/mips/tcg-target-con-set.h
> @@ -24,7 +24,6 @@ C_O1_I2(r, r, rI)
> C_O1_I2(r, r, rIK)
> C_O1_I2(r, r, rJ)
> C_O1_I2(r, r, rzW)
> -C_O1_I2(r, rz, rN)
> C_O1_I2(r, rz, rz)
> C_O1_I4(r, rz, rz, rz, 0)
> C_O1_I4(r, rz, rz, rz, rz)
> diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h
> index 453abde6c1..77a1038d51 100644
> --- a/tcg/ppc/tcg-target-con-set.h
> +++ b/tcg/ppc/tcg-target-con-set.h
> @@ -22,8 +22,7 @@ C_O1_I1(v, r)
> C_O1_I1(v, v)
> C_O1_I1(v, vr)
> C_O1_I2(r, 0, rZ)
> -C_O1_I2(r, rI, ri)
> -C_O1_I2(r, rI, rT)
> +C_O1_I2(r, rI, r)
> C_O1_I2(r, r, r)
> C_O1_I2(r, r, ri)
> C_O1_I2(r, r, rC)
> diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h
> index 21f8833b3b..f3a6f7a7ed 100644
> --- a/tcg/riscv/tcg-target-con-set.h
> +++ b/tcg/riscv/tcg-target-con-set.h
> @@ -16,7 +16,6 @@ C_O1_I1(r, r)
> C_O1_I2(r, r, r)
> C_O1_I2(r, r, ri)
> C_O1_I2(r, r, rI)
> -C_O1_I2(r, rz, rN)
> C_O1_I2(r, rz, rz)
> C_N1_I2(r, r, rM)
> C_O1_I4(r, r, rI, rM, rM)
> diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h
> index 1956f75f9a..c04e15ddfa 100644
> --- a/tcg/riscv/tcg-target-con-str.h
> +++ b/tcg/riscv/tcg-target-con-str.h
> @@ -18,5 +18,4 @@ REGS('v', ALL_VECTOR_REGS)
> CONST('I', TCG_CT_CONST_S12)
> CONST('K', TCG_CT_CONST_S5)
> CONST('L', TCG_CT_CONST_CMP_VI)
> -CONST('N', TCG_CT_CONST_N12)
> CONST('M', TCG_CT_CONST_M12)
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index e70877244e..fd7d7bdd2d 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -986,6 +986,14 @@ typedef struct TCGOutOpBinary {
> TCGReg a0, TCGReg a1, tcg_target_long a2);
> } TCGOutOpBinary;
>
> +typedef struct TCGOutOpSubtract {
> + TCGOutOp base;
> + void (*out_rrr)(TCGContext *s, TCGType type,
> + TCGReg a0, TCGReg a1, TCGReg a2);
> + void (*out_rir)(TCGContext *s, TCGType type,
> + TCGReg a0, tcg_target_long a1, TCGReg a2);
> +} TCGOutOpSubtract;
> +
> #include "tcg-target.c.inc"
>
> #ifndef CONFIG_TCG_INTERPRETER
> @@ -1012,6 +1020,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
> OUTOP(INDEX_op_nor, TCGOutOpBinary, outop_nor),
> OUTOP(INDEX_op_or, TCGOutOpBinary, outop_or),
> OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc),
> + OUTOP(INDEX_op_sub_i32, TCGOutOpSubtract, outop_sub),
> + OUTOP(INDEX_op_sub_i64, TCGOutOpSubtract, outop_sub),
> OUTOP(INDEX_op_xor, TCGOutOpBinary, outop_xor),
> };
>
> @@ -2231,7 +2241,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_st8_i32:
> case INDEX_op_st16_i32:
> case INDEX_op_st_i32:
> - case INDEX_op_sub_i32:
> case INDEX_op_neg_i32:
> case INDEX_op_mul_i32:
> case INDEX_op_shl_i32:
> @@ -2301,7 +2310,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_st16_i64:
> case INDEX_op_st32_i64:
> case INDEX_op_st_i64:
> - case INDEX_op_sub_i64:
> case INDEX_op_neg_i64:
> case INDEX_op_mul_i64:
> case INDEX_op_shl_i64:
> @@ -5446,6 +5454,24 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
> }
> break;
>
> + case INDEX_op_sub_i32:
> + case INDEX_op_sub_i64:
> + {
> + const TCGOutOpSubtract *out = &outop_sub;
> +
> + /*
> + * Constants should never appear in the second source operand.
> + * These are folded to add with negative constant.
> + */
> + tcg_debug_assert(!const_args[2]);
> + if (const_args[1]) {
> + out->out_rir(s, type, new_args[0], new_args[1], new_args[2]);
> + } else {
> + out->out_rrr(s, type, new_args[0], new_args[1], new_args[2]);
> + }
> + }
> + break;
> +
> default:
> if (def->flags & TCG_OPF_VECTOR) {
> tcg_out_vec_op(s, op->opc, type - TCG_TYPE_V64,
> diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
> index 30cad937b7..dfe67c1261 100644
> --- a/tcg/aarch64/tcg-target.c.inc
> +++ b/tcg/aarch64/tcg-target.c.inc
> @@ -2205,6 +2205,17 @@ static const TCGOutOpBinary outop_orc = {
> .out_rrr = tgen_orc,
> };
>
> +static void tgen_sub(TCGContext *s, TCGType type,
> + TCGReg a0, TCGReg a1, TCGReg a2)
> +{
> + tcg_out_insn(s, 3502, SUB, type, a0, a1, a2);
> +}
> +
> +static const TCGOutOpSubtract outop_sub = {
> + .base.static_constraint = C_O1_I2(r, r, r),
> + .out_rrr = tgen_sub,
> +};
> +
> static void tgen_xor(TCGContext *s, TCGType type,
> TCGReg a0, TCGReg a1, TCGReg a2)
> {
> @@ -2290,15 +2301,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
> tcg_out_ldst(s, I3312_STRX, a0, a1, a2, 3);
> break;
>
> - case INDEX_op_sub_i32:
> - case INDEX_op_sub_i64:
> - if (c2) {
> - tgen_addi(s, ext, a0, a1, -a2);
> - } else {
> - tcg_out_insn(s, 3502, SUB, ext, a0, a1, a2);
> - }
> - break;
> -
> case INDEX_op_neg_i64:
> case INDEX_op_neg_i32:
> tcg_out_insn(s, 3502, SUB, ext, a0, TCG_REG_XZR, a1);
> @@ -3014,10 +3016,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_st_i64:
> return C_O0_I2(rz, r);
>
> - case INDEX_op_sub_i32:
> - case INDEX_op_sub_i64:
> - return C_O1_I2(r, r, rA);
> -
> case INDEX_op_setcond_i32:
> case INDEX_op_setcond_i64:
> case INDEX_op_negsetcond_i32:
> diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
> index 47c09ff2b1..13b78f0ada 100644
> --- a/tcg/arm/tcg-target.c.inc
> +++ b/tcg/arm/tcg-target.c.inc
> @@ -1915,6 +1915,24 @@ static const TCGOutOpBinary outop_orc = {
> .base.static_constraint = C_NotImplemented,
> };
>
> +static void tgen_sub(TCGContext *s, TCGType type,
> + TCGReg a0, TCGReg a1, TCGReg a2)
> +{
> + tcg_out_dat_reg(s, COND_AL, ARITH_SUB, a0, a1, a2, SHIFT_IMM_LSL(0));
> +}
> +
> +static void tgen_subfi(TCGContext *s, TCGType type,
> + TCGReg a0, tcg_target_long a1, TCGReg a2)
> +{
> + tcg_out_dat_imm(s, COND_AL, ARITH_RSB, a0, a2, encode_imm_nofail(a1));
> +}
> +
> +static const TCGOutOpSubtract outop_sub = {
> + .base.static_constraint = C_O1_I2(r, rI, r),
> + .out_rrr = tgen_sub,
> + .out_rir = tgen_subfi,
> +};
> +
> static void tgen_xor(TCGContext *s, TCGType type,
> TCGReg a0, TCGReg a1, TCGReg a2)
> {
> @@ -1982,15 +2000,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[c], ARITH_MOV,
> ARITH_MVN, args[0], 0, args[3], const_args[3]);
> break;
> - case INDEX_op_sub_i32:
> - if (const_args[1]) {
> - tcg_out_dat_imm(s, COND_AL, ARITH_RSB,
> - args[0], args[2], encode_imm_nofail(args[1]));
> - } else {
> - tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD,
> - args[0], args[1], args[2], const_args[2]);
> - }
> - break;
> case INDEX_op_add2_i32:
> a0 = args[0], a1 = args[1], a2 = args[2];
> a3 = args[3], a4 = args[4], a5 = args[5];
> @@ -2233,8 +2242,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_setcond_i32:
> case INDEX_op_negsetcond_i32:
> return C_O1_I2(r, r, rIN);
> - case INDEX_op_sub_i32:
> - return C_O1_I2(r, rI, r);
>
> case INDEX_op_clz_i32:
> case INDEX_op_ctz_i32:
> diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
> index 9185f6879c..104f1b010a 100644
> --- a/tcg/i386/tcg-target.c.inc
> +++ b/tcg/i386/tcg-target.c.inc
> @@ -2669,6 +2669,18 @@ static const TCGOutOpBinary outop_orc = {
> .base.static_constraint = C_NotImplemented,
> };
>
> +static void tgen_sub(TCGContext *s, TCGType type,
> + TCGReg a0, TCGReg a1, TCGReg a2)
> +{
> + int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW;
> + tgen_arithr(s, ARITH_SUB + rexw, a0, a2);
> +}
> +
> +static const TCGOutOpSubtract outop_sub = {
> + .base.static_constraint = C_O1_I2(r, 0, r),
> + .out_rrr = tgen_sub,
> +};
> +
> static void tgen_xor(TCGContext *s, TCGType type,
> TCGReg a0, TCGReg a1, TCGReg a2)
> {
> @@ -2770,15 +2782,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> }
> break;
>
> - OP_32_64(sub):
> - c = ARITH_SUB;
> - if (const_a2) {
> - tgen_arithi(s, c + rexw, a0, a2, 0);
> - } else {
> - tgen_arithr(s, c + rexw, a0, a2);
> - }
> - break;
> -
> OP_32_64(mul):
> if (const_a2) {
> int32_t val;
> @@ -3689,8 +3692,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_st_i64:
> return C_O0_I2(re, r);
>
> - case INDEX_op_sub_i32:
> - case INDEX_op_sub_i64:
> case INDEX_op_mul_i32:
> case INDEX_op_mul_i64:
> return C_O1_I2(r, 0, re);
> diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
> index 59e7de76fa..9d71ec2a86 100644
> --- a/tcg/loongarch64/tcg-target.c.inc
> +++ b/tcg/loongarch64/tcg-target.c.inc
> @@ -1364,6 +1364,21 @@ static const TCGOutOpBinary outop_orc = {
> .out_rrr = tgen_orc,
> };
>
> +static void tgen_sub(TCGContext *s, TCGType type,
> + TCGReg a0, TCGReg a1, TCGReg a2)
> +{
> + if (type == TCG_TYPE_I32) {
> + tcg_out_opc_sub_w(s, a0, a1, a2);
> + } else {
> + tcg_out_opc_sub_d(s, a0, a1, a2);
> + }
> +}
> +
> +static const TCGOutOpSubtract outop_sub = {
> + .base.static_constraint = C_O1_I2(r, r, r),
> + .out_rrr = tgen_sub,
> +};
> +
> static void tgen_xor(TCGContext *s, TCGType type,
> TCGReg a0, TCGReg a1, TCGReg a2)
> {
> @@ -1584,21 +1599,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> }
> break;
>
> - case INDEX_op_sub_i32:
> - if (c2) {
> - tcg_out_addi(s, TCG_TYPE_I32, a0, a1, -a2);
> - } else {
> - tcg_out_opc_sub_w(s, a0, a1, a2);
> - }
> - break;
> - case INDEX_op_sub_i64:
> - if (c2) {
> - tcg_out_addi(s, TCG_TYPE_I64, a0, a1, -a2);
> - } else {
> - tcg_out_opc_sub_d(s, a0, a1, a2);
> - }
> - break;
> -
> case INDEX_op_neg_i32:
> tcg_out_opc_sub_w(s, a0, TCG_REG_ZERO, a1);
> break;
> @@ -2318,10 +2318,8 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> /* Must deposit into the same register as input */
> return C_O1_I2(r, 0, rz);
>
> - case INDEX_op_sub_i32:
> case INDEX_op_setcond_i32:
> return C_O1_I2(r, rz, ri);
> - case INDEX_op_sub_i64:
> case INDEX_op_setcond_i64:
> return C_O1_I2(r, rz, rJ);
>
> diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
> index bfe329b3ef..15c5661fb8 100644
> --- a/tcg/mips/tcg-target.c.inc
> +++ b/tcg/mips/tcg-target.c.inc
> @@ -1753,6 +1753,18 @@ static const TCGOutOpBinary outop_orc = {
> .base.static_constraint = C_NotImplemented,
> };
>
> +static void tgen_sub(TCGContext *s, TCGType type,
> + TCGReg a0, TCGReg a1, TCGReg a2)
> +{
> + MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SUBU : OPC_DSUBU;
> + tcg_out_opc_reg(s, insn, a0, a1, a2);
> +}
> +
> +static const TCGOutOpSubtract outop_sub = {
> + .base.static_constraint = C_O1_I2(r, r, r),
> + .out_rrr = tgen_sub,
> +};
> +
> static void tgen_xor(TCGContext *s, TCGType type,
> TCGReg a0, TCGReg a1, TCGReg a2)
> {
> @@ -1844,22 +1856,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out_ldst(s, i1, a0, a1, a2);
> break;
>
> - do_binaryv:
> - tcg_out_opc_reg(s, i1, a0, a1, a2);
> - break;
> -
> - case INDEX_op_sub_i32:
> - i1 = OPC_SUBU, i2 = OPC_ADDIU;
> - goto do_subtract;
> - case INDEX_op_sub_i64:
> - i1 = OPC_DSUBU, i2 = OPC_DADDIU;
> - do_subtract:
> - if (c2) {
> - tcg_out_opc_imm(s, i2, a0, a1, -a2);
> - break;
> - }
> - goto do_binaryv;
> -
> case INDEX_op_mul_i32:
> if (use_mips32_instructions) {
> tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
> @@ -2234,9 +2230,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_st_i64:
> return C_O0_I2(rz, r);
>
> - case INDEX_op_sub_i32:
> - case INDEX_op_sub_i64:
> - return C_O1_I2(r, rz, rN);
> case INDEX_op_mul_i32:
> case INDEX_op_mulsh_i32:
> case INDEX_op_muluh_i32:
> diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
> index c3366e4316..bfbfdc2dfa 100644
> --- a/tcg/ppc/tcg-target.c.inc
> +++ b/tcg/ppc/tcg-target.c.inc
> @@ -3016,6 +3016,24 @@ static const TCGOutOpBinary outop_orc = {
> .out_rrr = tgen_orc,
> };
>
> +static void tgen_sub(TCGContext *s, TCGType type,
> + TCGReg a0, TCGReg a1, TCGReg a2)
> +{
> + tcg_out32(s, SUBF | TAB(a0, a2, a1));
> +}
> +
> +static void tgen_subfi(TCGContext *s, TCGType type,
> + TCGReg a0, tcg_target_long a1, TCGReg a2)
> +{
> + tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
> +}
> +
> +static const TCGOutOpSubtract outop_sub = {
> + .base.static_constraint = C_O1_I2(r, rI, r),
> + .out_rrr = tgen_sub,
> + .out_rir = tgen_subfi,
> +};
> +
> static void tgen_xor(TCGContext *s, TCGType type,
> TCGReg a0, TCGReg a1, TCGReg a2)
> {
> @@ -3104,21 +3122,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
> break;
>
> - case INDEX_op_sub_i32:
> - a0 = args[0], a1 = args[1], a2 = args[2];
> - if (const_args[1]) {
> - if (const_args[2]) {
> - tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
> - } else {
> - tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
> - }
> - } else if (const_args[2]) {
> - tgen_addi(s, type, a0, a1, (int32_t)-a2);
> - } else {
> - tcg_out32(s, SUBF | TAB(a0, a2, a1));
> - }
> - break;
> -
> case INDEX_op_clz_i32:
> tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, args[0], args[1],
> args[2], const_args[2]);
> @@ -3231,21 +3234,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
> break;
>
> - case INDEX_op_sub_i64:
> - a0 = args[0], a1 = args[1], a2 = args[2];
> - if (const_args[1]) {
> - if (const_args[2]) {
> - tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
> - } else {
> - tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
> - }
> - } else if (const_args[2]) {
> - tgen_addi(s, type, a0, a1, -a2);
> - } else {
> - tcg_out32(s, SUBF | TAB(a0, a2, a1));
> - }
> - break;
> -
> case INDEX_op_shl_i64:
> if (const_args[2]) {
> /* Limit immediate shift count lest we create an illegal insn. */
> @@ -4195,10 +4183,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_muluh_i64:
> return C_O1_I2(r, r, r);
>
> - case INDEX_op_sub_i32:
> - return C_O1_I2(r, rI, ri);
> - case INDEX_op_sub_i64:
> - return C_O1_I2(r, rI, rT);
> case INDEX_op_clz_i32:
> case INDEX_op_ctz_i32:
> case INDEX_op_clz_i64:
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 887f20d4cb..54da432ab1 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -113,10 +113,9 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
> }
>
> #define TCG_CT_CONST_S12 0x100
> -#define TCG_CT_CONST_N12 0x200
> -#define TCG_CT_CONST_M12 0x400
> -#define TCG_CT_CONST_S5 0x800
> -#define TCG_CT_CONST_CMP_VI 0x1000
> +#define TCG_CT_CONST_M12 0x200
> +#define TCG_CT_CONST_S5 0x400
> +#define TCG_CT_CONST_CMP_VI 0x800
>
> #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
> #define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32)
> @@ -400,13 +399,6 @@ static bool tcg_target_const_match(int64_t val, int ct,
> if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) {
> return 1;
> }
> - /*
> - * Sign extended from 12 bits, negated: [-0x7ff, 0x800].
> - * Used for subtraction, where a constant must be handled by ADDI.
> - */
> - if ((ct & TCG_CT_CONST_N12) && val >= -0x7ff && val <= 0x800) {
> - return 1;
> - }
> /*
> * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff].
> * Used by addsub2 and movcond, which may need the negative value,
> @@ -2055,6 +2047,18 @@ static const TCGOutOpBinary outop_orc = {
> .out_rrr = tgen_orc,
> };
>
> +static void tgen_sub(TCGContext *s, TCGType type,
> + TCGReg a0, TCGReg a1, TCGReg a2)
> +{
> + RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_SUBW : OPC_SUB;
> + tcg_out_opc_reg(s, insn, a0, a1, a2);
> +}
> +
> +static const TCGOutOpSubtract outop_sub = {
> + .base.static_constraint = C_O1_I2(r, r, r),
> + .out_rrr = tgen_sub,
> +};
> +
> static void tgen_xor(TCGContext *s, TCGType type,
> TCGReg a0, TCGReg a1, TCGReg a2)
> {
> @@ -2136,21 +2140,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out_ldst(s, OPC_SD, a0, a1, a2);
> break;
>
> - case INDEX_op_sub_i32:
> - if (c2) {
> - tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, -a2);
> - } else {
> - tcg_out_opc_reg(s, OPC_SUBW, a0, a1, a2);
> - }
> - break;
> - case INDEX_op_sub_i64:
> - if (c2) {
> - tcg_out_opc_imm(s, OPC_ADDI, a0, a1, -a2);
> - } else {
> - tcg_out_opc_reg(s, OPC_SUB, a0, a1, a2);
> - }
> - break;
> -
> case INDEX_op_not_i32:
> case INDEX_op_not_i64:
> tcg_out_opc_imm(s, OPC_XORI, a0, a1, -1);
> @@ -2713,10 +2702,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_negsetcond_i64:
> return C_O1_I2(r, r, rI);
>
> - case INDEX_op_sub_i32:
> - case INDEX_op_sub_i64:
> - return C_O1_I2(r, rz, rN);
> -
> case INDEX_op_mul_i32:
> case INDEX_op_mulsh_i32:
> case INDEX_op_muluh_i32:
> diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
> index 29570d3be1..662984f733 100644
> --- a/tcg/s390x/tcg-target.c.inc
> +++ b/tcg/s390x/tcg-target.c.inc
> @@ -2331,6 +2331,23 @@ static const TCGOutOpBinary outop_orc = {
> .out_rrr = tgen_orc,
> };
>
> +static void tgen_sub(TCGContext *s, TCGType type,
> + TCGReg a0, TCGReg a1, TCGReg a2)
> +{
> + if (type != TCG_TYPE_I32) {
> + tcg_out_insn(s, RRFa, SGRK, a0, a1, a2);
> + } else if (a0 == a1) {
> + tcg_out_insn(s, RR, SR, a0, a2);
> + } else {
> + tcg_out_insn(s, RRFa, SRK, a0, a1, a2);
> + }
> +}
> +
> +static const TCGOutOpSubtract outop_sub = {
> + .base.static_constraint = C_O1_I2(r, r, r),
> + .out_rrr = tgen_sub,
> +};
> +
> static void tgen_xor(TCGContext *s, TCGType type,
> TCGReg a0, TCGReg a1, TCGReg a2)
> {
> @@ -2413,17 +2430,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
> break;
>
> - case INDEX_op_sub_i32:
> - a0 = args[0], a1 = args[1], a2 = args[2];
> - if (const_args[2]) {
> - tgen_addi(s, type, a0, a1, (int32_t)-a2);
> - } else if (a0 == a1) {
> - tcg_out_insn(s, RR, SR, a0, a2);
> - } else {
> - tcg_out_insn(s, RRFa, SRK, a0, a1, a2);
> - }
> - break;
> -
> case INDEX_op_neg_i32:
> tcg_out_insn(s, RR, LCR, args[0], args[1]);
> break;
> @@ -2618,15 +2624,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]);
> break;
>
> - case INDEX_op_sub_i64:
> - a0 = args[0], a1 = args[1], a2 = args[2];
> - if (const_args[2]) {
> - tgen_addi(s, type, a0, a1, -a2);
> - } else {
> - tcg_out_insn(s, RRFa, SGRK, a0, a1, a2);
> - }
> - break;
> -
> case INDEX_op_neg_i64:
> tcg_out_insn(s, RRE, LCGR, args[0], args[1]);
> break;
> @@ -3302,10 +3299,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_clz_i64:
> return C_O1_I2(r, r, rI);
>
> - case INDEX_op_sub_i32:
> - case INDEX_op_sub_i64:
> - return C_O1_I2(r, r, ri);
> -
> case INDEX_op_mul_i32:
> return (HAVE_FACILITY(MISC_INSN_EXT2)
> ? C_O1_I2(r, r, ri)
> diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
> index 1ebff04af4..04b2b3b195 100644
> --- a/tcg/sparc64/tcg-target.c.inc
> +++ b/tcg/sparc64/tcg-target.c.inc
> @@ -1374,6 +1374,17 @@ static const TCGOutOpBinary outop_orc = {
> .out_rrr = tgen_orc,
> };
>
> +static void tgen_sub(TCGContext *s, TCGType type,
> + TCGReg a0, TCGReg a1, TCGReg a2)
> +{
> + tcg_out_arith(s, a0, a1, a2, ARITH_SUB);
> +}
> +
> +static const TCGOutOpSubtract outop_sub = {
> + .base.static_constraint = C_O1_I2(r, r, r),
> + .out_rrr = tgen_sub,
> +};
> +
> static void tgen_xor(TCGContext *s, TCGType type,
> TCGReg a0, TCGReg a1, TCGReg a2)
> {
> @@ -1446,9 +1457,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> case INDEX_op_st32_i64:
> tcg_out_ldst(s, a0, a1, a2, STW);
> break;
> - OP_32_64(sub):
> - c = ARITH_SUB;
> - goto gen_arith;
> case INDEX_op_shl_i32:
> c = SHIFT_SLL;
> do_shift32:
> @@ -1660,8 +1668,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_div_i64:
> case INDEX_op_divu_i32:
> case INDEX_op_divu_i64:
> - case INDEX_op_sub_i32:
> - case INDEX_op_sub_i64:
> case INDEX_op_shl_i32:
> case INDEX_op_shl_i64:
> case INDEX_op_shr_i32:
> diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
> index dec51692f0..353994e83f 100644
> --- a/tcg/tci/tcg-target.c.inc
> +++ b/tcg/tci/tcg-target.c.inc
> @@ -91,8 +91,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_rem_i64:
> case INDEX_op_remu_i32:
> case INDEX_op_remu_i64:
> - case INDEX_op_sub_i32:
> - case INDEX_op_sub_i64:
> case INDEX_op_mul_i32:
> case INDEX_op_mul_i64:
> case INDEX_op_shl_i32:
> @@ -711,6 +709,17 @@ static const TCGOutOpBinary outop_orc = {
> .out_rrr = tgen_orc,
> };
>
> +static void tgen_sub(TCGContext *s, TCGType type,
> + TCGReg a0, TCGReg a1, TCGReg a2)
> +{
> + tcg_out_op_rrr(s, glue(INDEX_op_sub_i,TCG_TARGET_REG_BITS), a0, a1, a2);
> +}
> +
> +static const TCGOutOpSubtract outop_sub = {
> + .base.static_constraint = C_O1_I2(r, r, r),
> + .out_rrr = tgen_sub,
> +};
> +
> static void tgen_xor(TCGContext *s, TCGType type,
> TCGReg a0, TCGReg a1, TCGReg a2)
> {
> @@ -764,7 +773,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out_ldst(s, opc, args[0], args[1], args[2]);
> break;
>
> - CASE_32_64(sub)
> CASE_32_64(mul)
> CASE_32_64(shl)
> CASE_32_64(shr)
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
next prev parent reply other threads:[~2025-04-15 21:01 UTC|newest]
Thread overview: 316+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-15 19:22 [PATCH v4 000/163] tcg: Convert to TCGOutOp structures Richard Henderson
2025-04-15 19:22 ` [PATCH v4 001/163] tcg: Add all_outop[] Richard Henderson
2025-04-15 19:22 ` [PATCH v4 002/163] tcg: Use extract2 for cross-word 64-bit extract on 32-bit host Richard Henderson
2025-04-15 19:22 ` [PATCH v4 003/163] tcg: Remove INDEX_op_ext{8,16,32}* Richard Henderson
2025-04-15 19:22 ` [PATCH v4 004/163] tcg: Merge INDEX_op_mov_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 005/163] tcg: Convert add to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 006/163] tcg: Merge INDEX_op_add_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 007/163] tcg: Convert and to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 008/163] tcg: Merge INDEX_op_and_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 009/163] tcg/optimize: Fold andc with immediate to and Richard Henderson
2025-04-15 19:22 ` [PATCH v4 010/163] tcg/optimize: Emit add r, r, -1 in fold_setcond_tst_pow2 Richard Henderson
2025-04-15 19:22 ` [PATCH v4 011/163] tcg: Convert andc to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 012/163] tcg: Merge INDEX_op_andc_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 013/163] tcg: Convert or to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 014/163] tcg: Merge INDEX_op_or_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 015/163] tcg/optimize: Fold orc with immediate to or Richard Henderson
2025-04-15 19:22 ` [PATCH v4 016/163] tcg: Convert orc to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 017/163] tcg: Merge INDEX_op_orc_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 018/163] tcg: Convert xor to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 019/163] tcg: Merge INDEX_op_xor_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 020/163] tcg/optimize: Fold eqv with immediate to xor Richard Henderson
2025-04-15 19:22 ` [PATCH v4 021/163] tcg: Convert eqv to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 022/163] tcg: Merge INDEX_op_eqv_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 023/163] tcg: Convert nand to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 024/163] tcg: Merge INDEX_op_nand_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 025/163] tcg/loongarch64: Do not accept constant argument to nor Richard Henderson
2025-04-15 19:22 ` [PATCH v4 026/163] tcg: Convert nor to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 027/163] tcg: Merge INDEX_op_nor_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 028/163] tcg/arm: Fix constraints for sub Richard Henderson
2025-04-15 19:23 ` [PATCH v4 029/163] tcg: Convert sub to TCGOutOpSubtract Richard Henderson
2025-04-15 21:00 ` Pierrick Bouvier [this message]
2025-04-15 19:23 ` [PATCH v4 030/163] tcg: Merge INDEX_op_sub_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 031/163] tcg: Convert neg to TCGOutOpUnary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 032/163] tcg: Merge INDEX_op_neg_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 033/163] tcg: Convert not to TCGOutOpUnary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 034/163] tcg: Merge INDEX_op_not_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 035/163] tcg: Convert mul to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 036/163] tcg: Merge INDEX_op_mul_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 037/163] tcg: Convert muluh to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 038/163] tcg: Merge INDEX_op_muluh_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 039/163] tcg: Convert mulsh to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 040/163] tcg: Merge INDEX_op_mulsh_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 041/163] tcg: Convert div to TCGOutOpBinary Richard Henderson
2025-04-15 21:02 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 042/163] tcg: Merge INDEX_op_div_{i32,i64} Richard Henderson
2025-04-15 21:04 ` Pierrick Bouvier
2025-04-22 15:27 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 043/163] tcg: Convert divu to TCGOutOpBinary Richard Henderson
2025-04-15 21:04 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 044/163] tcg: Merge INDEX_op_divu_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 045/163] tcg: Convert div2 to TCGOutOpDivRem Richard Henderson
2025-04-15 19:23 ` [PATCH v4 046/163] tcg: Merge INDEX_op_div2_{i32,i64} Richard Henderson
2025-04-15 21:05 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 047/163] tcg: Convert divu2 to TCGOutOpDivRem Richard Henderson
2025-04-15 21:05 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 048/163] tcg: Merge INDEX_op_divu2_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 049/163] tcg: Convert rem to TCGOutOpBinary Richard Henderson
2025-04-15 21:06 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 050/163] tcg: Merge INDEX_op_rem_{i32,i64} Richard Henderson
2025-04-15 21:06 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 051/163] tcg: Convert remu to TCGOutOpBinary Richard Henderson
2025-04-15 21:07 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 052/163] tcg: Merge INDEX_op_remu_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 053/163] tcg: Convert shl to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 054/163] tcg: Merge INDEX_op_shl_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 055/163] tcg: Convert shr to TCGOutOpBinary Richard Henderson
2025-04-15 21:08 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 056/163] tcg: Merge INDEX_op_shr_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 057/163] tcg: Convert sar to TCGOutOpBinary Richard Henderson
2025-04-15 21:09 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 058/163] tcg: Merge INDEX_op_sar_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 059/163] tcg: Do not require both rotr and rotl from the backend Richard Henderson
2025-04-15 21:10 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 060/163] tcg: Convert rotl, rotr to TCGOutOpBinary Richard Henderson
2025-04-15 21:10 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 061/163] tcg: Merge INDEX_op_rot{l,r}_{i32,i64} Richard Henderson
2025-04-15 21:11 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 062/163] tcg: Convert clz to TCGOutOpBinary Richard Henderson
2025-04-15 21:12 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 063/163] tcg: Merge INDEX_op_clz_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 064/163] tcg: Convert ctz to TCGOutOpBinary Richard Henderson
2025-04-15 21:13 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 065/163] tcg: Merge INDEX_op_ctz_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 066/163] tcg: Convert ctpop to TCGOutOpUnary Richard Henderson
2025-04-15 21:14 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 067/163] tcg: Merge INDEX_op_ctpop_{i32,i64} Richard Henderson
2025-04-15 21:15 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 068/163] tcg: Convert muls2 to TCGOutOpMul2 Richard Henderson
2025-04-15 21:17 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 069/163] tcg: Merge INDEX_op_muls2_{i32,i64} Richard Henderson
2025-04-15 21:17 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 070/163] tcg: Convert mulu2 to TCGOutOpMul2 Richard Henderson
2025-04-15 21:18 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 071/163] tcg: Merge INDEX_op_mulu2_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 072/163] tcg/loongarch64: Support negsetcond Richard Henderson
2025-04-15 21:19 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 073/163] tcg/mips: " Richard Henderson
2025-04-15 21:20 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 074/163] tcg/tci: " Richard Henderson
2025-04-15 21:20 ` Pierrick Bouvier
2025-04-22 15:28 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 075/163] tcg: Remove TCG_TARGET_HAS_negsetcond_{i32,i64} Richard Henderson
2025-04-22 15:35 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 076/163] tcg: Convert setcond, negsetcond to TCGOutOpSetcond Richard Henderson
2025-04-15 21:21 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 077/163] tcg: Merge INDEX_op_{neg}setcond_{i32,i64}` Richard Henderson
2025-04-15 21:22 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 078/163] tcg: Convert brcond to TCGOutOpBrcond Richard Henderson
2025-04-15 21:23 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 079/163] tcg: Merge INDEX_op_brcond_{i32,i64} Richard Henderson
2025-04-15 21:24 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 080/163] tcg: Convert movcond to TCGOutOpMovcond Richard Henderson
2025-04-15 21:25 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 081/163] tcg: Merge INDEX_op_movcond_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 082/163] tcg/ppc: Drop fallback constant loading in tcg_out_cmp Richard Henderson
2025-04-15 21:26 ` Pierrick Bouvier
2025-04-16 14:39 ` Nicholas Piggin
2025-04-16 18:57 ` Richard Henderson
2025-04-15 19:23 ` [PATCH v4 083/163] tcg/arm: Expand arguments to tcg_out_cmp2 Richard Henderson
2025-04-15 21:27 ` Pierrick Bouvier
2025-04-22 15:37 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 084/163] tcg/ppc: " Richard Henderson
2025-04-15 21:27 ` Pierrick Bouvier
2025-04-16 14:43 ` Nicholas Piggin
2025-04-22 15:37 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 085/163] tcg: Convert brcond2_i32 to TCGOutOpBrcond2 Richard Henderson
2025-04-15 21:37 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 086/163] tcg: Convert setcond2_i32 to TCGOutOpSetcond2 Richard Henderson
2025-04-15 21:39 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 087/163] tcg: Convert bswap16 to TCGOutOpBswap Richard Henderson
2025-04-15 21:40 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 088/163] tcg: Merge INDEX_op_bswap16_{i32,i64} Richard Henderson
2025-04-15 21:41 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 089/163] tcg: Convert bswap32 to TCGOutOpBswap Richard Henderson
2025-04-15 21:46 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 090/163] tcg: Merge INDEX_op_bswap32_{i32,i64} Richard Henderson
2025-04-15 21:47 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 091/163] tcg: Convert bswap64 to TCGOutOpUnary Richard Henderson
2025-04-15 21:48 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 092/163] tcg: Rename INDEX_op_bswap64_i64 to INDEX_op_bswap64 Richard Henderson
2025-04-15 21:48 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 093/163] tcg: Convert extract to TCGOutOpExtract Richard Henderson
2025-04-15 21:50 ` Pierrick Bouvier
2025-06-09 13:52 ` Andrea Bolognani
2025-06-26 16:20 ` Andrea Bolognani
2025-06-27 13:16 ` Richard Henderson
2025-06-27 14:29 ` Philippe Mathieu-Daudé
2025-06-30 12:08 ` Andrea Bolognani
2025-04-15 19:24 ` [PATCH v4 094/163] tcg: Merge INDEX_op_extract_{i32,i64} Richard Henderson
2025-04-15 21:51 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 095/163] tcg: Convert sextract to TCGOutOpExtract Richard Henderson
2025-04-15 21:55 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 096/163] tcg: Merge INDEX_op_sextract_{i32,i64} Richard Henderson
2025-04-15 21:55 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 097/163] tcg: Convert ext_i32_i64 to TCGOutOpUnary Richard Henderson
2025-04-15 21:55 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 098/163] tcg: Convert extu_i32_i64 " Richard Henderson
2025-04-15 21:56 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 099/163] tcg: Convert extrl_i64_i32 " Richard Henderson
2025-04-15 21:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 100/163] tcg: Convert extrh_i64_i32 " Richard Henderson
2025-04-15 21:58 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 101/163] tcg: Convert deposit to TCGOutOpDeposit Richard Henderson
2025-04-15 21:59 ` Pierrick Bouvier
2025-08-28 7:37 ` Michael Tokarev
2025-04-15 19:24 ` [PATCH v4 102/163] tcg/aarch64: Improve deposit Richard Henderson
2025-04-15 22:01 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 103/163] tcg: Merge INDEX_op_deposit_{i32,i64} Richard Henderson
2025-04-15 19:24 ` [PATCH v4 104/163] tcg: Convert extract2 to TCGOutOpExtract2 Richard Henderson
2025-04-15 22:01 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 105/163] tcg: Merge INDEX_op_extract2_{i32,i64} Richard Henderson
2025-04-15 22:02 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 106/163] tcg: Expand fallback add2 with 32-bit operations Richard Henderson
2025-04-15 22:03 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 107/163] tcg: Expand fallback sub2 " Richard Henderson
2025-04-15 22:03 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 108/163] tcg: Do not default add2/sub2_i32 for 32-bit hosts Richard Henderson
2025-04-15 22:04 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 109/163] tcg/mips: Drop support for add2/sub2 Richard Henderson
2025-04-15 22:04 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 110/163] tcg/riscv: " Richard Henderson
2025-04-15 22:05 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 111/163] tcg: Move i into each for loop in liveness_pass_1 Richard Henderson
2025-04-15 22:07 ` Pierrick Bouvier
2025-04-16 6:37 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 112/163] tcg: Sink def, nb_iargs, nb_oargs loads " Richard Henderson
2025-04-15 22:09 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 113/163] tcg: Add add/sub with carry opcodes and infrastructure Richard Henderson
2025-04-16 19:01 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 114/163] tcg: Add TCGOutOp structures for add/sub carry opcodes Richard Henderson
2025-04-16 18:56 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 115/163] tcg/optimize: Handle add/sub with " Richard Henderson
2025-04-16 19:02 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 116/163] tcg/optimize: With two const operands, prefer 0 in arg1 Richard Henderson
2025-04-16 19:03 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 117/163] tcg: Use add carry opcodes to expand add2 Richard Henderson
2025-04-16 18:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 118/163] tcg: Use sub carry opcodes to expand sub2 Richard Henderson
2025-04-16 18:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 119/163] tcg/i386: Honor carry_live in tcg_out_movi Richard Henderson
2025-04-16 18:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 120/163] tcg/i386: Implement add/sub carry opcodes Richard Henderson
2025-04-16 18:58 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 121/163] tcg/i386: Remove support for add2/sub2 Richard Henderson
2025-04-16 18:58 ` Pierrick Bouvier
2025-04-22 16:13 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 122/163] tcg/i386: Special case addci r, 0, 0 Richard Henderson
2025-04-16 18:59 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 123/163] tcg: Add tcg_gen_addcio_{i32,i64,tl} Richard Henderson
2025-04-16 18:59 ` Pierrick Bouvier
2025-04-22 16:13 ` Philippe Mathieu-Daudé
2025-04-22 16:30 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 124/163] target/arm: Use tcg_gen_addcio_* for ADCS Richard Henderson
2025-04-16 19:00 ` Pierrick Bouvier
2025-04-22 16:15 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 125/163] target/hppa: Use tcg_gen_addcio_i64 Richard Henderson
2025-04-16 19:05 ` Pierrick Bouvier
2025-04-22 16:17 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 126/163] target/microblaze: Use tcg_gen_addcio_i32 Richard Henderson
2025-04-16 19:05 ` Pierrick Bouvier
2025-04-22 16:28 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 127/163] target/openrisc: Use tcg_gen_addcio_* for ADDC Richard Henderson
2025-04-16 19:05 ` Pierrick Bouvier
2025-04-22 16:32 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 128/163] target/ppc: Use tcg_gen_addcio_tl for ADD and SUBF Richard Henderson
2025-04-16 14:08 ` Nicholas Piggin
2025-04-16 19:08 ` Pierrick Bouvier
2025-04-22 16:33 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 129/163] target/s390x: Use tcg_gen_addcio_i64 for op_addc64 Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-22 16:33 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 130/163] target/sh4: Use tcg_gen_addcio_i32 for addc Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-22 16:34 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 131/163] target/sparc: Use tcg_gen_addcio_tl for gen_op_addcc_int Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 132/163] target/tricore: Use tcg_gen_addcio_i32 for gen_addc_CC Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-22 16:38 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 133/163] tcg/aarch64: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:10 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 134/163] tcg/aarch64: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:13 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 135/163] tcg/arm: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:14 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 136/163] tcg/arm: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:14 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 137/163] tcg/ppc: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:14 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 138/163] tcg/ppc: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:15 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 139/163] tcg/s390x: Honor carry_live in tcg_out_movi Richard Henderson
2025-04-16 19:15 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 140/163] tcg/s390: Add TCG_CT_CONST_N32 Richard Henderson
2025-04-16 19:16 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 141/163] tcg/s390x: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:16 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 142/163] tcg/s390x: Use ADD LOGICAL WITH SIGNED IMMEDIATE Richard Henderson
2025-04-16 19:18 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 143/163] tcg/s390x: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:18 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 144/163] tcg/sparc64: Hoist tcg_cond_to_bcond lookup out of tcg_out_movcc Richard Henderson
2025-04-16 6:40 ` Philippe Mathieu-Daudé
2025-04-16 19:19 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 145/163] tcg/sparc64: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:20 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 146/163] tcg/sparc64: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:20 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 147/163] tcg/tci: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:36 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 148/163] tcg/tci: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:37 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 149/163] tcg: Remove add2/sub2 opcodes Richard Henderson
2025-04-16 19:37 ` Pierrick Bouvier
2025-04-22 16:42 ` Philippe Mathieu-Daudé
2025-04-22 17:10 ` Richard Henderson
2025-04-15 19:25 ` [PATCH v4 150/163] tcg: Formalize tcg_out_mb Richard Henderson
2025-04-16 19:38 ` Pierrick Bouvier
2025-04-22 16:44 ` Philippe Mathieu-Daudé
2025-04-15 19:25 ` [PATCH v4 151/163] tcg: Formalize tcg_out_br Richard Henderson
2025-04-16 19:38 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 152/163] tcg: Formalize tcg_out_goto_ptr Richard Henderson
2025-04-16 20:45 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 153/163] tcg: Assign TCGOP_TYPE in liveness_pass_2 Richard Henderson
2025-04-16 20:46 ` Pierrick Bouvier
2025-04-18 10:46 ` Nicholas Piggin
2025-04-21 16:28 ` Richard Henderson
2025-04-15 19:25 ` [PATCH v4 154/163] tcg: Convert ld to TCGOutOpLoad Richard Henderson
2025-04-16 20:52 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 155/163] tcg: Merge INDEX_op_ld*_{i32,i64} Richard Henderson
2025-04-16 20:53 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 156/163] tcg: Convert st to TCGOutOpStore Richard Henderson
2025-04-16 20:53 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 157/163] tcg: Merge INDEX_op_st*_{i32,i64} Richard Henderson
2025-04-16 7:05 ` Philippe Mathieu-Daudé
2025-04-16 20:53 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 158/163] tcg: Stash MemOp size in TCGOP_FLAGS Richard Henderson
2025-04-16 6:55 ` Philippe Mathieu-Daudé
2025-04-16 20:54 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 159/163] tcg: Remove INDEX_op_qemu_st8_* Richard Henderson
2025-04-16 6:55 ` Philippe Mathieu-Daudé
2025-04-16 19:24 ` Richard Henderson
2025-04-16 20:55 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 160/163] tcg: Merge INDEX_op_{ld,st}_{i32,i64,i128} Richard Henderson
2025-04-16 20:56 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 161/163] tcg: Convert qemu_ld{2} to TCGOutOpLoad{2} Richard Henderson
2025-04-16 20:57 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 162/163] tcg: Convert qemu_st{2} to TCGOutOpLdSt{2} Richard Henderson
2025-04-16 20:58 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 163/163] tcg: Remove tcg_out_op Richard Henderson
2025-04-16 19:04 ` Pierrick Bouvier
2025-04-16 13:24 ` [PATCH v4 000/163] tcg: Convert to TCGOutOp structures Nicholas Piggin
2025-04-16 23:38 ` Pierrick Bouvier
2025-04-17 0:18 ` Richard Henderson
2025-04-17 0:49 ` Pierrick Bouvier
2025-04-17 12:02 ` BALATON Zoltan
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