From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53429) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1etJfB-0000Zl-AY for qemu-devel@nongnu.org; Tue, 06 Mar 2018 15:58:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1etJf7-0002qE-Az for qemu-devel@nongnu.org; Tue, 06 Mar 2018 15:58:21 -0500 Received: from mail-pl0-x244.google.com ([2607:f8b0:400e:c01::244]:46626) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1etJf7-0002qA-51 for qemu-devel@nongnu.org; Tue, 06 Mar 2018 15:58:17 -0500 Received: by mail-pl0-x244.google.com with SMTP id y8-v6so12559774pll.13 for ; Tue, 06 Mar 2018 12:58:16 -0800 (PST) From: Michael Clark Date: Wed, 7 Mar 2018 09:56:21 +1300 Message-Id: <1520369790-38306-12-git-send-email-mjc@sifive.com> In-Reply-To: <1520369790-38306-1-git-send-email-mjc@sifive.com> References: <1520369790-38306-1-git-send-email-mjc@sifive.com> Subject: [Qemu-devel] [PATCH v1 13/22] RISC-V: Make some header guards more specific List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann , RISC-V Patches Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- include/hw/riscv/spike.h | 4 ++-- include/hw/riscv/virt.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index 179b6cf..ed9d1db 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -16,8 +16,8 @@ * this program. If not, see . */ -#ifndef HW_SPIKE_H -#define HW_SPIKE_H +#ifndef HW_RISCV_SPIKE_H +#define HW_RISCV_SPIKE_H #define TYPE_RISCV_SPIKE_V1_09_1_BOARD "riscv.spike_v1_9_1" #define TYPE_RISCV_SPIKE_V1_10_0_BOARD "riscv.spike_v1_10" diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 9588909..d22f184 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -16,8 +16,8 @@ * this program. If not, see . */ -#ifndef HW_VIRT_H -#define HW_VIRT_H +#ifndef HW_RISCV_VIRT_H +#define HW_RISCV_VIRT_H typedef struct { RISCVHartArrayState soc; -- 2.7.0