From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Cc: Michael Clark <mjc@sifive.com>,
Palmer Dabbelt <palmer@sifive.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
RISC-V Patches <patches@groups.riscv.org>
Subject: [Qemu-devel] [PATCH v1 15/22] RISC-V: Use memory_region_is_ram in pte update
Date: Wed, 7 Mar 2018 09:56:23 +1300 [thread overview]
Message-ID: <1520369790-38306-14-git-send-email-mjc@sifive.com> (raw)
In-Reply-To: <1520369790-38306-1-git-send-email-mjc@sifive.com>
After reading cpu_physical_memory_write and friends, it seems
that memory_region_is_ram is a more appropriate interface,
and matches the intent of the code that is calling it.
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
target/riscv/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/helper.c b/target/riscv/helper.c
index 2165ecb..88551be 100644
--- a/target/riscv/helper.c
+++ b/target/riscv/helper.c
@@ -235,7 +235,7 @@ restart:
rcu_read_lock();
mr = address_space_translate(cs->as, pte_addr,
&addr1, &l, false);
- if (memory_access_is_direct(mr, true)) {
+ if (memory_region_is_ram(mr)) {
target_ulong *pte_pa =
qemu_map_ram_ptr(mr->ram_block, addr1);
#if TCG_OVERSIZED_GUEST
--
2.7.0
next prev parent reply other threads:[~2018-03-06 20:58 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-06 20:56 [Qemu-devel] [PATCH v1 02/22] RISC-V: Replace hardcoded constants with enum values Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 03/22] RISC-V: Make virt board description match spike Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 04/22] RISC-V: Use ROM base address and size from memmap Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 05/22] RISC-V: Remove identity_translate from load_elf Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 06/22] RISC-V: Mark ROM read-only after copying in code Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 07/22] RISC-V: Remove unused class definitions Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 08/22] RISC-V: Make sure rom has space for fdt Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 09/22] RISC-V: Include hexidecimal in disassembly Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 10/22] RISC-V: Hold rcu_read_lock when accessing memory Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 11/22] RISC-V: Improve page table walker spec compliance Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 12/22] RISC-V: Update E order and I extension order Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 13/22] RISC-V: Make some header guards more specific Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 14/22] RISC-V: Make virt header comment title consistent Michael Clark
2018-03-06 20:56 ` Michael Clark [this message]
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 16/22] RISC-V: Remove EM_RISCV ELF_MACHINE indirection Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 17/22] RISC-V: Hardwire satp to 0 for no-mmu case Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 18/22] RISC-V: Remove braces from satp case statement Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 19/22] RISC-V: riscv-qemu port supports sv39 and sv48 Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 20/22] RISC-V: vectored traps are optional Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 21/22] RISC-V: No traps on writes to misa/minstret/mcycle Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 22/22] RISC-V: Remove support for adhoc X_COP interrupt Michael Clark
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