From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53569) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1etJfU-0000sA-UM for qemu-devel@nongnu.org; Tue, 06 Mar 2018 15:58:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1etJfR-0002uQ-3Q for qemu-devel@nongnu.org; Tue, 06 Mar 2018 15:58:41 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:33295) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1etJfQ-0002uC-Tx for qemu-devel@nongnu.org; Tue, 06 Mar 2018 15:58:37 -0500 Received: by mail-pg0-x244.google.com with SMTP id g12so11746pgs.0 for ; Tue, 06 Mar 2018 12:58:36 -0800 (PST) From: Michael Clark Date: Wed, 7 Mar 2018 09:56:27 +1300 Message-Id: <1520369790-38306-18-git-send-email-mjc@sifive.com> In-Reply-To: <1520369790-38306-1-git-send-email-mjc@sifive.com> References: <1520369790-38306-1-git-send-email-mjc@sifive.com> Subject: [Qemu-devel] [PATCH v1 19/22] RISC-V: riscv-qemu port supports sv39 and sv48 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann , RISC-V Patches Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7c4482b..f47fc9c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -24,8 +24,8 @@ #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ #if defined(TARGET_RISCV64) #define TARGET_LONG_BITS 64 -#define TARGET_PHYS_ADDR_SPACE_BITS 50 -#define TARGET_VIRT_ADDR_SPACE_BITS 39 +#define TARGET_PHYS_ADDR_SPACE_BITS 52 +#define TARGET_VIRT_ADDR_SPACE_BITS 48 #elif defined(TARGET_RISCV32) #define TARGET_LONG_BITS 32 #define TARGET_PHYS_ADDR_SPACE_BITS 34 -- 2.7.0