From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Cc: Michael Clark <mjc@sifive.com>,
Palmer Dabbelt <palmer@sifive.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
RISC-V Patches <patches@groups.riscv.org>
Subject: [Qemu-devel] [PATCH v1 05/22] RISC-V: Remove identity_translate from load_elf
Date: Wed, 7 Mar 2018 09:56:13 +1300 [thread overview]
Message-ID: <1520369790-38306-4-git-send-email-mjc@sifive.com> (raw)
In-Reply-To: <1520369790-38306-1-git-send-email-mjc@sifive.com>
When load_elf is called with NULL as an argument to the
address translate callback, it does an identity translation.
This commit removes the redundant identity_translate callback.
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
hw/riscv/sifive_e.c | 7 +------
hw/riscv/sifive_u.c | 7 +------
hw/riscv/spike.c | 7 +------
hw/riscv/virt.c | 7 +------
4 files changed, 4 insertions(+), 24 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 19eca36..09c9d49 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -82,16 +82,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len)
}
}
-static uint64_t identity_translate(void *opaque, uint64_t addr)
-{
- return addr;
-}
-
static uint64_t load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;
- if (load_elf(kernel_filename, identity_translate, NULL,
+ if (load_elf(kernel_filename, NULL, NULL,
&kernel_entry, NULL, &kernel_high,
0, ELF_MACHINE, 1, 0) < 0) {
error_report("qemu: could not load kernel '%s'", kernel_filename);
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index f3f7615..6116c38 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -68,16 +68,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len)
}
}
-static uint64_t identity_translate(void *opaque, uint64_t addr)
-{
- return addr;
-}
-
static uint64_t load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;
- if (load_elf(kernel_filename, identity_translate, NULL,
+ if (load_elf(kernel_filename, NULL, NULL,
&kernel_entry, NULL, &kernel_high,
0, ELF_MACHINE, 1, 0) < 0) {
error_report("qemu: could not load kernel '%s'", kernel_filename);
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 4c233ec..7710333 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -59,16 +59,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len)
}
}
-static uint64_t identity_translate(void *opaque, uint64_t addr)
-{
- return addr;
-}
-
static uint64_t load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;
- if (load_elf_ram_sym(kernel_filename, identity_translate, NULL,
+ if (load_elf_ram_sym(kernel_filename, NULL, NULL,
&kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0,
NULL, true, htif_symbol_callback) < 0) {
error_report("qemu: could not load kernel '%s'", kernel_filename);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 0d101fc..f8c19b4 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -62,16 +62,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len)
}
}
-static uint64_t identity_translate(void *opaque, uint64_t addr)
-{
- return addr;
-}
-
static uint64_t load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;
- if (load_elf(kernel_filename, identity_translate, NULL,
+ if (load_elf(kernel_filename, NULL, NULL,
&kernel_entry, NULL, &kernel_high,
0, ELF_MACHINE, 1, 0) < 0) {
error_report("qemu: could not load kernel '%s'", kernel_filename);
--
2.7.0
next prev parent reply other threads:[~2018-03-06 20:57 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-06 20:56 [Qemu-devel] [PATCH v1 02/22] RISC-V: Replace hardcoded constants with enum values Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 03/22] RISC-V: Make virt board description match spike Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 04/22] RISC-V: Use ROM base address and size from memmap Michael Clark
2018-03-06 20:56 ` Michael Clark [this message]
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 06/22] RISC-V: Mark ROM read-only after copying in code Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 07/22] RISC-V: Remove unused class definitions Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 08/22] RISC-V: Make sure rom has space for fdt Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 09/22] RISC-V: Include hexidecimal in disassembly Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 10/22] RISC-V: Hold rcu_read_lock when accessing memory Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 11/22] RISC-V: Improve page table walker spec compliance Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 12/22] RISC-V: Update E order and I extension order Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 13/22] RISC-V: Make some header guards more specific Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 14/22] RISC-V: Make virt header comment title consistent Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 15/22] RISC-V: Use memory_region_is_ram in pte update Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 16/22] RISC-V: Remove EM_RISCV ELF_MACHINE indirection Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 17/22] RISC-V: Hardwire satp to 0 for no-mmu case Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 18/22] RISC-V: Remove braces from satp case statement Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 19/22] RISC-V: riscv-qemu port supports sv39 and sv48 Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 20/22] RISC-V: vectored traps are optional Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 21/22] RISC-V: No traps on writes to misa/minstret/mcycle Michael Clark
2018-03-06 20:56 ` [Qemu-devel] [PATCH v1 22/22] RISC-V: Remove support for adhoc X_COP interrupt Michael Clark
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