From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Cc: Michael Clark <mjc@sifive.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-devel] [PATCH v2 04/23] RISC-V: Use ROM base address and size from memmap
Date: Fri, 9 Mar 2018 17:12:26 +1300 [thread overview]
Message-ID: <1520568765-58189-5-git-send-email-mjc@sifive.com> (raw)
In-Reply-To: <1520568765-58189-1-git-send-email-mjc@sifive.com>
Another case of replaceing hard coded constants, this time
referring to the definition in the virt machine's memmap.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
hw/riscv/virt.c | 4 ++--
include/hw/riscv/virt.h | 2 --
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 0055439..0d101fc 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -338,11 +338,11 @@ static void riscv_virt_board_init(MachineState *machine)
};
/* copy in the reset vector */
- copy_le32_to_phys(ROM_BASE, reset_vec, sizeof(reset_vec));
+ copy_le32_to_phys(memmap[VIRT_MROM].base, reset_vec, sizeof(reset_vec));
/* copy in the device tree */
qemu_fdt_dumpdtb(s->fdt, s->fdt_size);
- cpu_physical_memory_write(ROM_BASE + sizeof(reset_vec),
+ cpu_physical_memory_write(memmap[VIRT_MROM].base + sizeof(reset_vec),
s->fdt, s->fdt_size);
/* create PLIC hart topology configuration string */
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 2fbe808..655e85d 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -23,8 +23,6 @@
#define VIRT(obj) \
OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD)
-enum { ROM_BASE = 0x1000 };
-
typedef struct {
/*< private >*/
SysBusDevice parent_obj;
--
2.7.0
next prev parent reply other threads:[~2018-03-09 4:14 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-09 4:12 [Qemu-devel] [PATCH v2 00/23] RISC-V Post-merge spec conformance and cleanup Michael Clark
2018-03-09 4:12 ` [Qemu-devel] [PATCH v2 01/23] RISC-V: Make virt create_fdt interface consistent Michael Clark
2018-03-10 20:33 ` Philippe Mathieu-Daudé
2018-03-09 4:12 ` [Qemu-devel] [PATCH v2 02/23] RISC-V: Replace hardcoded constants with enum values Michael Clark
2018-03-09 4:12 ` [Qemu-devel] [PATCH v2 03/23] RISC-V: Make virt board description match spike Michael Clark
2018-03-10 20:34 ` Philippe Mathieu-Daudé
2018-03-09 4:12 ` Michael Clark [this message]
2018-03-10 20:35 ` [Qemu-devel] [PATCH v2 04/23] RISC-V: Use ROM base address and size from memmap Philippe Mathieu-Daudé
2018-03-12 18:24 ` Eric Blake
2018-03-09 4:12 ` [Qemu-devel] [PATCH v2 05/23] RISC-V: Remove identity_translate from load_elf Michael Clark
2018-03-09 4:12 ` [Qemu-devel] [PATCH v2 06/23] RISC-V: Mark ROM read-only after copying in code Michael Clark
2018-03-09 4:12 ` [Qemu-devel] [PATCH v2 07/23] RISC-V: Remove unused class definitions Michael Clark
2018-03-09 4:12 ` [Qemu-devel] [PATCH v2 08/23] RISC-V: Make sure rom has space for fdt Michael Clark
2018-03-09 4:12 ` [Qemu-devel] [PATCH v2 09/23] RISC-V: Include intruction hex in disassembly Michael Clark
2018-03-09 4:12 ` [Qemu-devel] [PATCH v2 10/23] RISC-V: Hold rcu_read_lock when accessing memory Michael Clark
2018-03-10 20:45 ` Philippe Mathieu-Daudé
2018-03-09 4:12 ` [Qemu-devel] [PATCH v2 11/23] RISC-V: Improve page table walker spec compliance Michael Clark
2018-03-09 4:12 ` [Qemu-devel] [PATCH v2 12/23] RISC-V: Update E order and I extension order Michael Clark
2018-03-09 4:12 ` [Qemu-devel] [PATCH v2 13/23] RISC-V: Make some header guards more specific Michael Clark
2018-03-10 20:30 ` Philippe Mathieu-Daudé
2018-03-09 4:12 ` [Qemu-devel] [PATCH v2 14/23] RISC-V: Make virt header comment title consistent Michael Clark
2018-03-10 20:31 ` Philippe Mathieu-Daudé
2018-03-09 4:12 ` [Qemu-devel] [PATCH v2 15/23] RISC-V: Use memory_region_is_ram in pte update Michael Clark
2018-03-10 20:42 ` Philippe Mathieu-Daudé
2018-03-09 4:12 ` [Qemu-devel] [PATCH v2 16/23] RISC-V: Remove EM_RISCV ELF_MACHINE indirection Michael Clark
2018-03-10 20:32 ` Philippe Mathieu-Daudé
2018-03-09 4:12 ` [Qemu-devel] [PATCH v2 17/23] RISC-V: Hardwire satp to 0 for no-mmu case Michael Clark
2018-03-09 4:12 ` [Qemu-devel] [PATCH v2 18/23] RISC-V: Remove braces from satp case statement Michael Clark
2018-03-09 4:12 ` [Qemu-devel] [PATCH v2 19/23] RISC-V: riscv-qemu port supports sv39 and sv48 Michael Clark
2018-03-09 4:12 ` [Qemu-devel] [PATCH v2 20/23] RISC-V: vectored traps are optional Michael Clark
2018-03-09 4:12 ` [Qemu-devel] [PATCH v2 21/23] RISC-V: No traps on writes to misa, minstret, mcycle Michael Clark
2018-03-09 4:12 ` [Qemu-devel] [PATCH v2 22/23] RISC-V: Remove support for adhoc X_COP interrupt Michael Clark
2018-03-09 4:12 ` [Qemu-devel] [PATCH v2 23/23] RISC-V: Convert cpu definition towards future model Michael Clark
2018-03-10 20:30 ` Philippe Mathieu-Daudé
2018-03-12 17:34 ` [Qemu-devel] [PATCH v2 00/23] RISC-V Post-merge spec conformance and cleanup no-reply
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