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* [Qemu-devel] [PATCH] RISC-V: Fix isa string logic bug, use popcount to count bits
@ 2018-03-09 20:20 Michael Clark
  2018-03-09 20:32 ` Eric Blake
  2018-03-09 20:33 ` Eric Blake
  0 siblings, 2 replies; 4+ messages in thread
From: Michael Clark @ 2018-03-09 20:20 UTC (permalink / raw)
  To: qemu-devel; +Cc: Michael Clark, Palmer Dabbelt, Peter Maydell

Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
---
 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4851890..f0d6d1d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -391,7 +391,7 @@ static const TypeInfo riscv_cpu_type_info = {
 char *riscv_isa_string(RISCVCPU *cpu)
 {
     int i;
-    size_t maxlen = 5 + ctz32(cpu->env.misa);
+    size_t maxlen = 5 + __builtin_popcountll(cpu->env.misa);
     char *isa_string = g_new0(char, maxlen);
     snprintf(isa_string, maxlen, "rv%d", TARGET_LONG_BITS);
     for (i = 0; i < sizeof(riscv_exts); i++) {
-- 
2.7.0

^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [Qemu-devel] [PATCH] RISC-V: Fix isa string logic bug, use popcount to count bits
  2018-03-09 20:20 [Qemu-devel] [PATCH] RISC-V: Fix isa string logic bug, use popcount to count bits Michael Clark
@ 2018-03-09 20:32 ` Eric Blake
  2018-03-09 20:33 ` Eric Blake
  1 sibling, 0 replies; 4+ messages in thread
From: Eric Blake @ 2018-03-09 20:32 UTC (permalink / raw)
  To: qemu-devel

On 03/09/2018 02:20 PM, Michael Clark wrote:
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> ---
>   target/riscv/cpu.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 4851890..f0d6d1d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -391,7 +391,7 @@ static const TypeInfo riscv_cpu_type_info = {
>   char *riscv_isa_string(RISCVCPU *cpu)
>   {
>       int i;
> -    size_t maxlen = 5 + ctz32(cpu->env.misa);
> +    size_t maxlen = 5 + __builtin_popcountll(cpu->env.misa);

I'd rather you used ctpop64() from host-utils.h, so we have a 
centralized place to change things just once in case we have to tweak 
the use of __builtin_popcount when targetting a different compiler.

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.           +1-919-301-3266
Virtualization:  qemu.org | libvirt.org

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [Qemu-devel] [PATCH] RISC-V: Fix isa string logic bug, use popcount to count bits
  2018-03-09 20:20 [Qemu-devel] [PATCH] RISC-V: Fix isa string logic bug, use popcount to count bits Michael Clark
  2018-03-09 20:32 ` Eric Blake
@ 2018-03-09 20:33 ` Eric Blake
  2018-03-09 20:50   ` Michael Clark
  1 sibling, 1 reply; 4+ messages in thread
From: Eric Blake @ 2018-03-09 20:33 UTC (permalink / raw)
  To: Michael Clark, qemu-devel; +Cc: Peter Maydell, Palmer Dabbelt

[resend, this time with proper cc's]

On 03/09/2018 02:20 PM, Michael Clark wrote:
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> ---
>   target/riscv/cpu.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 4851890..f0d6d1d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -391,7 +391,7 @@ static const TypeInfo riscv_cpu_type_info = {
>   char *riscv_isa_string(RISCVCPU *cpu)
>   {
>       int i;
> -    size_t maxlen = 5 + ctz32(cpu->env.misa);
> +    size_t maxlen = 5 + __builtin_popcountll(cpu->env.misa);
>       char *isa_string = g_new0(char, maxlen);
>       snprintf(isa_string, maxlen, "rv%d", TARGET_LONG_BITS);
>       for (i = 0; i < sizeof(riscv_exts); i++) {

I'd rather you used ctpop64() from host-utils.h, so we have a 
centralized place to change things just once in case we have to tweak 
the use of __builtin_popcount when targetting a different compiler.

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.           +1-919-301-3266
Virtualization:  qemu.org | libvirt.org

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [Qemu-devel] [PATCH] RISC-V: Fix isa string logic bug, use popcount to count bits
  2018-03-09 20:33 ` Eric Blake
@ 2018-03-09 20:50   ` Michael Clark
  0 siblings, 0 replies; 4+ messages in thread
From: Michael Clark @ 2018-03-09 20:50 UTC (permalink / raw)
  To: Eric Blake; +Cc: QEMU Developers, Peter Maydell, Palmer Dabbelt

On Sat, Mar 10, 2018 at 9:33 AM, Eric Blake <eblake@redhat.com> wrote:

> [resend, this time with proper cc's]
>
> On 03/09/2018 02:20 PM, Michael Clark wrote:
>
>> Cc: Palmer Dabbelt <palmer@sifive.com>
>> Cc: Peter Maydell <peter.maydell@linaro.org>
>> Signed-off-by: Michael Clark <mjc@sifive.com>
>> ---
>>   target/riscv/cpu.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 4851890..f0d6d1d 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -391,7 +391,7 @@ static const TypeInfo riscv_cpu_type_info = {
>>   char *riscv_isa_string(RISCVCPU *cpu)
>>   {
>>       int i;
>> -    size_t maxlen = 5 + ctz32(cpu->env.misa);
>> +    size_t maxlen = 5 + __builtin_popcountll(cpu->env.misa);
>>       char *isa_string = g_new0(char, maxlen);
>>       snprintf(isa_string, maxlen, "rv%d", TARGET_LONG_BITS);
>>       for (i = 0; i < sizeof(riscv_exts); i++) {
>>
>
> I'd rather you used ctpop64() from host-utils.h, so we have a centralized
> place to change things just once in case we have to tweak the use of
> __builtin_popcount when targetting a different compiler.


Okay. I'll revise the patch...

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2018-03-09 20:50 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2018-03-09 20:20 [Qemu-devel] [PATCH] RISC-V: Fix isa string logic bug, use popcount to count bits Michael Clark
2018-03-09 20:32 ` Eric Blake
2018-03-09 20:33 ` Eric Blake
2018-03-09 20:50   ` Michael Clark

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