* [Qemu-devel] [PULL] RISC-V: Fix riscv_isa_string g_new0 size calculation
@ 2018-03-09 20:29 Michael Clark
2018-03-09 20:54 ` Michael Clark
0 siblings, 1 reply; 3+ messages in thread
From: Michael Clark @ 2018-03-09 20:29 UTC (permalink / raw)
To: Peter Maydell, qemu-devel; +Cc: Michael Clark, Palmer Dabbelt, RISC-V Patches
The following changes since commit e4ae62b802cec437f877f2cadc4ef059cc0eca76:
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2018-03-09 17:28:16 +0000)
are available in the git repository at:
https://github.com/michaeljclark/riscv-qemu.git fix-riscv-isa-string
for you to fetch changes up to 32b3a5716062f805a42e1cae1df95f2f869a78c1:
RISC-V: Fix isa string logic bug, use popcount to count bits (2018-03-10 09:17:29 +1300)
----------------------------------------------------------------
Michael Clark (1):
RISC-V: Fix isa string logic bug, use popcount to count bits
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [Qemu-devel] [PULL] RISC-V: Fix riscv_isa_string g_new0 size calculation
2018-03-09 20:29 [Qemu-devel] [PULL] RISC-V: Fix riscv_isa_string g_new0 size calculation Michael Clark
@ 2018-03-09 20:54 ` Michael Clark
2018-03-10 16:51 ` Peter Maydell
0 siblings, 1 reply; 3+ messages in thread
From: Michael Clark @ 2018-03-09 20:54 UTC (permalink / raw)
To: Peter Maydell, QEMU Developers
Cc: Michael Clark, Palmer Dabbelt, RISC-V Patches
Apologies for jumping the gun again with a PR before a review. It was most
likely because I thought it was a critical bug fix.
I'm incorporating Eric Blake's feedback.
On Sat, Mar 10, 2018 at 9:29 AM, Michael Clark <mjc@sifive.com> wrote:
> The following changes since commit e4ae62b802cec437f877f2cadc4ef0
> 59cc0eca76:
>
> Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request'
> into staging (2018-03-09 17:28:16 +0000)
>
> are available in the git repository at:
>
> https://github.com/michaeljclark/riscv-qemu.git fix-riscv-isa-string
>
> for you to fetch changes up to 32b3a5716062f805a42e1cae1df95f2f869a78c1:
>
> RISC-V: Fix isa string logic bug, use popcount to count bits (2018-03-10
> 09:17:29 +1300)
>
> ----------------------------------------------------------------
> Michael Clark (1):
> RISC-V: Fix isa string logic bug, use popcount to count bits
>
> target/riscv/cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PULL] RISC-V: Fix riscv_isa_string g_new0 size calculation
2018-03-09 20:54 ` Michael Clark
@ 2018-03-10 16:51 ` Peter Maydell
0 siblings, 0 replies; 3+ messages in thread
From: Peter Maydell @ 2018-03-10 16:51 UTC (permalink / raw)
To: Michael Clark; +Cc: QEMU Developers, Palmer Dabbelt, RISC-V Patches
On 9 March 2018 at 20:54, Michael Clark <mjc@sifive.com> wrote:
> Apologies for jumping the gun again with a PR before a review. It was most
> likely because I thought it was a critical bug fix.
>
> I'm incorporating Eric Blake's feedback.
For one-off "this is a build fix" bugfix patches, the simplest
thing is just to cc me on them and note (either in the commit
message or after the '---' separator) that it's a build fix.
Then I can just apply them directly to master once they've
been reviewed.
thanks
-- PMM
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2018-03-10 16:52 UTC | newest]
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2018-03-09 20:29 [Qemu-devel] [PULL] RISC-V: Fix riscv_isa_string g_new0 size calculation Michael Clark
2018-03-09 20:54 ` Michael Clark
2018-03-10 16:51 ` Peter Maydell
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