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From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Cc: patches@groups.riscv.org, Michael Clark <mjc@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-devel] [PATCH v3 18/24] RISC-V: Remove braces from satp case statement
Date: Fri, 16 Mar 2018 12:41:15 -0700	[thread overview]
Message-ID: <1521229281-73637-19-git-send-email-mjc@sifive.com> (raw)
In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com>

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/riscv/op_helper.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index dd3e417..f79716a 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -240,7 +240,7 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
         csr_write_helper(env, next_mie, CSR_MIE);
         break;
     }
-    case CSR_SATP: /* CSR_SPTBR */ {
+    case CSR_SATP: /* CSR_SPTBR */
         if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
             break;
         }
@@ -258,7 +258,6 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
             env->satp = val_to_write;
         }
         break;
-    }
     case CSR_SEPC:
         env->sepc = val_to_write;
         break;
-- 
2.7.0

  parent reply	other threads:[~2018-03-16 19:42 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-16 19:40 [Qemu-devel] [PATCH v3 00/24] RISC-V Post-merge spec conformance and cleanup Michael Clark
2018-03-16 19:40 ` [Qemu-devel] [PATCH v3 01/24] RISC-V: Make virt create_fdt interface consistent Michael Clark
2018-03-16 19:40 ` [Qemu-devel] [PATCH v3 02/24] RISC-V: Replace hardcoded constants with enum values Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 03/24] RISC-V: Make virt board description match spike Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 04/24] RISC-V: Use ROM base address and size from memmap Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 05/24] RISC-V: Remove identity_translate from load_elf Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 06/24] RISC-V: Mark ROM read-only after copying in code Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 07/24] RISC-V: Remove unused class definitions Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 08/24] RISC-V: Make sure rom has space for fdt Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 09/24] RISC-V: Include intruction hex in disassembly Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 10/24] RISC-V: Hold rcu_read_lock when accessing memory Michael Clark
2018-03-19  9:41   ` Paolo Bonzini
2018-03-19 21:07     ` Michael Clark
2018-03-21 13:55       ` Paolo Bonzini
2018-03-21 16:33         ` Peter Maydell
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 11/24] RISC-V: Improve page table walker spec compliance Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 12/24] RISC-V: Update E order and I extension order Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 13/24] RISC-V: Make some header guards more specific Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 14/24] RISC-V: Make virt header comment title consistent Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 15/24] RISC-V: Use memory_region_is_ram in pte update Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 16/24] RISC-V: Remove EM_RISCV ELF_MACHINE indirection Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 17/24] RISC-V: Hardwire satp to 0 for no-mmu case Michael Clark
2018-03-16 19:41 ` Michael Clark [this message]
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 19/24] RISC-V: riscv-qemu port supports sv39 and sv48 Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 20/24] RISC-V: vectored traps are optional Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 21/24] RISC-V: No traps on writes to misa, minstret, mcycle Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 22/24] RISC-V: Remove support for adhoc X_COP interrupt Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 23/24] RISC-V: Convert cpu definition towards future model Michael Clark
2018-03-19 15:47   ` Igor Mammedov
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 24/24] RISC-V: Clear mtval/stval on exceptions without info Michael Clark
2018-03-16 20:06 ` [Qemu-devel] [PATCH v3 00/24] RISC-V Post-merge spec conformance and cleanup no-reply
2018-03-16 20:33   ` [Qemu-devel] [patches] " Michael Clark

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