From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40467) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvFR-0007en-3C for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvFN-0003qe-MD for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:41 -0400 Received: from mail-pl0-x242.google.com ([2607:f8b0:400e:c01::242]:33536) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvFN-0003qP-Fh for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:37 -0400 Received: by mail-pl0-x242.google.com with SMTP id c11-v6so6503753plo.0 for ; Fri, 16 Mar 2018 12:42:37 -0700 (PDT) From: Michael Clark Date: Fri, 16 Mar 2018 12:41:18 -0700 Message-Id: <1521229281-73637-22-git-send-email-mjc@sifive.com> In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> Subject: [Qemu-devel] [PATCH v3 21/24] RISC-V: No traps on writes to misa, minstret, mcycle List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@groups.riscv.org, Michael Clark , Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt These fields are marked WARL in the specification so illegal writes are silently dropped. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/op_helper.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index aa101cc..f8595a6 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -200,17 +200,19 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, break; } case CSR_MINSTRET: - qemu_log_mask(LOG_UNIMP, "CSR_MINSTRET: write not implemented"); - goto do_illegal; + /* minstret is WARL so unsupported writes are ignored */ + break; case CSR_MCYCLE: - qemu_log_mask(LOG_UNIMP, "CSR_MCYCLE: write not implemented"); - goto do_illegal; + /* mcycle is WARL so unsupported writes are ignored */ + break; +#if defined(TARGET_RISCV32) case CSR_MINSTRETH: - qemu_log_mask(LOG_UNIMP, "CSR_MINSTRETH: write not implemented"); - goto do_illegal; + /* minstreth is WARL so unsupported writes are ignored */ + break; case CSR_MCYCLEH: - qemu_log_mask(LOG_UNIMP, "CSR_MCYCLEH: write not implemented"); - goto do_illegal; + /* mcycleh is WARL so unsupported writes are ignored */ + break; +#endif case CSR_MUCOUNTEREN: env->mucounteren = val_to_write; break; @@ -300,10 +302,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, case CSR_MBADADDR: env->mbadaddr = val_to_write; break; - case CSR_MISA: { - qemu_log_mask(LOG_UNIMP, "CSR_MISA: misa writes not supported"); - goto do_illegal; - } + case CSR_MISA: + /* misa is WARL so unsupported writes are ignored */ + break; case CSR_PMPCFG0: case CSR_PMPCFG1: case CSR_PMPCFG2: @@ -328,7 +329,6 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, case CSR_PMPADDR15: pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val_to_write); break; - do_illegal: #endif default: do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); -- 2.7.0