From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Cc: patches@groups.riscv.org, Michael Clark <mjc@sifive.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-devel] [PATCH v3 06/24] RISC-V: Mark ROM read-only after copying in code
Date: Fri, 16 Mar 2018 12:41:03 -0700 [thread overview]
Message-ID: <1521229281-73637-7-git-send-email-mjc@sifive.com> (raw)
In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com>
The sifive_u machine already marks its ROM readonly. This fixes
the remaining boards.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
hw/riscv/sifive_u.c | 9 +++++----
hw/riscv/spike.c | 18 ++++++++++--------
hw/riscv/virt.c | 7 ++++---
include/hw/riscv/spike.h | 8 --------
4 files changed, 19 insertions(+), 23 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 6116c38..25df16c 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -223,7 +223,7 @@ static void riscv_sifive_u_init(MachineState *machine)
SiFiveUState *s = g_new0(SiFiveUState, 1);
MemoryRegion *sys_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
- MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
+ MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
/* Initialize SOC */
object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY);
@@ -246,10 +246,10 @@ static void riscv_sifive_u_init(MachineState *machine)
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
/* boot rom */
- memory_region_init_ram(boot_rom, NULL, "riscv.sifive.u.mrom",
+ memory_region_init_ram(mask_rom, NULL, "riscv.sifive.u.mrom",
memmap[SIFIVE_U_MROM].base, &error_fatal);
- memory_region_set_readonly(boot_rom, true);
- memory_region_add_subregion(sys_memory, 0x0, boot_rom);
+ memory_region_set_readonly(mask_rom, true);
+ memory_region_add_subregion(sys_memory, 0x0, mask_rom);
if (machine->kernel_filename) {
load_kernel(machine->kernel_filename);
@@ -279,6 +279,7 @@ static void riscv_sifive_u_init(MachineState *machine)
qemu_fdt_dumpdtb(s->fdt, s->fdt_size);
cpu_physical_memory_write(memmap[SIFIVE_U_MROM].base +
sizeof(reset_vec), s->fdt, s->fdt_size);
+ memory_region_set_readonly(mask_rom, true);
/* MMIO */
s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 7710333..74edf33 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -173,7 +173,7 @@ static void spike_v1_10_0_board_init(MachineState *machine)
SpikeState *s = g_new0(SpikeState, 1);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
- MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
+ MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
/* Initialize SOC */
object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY);
@@ -196,9 +196,9 @@ static void spike_v1_10_0_board_init(MachineState *machine)
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
/* boot rom */
- memory_region_init_ram(boot_rom, NULL, "riscv.spike.bootrom",
+ memory_region_init_ram(mask_rom, NULL, "riscv.spike.mrom",
s->fdt_size + 0x2000, &error_fatal);
- memory_region_add_subregion(system_memory, 0x0, boot_rom);
+ memory_region_add_subregion(system_memory, 0x0, mask_rom);
if (machine->kernel_filename) {
load_kernel(machine->kernel_filename);
@@ -228,9 +228,10 @@ static void spike_v1_10_0_board_init(MachineState *machine)
qemu_fdt_dumpdtb(s->fdt, s->fdt_size);
cpu_physical_memory_write(memmap[SPIKE_MROM].base + sizeof(reset_vec),
s->fdt, s->fdt_size);
+ memory_region_set_readonly(mask_rom, true);
/* initialize HTIF using symbols found in load_kernel */
- htif_mm_init(system_memory, boot_rom, &s->soc.harts[0].env, serial_hds[0]);
+ htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hds[0]);
/* Core Local Interruptor (timer and IPI) */
sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
@@ -244,7 +245,7 @@ static void spike_v1_09_1_board_init(MachineState *machine)
SpikeState *s = g_new0(SpikeState, 1);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
- MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
+ MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
/* Initialize SOC */
object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY);
@@ -264,9 +265,9 @@ static void spike_v1_09_1_board_init(MachineState *machine)
main_mem);
/* boot rom */
- memory_region_init_ram(boot_rom, NULL, "riscv.spike.bootrom",
+ memory_region_init_ram(mask_rom, NULL, "riscv.spike.mrom",
0x40000, &error_fatal);
- memory_region_add_subregion(system_memory, 0x0, boot_rom);
+ memory_region_add_subregion(system_memory, 0x0, mask_rom);
if (machine->kernel_filename) {
load_kernel(machine->kernel_filename);
@@ -325,9 +326,10 @@ static void spike_v1_09_1_board_init(MachineState *machine)
/* copy in the config string */
cpu_physical_memory_write(memmap[SPIKE_MROM].base + sizeof(reset_vec),
config_string, config_string_len);
+ memory_region_set_readonly(mask_rom, true);
/* initialize HTIF using symbols found in load_kernel */
- htif_mm_init(system_memory, boot_rom, &s->soc.harts[0].env, serial_hds[0]);
+ htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hds[0]);
/* Core Local Interruptor (timer and IPI) */
sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index f8c19b4..f1e3641 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -270,7 +270,7 @@ static void riscv_virt_board_init(MachineState *machine)
RISCVVirtState *s = g_new0(RISCVVirtState, 1);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
- MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
+ MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
char *plic_hart_config;
size_t plic_hart_config_len;
int i;
@@ -296,9 +296,9 @@ static void riscv_virt_board_init(MachineState *machine)
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
/* boot rom */
- memory_region_init_ram(boot_rom, NULL, "riscv_virt_board.bootrom",
+ memory_region_init_ram(mask_rom, NULL, "riscv_virt_board.mrom",
s->fdt_size + 0x2000, &error_fatal);
- memory_region_add_subregion(system_memory, 0x0, boot_rom);
+ memory_region_add_subregion(system_memory, 0x0, mask_rom);
if (machine->kernel_filename) {
uint64_t kernel_entry = load_kernel(machine->kernel_filename);
@@ -339,6 +339,7 @@ static void riscv_virt_board_init(MachineState *machine)
qemu_fdt_dumpdtb(s->fdt, s->fdt_size);
cpu_physical_memory_write(memmap[VIRT_MROM].base + sizeof(reset_vec),
s->fdt, s->fdt_size);
+ memory_region_set_readonly(mask_rom, true);
/* create PLIC hart topology configuration string */
plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
index d85a64e..179b6cf 100644
--- a/include/hw/riscv/spike.h
+++ b/include/hw/riscv/spike.h
@@ -22,20 +22,12 @@
#define TYPE_RISCV_SPIKE_V1_09_1_BOARD "riscv.spike_v1_9_1"
#define TYPE_RISCV_SPIKE_V1_10_0_BOARD "riscv.spike_v1_10"
-#define SPIKE(obj) \
- OBJECT_CHECK(SpikeState, (obj), TYPE_RISCV_SPIKE_BOARD)
-
typedef struct {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
RISCVHartArrayState soc;
void *fdt;
int fdt_size;
} SpikeState;
-
enum {
SPIKE_MROM,
SPIKE_CLINT,
--
2.7.0
next prev parent reply other threads:[~2018-03-16 19:42 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-16 19:40 [Qemu-devel] [PATCH v3 00/24] RISC-V Post-merge spec conformance and cleanup Michael Clark
2018-03-16 19:40 ` [Qemu-devel] [PATCH v3 01/24] RISC-V: Make virt create_fdt interface consistent Michael Clark
2018-03-16 19:40 ` [Qemu-devel] [PATCH v3 02/24] RISC-V: Replace hardcoded constants with enum values Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 03/24] RISC-V: Make virt board description match spike Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 04/24] RISC-V: Use ROM base address and size from memmap Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 05/24] RISC-V: Remove identity_translate from load_elf Michael Clark
2018-03-16 19:41 ` Michael Clark [this message]
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 07/24] RISC-V: Remove unused class definitions Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 08/24] RISC-V: Make sure rom has space for fdt Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 09/24] RISC-V: Include intruction hex in disassembly Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 10/24] RISC-V: Hold rcu_read_lock when accessing memory Michael Clark
2018-03-19 9:41 ` Paolo Bonzini
2018-03-19 21:07 ` Michael Clark
2018-03-21 13:55 ` Paolo Bonzini
2018-03-21 16:33 ` Peter Maydell
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 11/24] RISC-V: Improve page table walker spec compliance Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 12/24] RISC-V: Update E order and I extension order Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 13/24] RISC-V: Make some header guards more specific Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 14/24] RISC-V: Make virt header comment title consistent Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 15/24] RISC-V: Use memory_region_is_ram in pte update Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 16/24] RISC-V: Remove EM_RISCV ELF_MACHINE indirection Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 17/24] RISC-V: Hardwire satp to 0 for no-mmu case Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 18/24] RISC-V: Remove braces from satp case statement Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 19/24] RISC-V: riscv-qemu port supports sv39 and sv48 Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 20/24] RISC-V: vectored traps are optional Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 21/24] RISC-V: No traps on writes to misa, minstret, mcycle Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 22/24] RISC-V: Remove support for adhoc X_COP interrupt Michael Clark
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 23/24] RISC-V: Convert cpu definition towards future model Michael Clark
2018-03-19 15:47 ` Igor Mammedov
2018-03-16 19:41 ` [Qemu-devel] [PATCH v3 24/24] RISC-V: Clear mtval/stval on exceptions without info Michael Clark
2018-03-16 20:06 ` [Qemu-devel] [PATCH v3 00/24] RISC-V Post-merge spec conformance and cleanup no-reply
2018-03-16 20:33 ` [Qemu-devel] [patches] " Michael Clark
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1521229281-73637-7-git-send-email-mjc@sifive.com \
--to=mjc@sifive.com \
--cc=kbastian@mail.uni-paderborn.de \
--cc=palmer@sifive.com \
--cc=patches@groups.riscv.org \
--cc=qemu-devel@nongnu.org \
--cc=sagark@eecs.berkeley.edu \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).