From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44304) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww1Y-0005z2-IB for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eww1X-0003UJ-Kj for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:24 -0400 From: Aaron Lindsay Date: Fri, 16 Mar 2018 16:31:12 -0400 Message-Id: <1521232280-13089-15-git-send-email-alindsay@codeaurora.org> In-Reply-To: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> Subject: [Qemu-devel] [PATCH v3 14/22] target/arm: Make PMOVSCLR 64 bits wide List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Cc: qemu-devel@nongnu.org, Michael Spradling , Digant Desai , Aaron Lindsay This is a bug fix to ensure 64-bit reads of this register don't read adjacent data. Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9c3b5ef..fb2f983 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -367,7 +367,7 @@ typedef struct CPUARMState { uint32_t c9_data; uint64_t c9_pmcr; /* performance monitor control register */ uint64_t c9_pmcnten; /* perf monitor counter enables */ - uint32_t c9_pmovsr; /* perf monitor overflow status */ + uint64_t c9_pmovsr; /* perf monitor overflow status */ uint32_t c9_pmuserenr; /* perf monitor user enable */ uint64_t c9_pmselr; /* perf monitor counter selection register */ uint64_t c9_pminten; /* perf monitor interrupt enables */ -- Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.