qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Cc: patches@groups.riscv.org, Michael Clark <mjc@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-devel] [PULL 15/24] RISC-V: Remove EM_RISCV ELF_MACHINE indirection
Date: Wed, 21 Mar 2018 13:46:51 -0700	[thread overview]
Message-ID: <1521665220-3869-16-git-send-email-mjc@sifive.com> (raw)
In-Reply-To: <1521665220-3869-1-git-send-email-mjc@sifive.com>

Pointless indirection. Other ports use EM_ constants directly.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 hw/riscv/sifive_e.c | 2 +-
 hw/riscv/sifive_u.c | 2 +-
 hw/riscv/spike.c    | 2 +-
 hw/riscv/virt.c     | 2 +-
 target/riscv/cpu.h  | 1 -
 5 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 4872b68..39e4cb4 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -88,7 +88,7 @@ static uint64_t load_kernel(const char *kernel_filename)
 
     if (load_elf(kernel_filename, NULL, NULL,
                  &kernel_entry, NULL, &kernel_high,
-                 0, ELF_MACHINE, 1, 0) < 0) {
+                 0, EM_RISCV, 1, 0) < 0) {
         error_report("qemu: could not load kernel '%s'", kernel_filename);
         exit(1);
     }
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 57b4f4f..0e633a0 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -74,7 +74,7 @@ static uint64_t load_kernel(const char *kernel_filename)
 
     if (load_elf(kernel_filename, NULL, NULL,
                  &kernel_entry, NULL, &kernel_high,
-                 0, ELF_MACHINE, 1, 0) < 0) {
+                 0, EM_RISCV, 1, 0) < 0) {
         error_report("qemu: could not load kernel '%s'", kernel_filename);
         exit(1);
     }
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index c7d937b..70e697c 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -64,7 +64,7 @@ static uint64_t load_kernel(const char *kernel_filename)
     uint64_t kernel_entry, kernel_high;
 
     if (load_elf_ram_sym(kernel_filename, NULL, NULL,
-            &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0,
+            &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0,
             NULL, true, htif_symbol_callback) < 0) {
         error_report("qemu: could not load kernel '%s'", kernel_filename);
         exit(1);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index d680cbd..e3f8bb7 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -68,7 +68,7 @@ static uint64_t load_kernel(const char *kernel_filename)
 
     if (load_elf(kernel_filename, NULL, NULL,
                  &kernel_entry, NULL, &kernel_high,
-                 0, ELF_MACHINE, 1, 0) < 0) {
+                 0, EM_RISCV, 1, 0) < 0) {
         error_report("qemu: could not load kernel '%s'", kernel_filename);
         exit(1);
     }
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1fdcd75..1dcbdbe 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -34,7 +34,6 @@
 
 #define TCG_GUEST_DEFAULT_MO 0
 
-#define ELF_MACHINE EM_RISCV
 #define CPUArchState struct CPURISCVState
 
 #include "qemu-common.h"
-- 
2.7.0

  parent reply	other threads:[~2018-03-21 20:48 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-21 20:46 [Qemu-devel] [PULL 00/24] RISC-V: Post-merge spec conformance and cleanup v5 Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 01/24] RISC-V: Make virt create_fdt interface consistent Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 02/24] RISC-V: Replace hardcoded constants with enum values Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 03/24] RISC-V: Make virt board description match spike Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 04/24] RISC-V: Use ROM base address and size from memmap Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 05/24] RISC-V: Remove identity_translate from load_elf Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 06/24] RISC-V: Mark ROM read-only after copying in code Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 07/24] RISC-V: Remove unused class definitions Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 08/24] RISC-V: Make sure rom has space for fdt Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 09/24] RISC-V: Include intruction hex in disassembly Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 10/24] RISC-V: Improve page table walker spec compliance Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 11/24] RISC-V: Update E order and I extension order Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 12/24] RISC-V: Make some header guards more specific Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 13/24] RISC-V: Make virt header comment title consistent Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 14/24] RISC-V: Use memory_region_is_ram in pte update Michael Clark
2018-03-21 20:46 ` Michael Clark [this message]
2018-03-21 20:46 ` [Qemu-devel] [PULL 16/24] RISC-V: Hardwire satp to 0 for no-mmu case Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 17/24] RISC-V: Remove braces from satp case statement Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 18/24] RISC-V: riscv-qemu port supports sv39 and sv48 Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 19/24] RISC-V: vectored traps are optional Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 20/24] RISC-V: No traps on writes to misa, minstret, mcycle Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 21/24] RISC-V: Remove support for adhoc X_COP interrupt Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 22/24] RISC-V: Convert cpu definition towards future model Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 23/24] RISC-V: Clear mtval/stval on exceptions without info Michael Clark
2018-03-21 20:47 ` [Qemu-devel] [PULL 24/24] RISC-V: Remove erroneous comment from translate.c Michael Clark
2018-03-24 18:54 ` [Qemu-devel] [PULL 00/24] RISC-V: Post-merge spec conformance and cleanup v5 Michael Clark
2018-03-24 19:06   ` Michael Clark

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1521665220-3869-16-git-send-email-mjc@sifive.com \
    --to=mjc@sifive.com \
    --cc=kbastian@mail.uni-paderborn.de \
    --cc=palmer@sifive.com \
    --cc=patches@groups.riscv.org \
    --cc=qemu-devel@nongnu.org \
    --cc=sagark@eecs.berkeley.edu \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).