From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53142) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eykeT-00026H-Re for qemu-devel@nongnu.org; Wed, 21 Mar 2018 16:48:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eykeS-000294-P0 for qemu-devel@nongnu.org; Wed, 21 Mar 2018 16:48:05 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:34030) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eykeS-00028p-Iu for qemu-devel@nongnu.org; Wed, 21 Mar 2018 16:48:04 -0400 Received: by mail-pf0-x243.google.com with SMTP id j20so2466288pfi.1 for ; Wed, 21 Mar 2018 13:48:04 -0700 (PDT) From: Michael Clark Date: Wed, 21 Mar 2018 13:46:51 -0700 Message-Id: <1521665220-3869-16-git-send-email-mjc@sifive.com> In-Reply-To: <1521665220-3869-1-git-send-email-mjc@sifive.com> References: <1521665220-3869-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 15/24] RISC-V: Remove EM_RISCV ELF_MACHINE indirection List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@groups.riscv.org, Michael Clark , Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt Pointless indirection. Other ports use EM_ constants directly. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daudé --- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 2 +- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 2 +- target/riscv/cpu.h | 1 - 5 files changed, 4 insertions(+), 5 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 4872b68..39e4cb4 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -88,7 +88,7 @@ static uint64_t load_kernel(const char *kernel_filename) if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, - 0, ELF_MACHINE, 1, 0) < 0) { + 0, EM_RISCV, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); exit(1); } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 57b4f4f..0e633a0 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -74,7 +74,7 @@ static uint64_t load_kernel(const char *kernel_filename) if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, - 0, ELF_MACHINE, 1, 0) < 0) { + 0, EM_RISCV, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); exit(1); } diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index c7d937b..70e697c 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -64,7 +64,7 @@ static uint64_t load_kernel(const char *kernel_filename) uint64_t kernel_entry, kernel_high; if (load_elf_ram_sym(kernel_filename, NULL, NULL, - &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0, + &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0, NULL, true, htif_symbol_callback) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); exit(1); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index d680cbd..e3f8bb7 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -68,7 +68,7 @@ static uint64_t load_kernel(const char *kernel_filename) if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, - 0, ELF_MACHINE, 1, 0) < 0) { + 0, EM_RISCV, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); exit(1); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1fdcd75..1dcbdbe 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -34,7 +34,6 @@ #define TCG_GUEST_DEFAULT_MO 0 -#define ELF_MACHINE EM_RISCV #define CPUArchState struct CPURISCVState #include "qemu-common.h" -- 2.7.0