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From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Cc: patches@groups.riscv.org, Michael Clark <mjc@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-devel] [PULL 03/24] RISC-V: Make virt board description match spike
Date: Wed, 21 Mar 2018 13:46:39 -0700	[thread overview]
Message-ID: <1521665220-3869-4-git-send-email-mjc@sifive.com> (raw)
In-Reply-To: <1521665220-3869-1-git-send-email-mjc@sifive.com>

This makes 'qemu-system-riscv64 -machine help' output more tidy
and consistent.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 hw/riscv/virt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index a402856..0055439 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -404,7 +404,7 @@ static const TypeInfo riscv_virt_board_device = {
 
 static void riscv_virt_board_machine_init(MachineClass *mc)
 {
-    mc->desc = "RISC-V VirtIO Board (Privileged spec v1.10)";
+    mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)";
     mc->init = riscv_virt_board_init;
     mc->max_cpus = 8; /* hardcoded limit in BBL */
 }
-- 
2.7.0

  parent reply	other threads:[~2018-03-21 20:47 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-21 20:46 [Qemu-devel] [PULL 00/24] RISC-V: Post-merge spec conformance and cleanup v5 Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 01/24] RISC-V: Make virt create_fdt interface consistent Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 02/24] RISC-V: Replace hardcoded constants with enum values Michael Clark
2018-03-21 20:46 ` Michael Clark [this message]
2018-03-21 20:46 ` [Qemu-devel] [PULL 04/24] RISC-V: Use ROM base address and size from memmap Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 05/24] RISC-V: Remove identity_translate from load_elf Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 06/24] RISC-V: Mark ROM read-only after copying in code Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 07/24] RISC-V: Remove unused class definitions Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 08/24] RISC-V: Make sure rom has space for fdt Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 09/24] RISC-V: Include intruction hex in disassembly Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 10/24] RISC-V: Improve page table walker spec compliance Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 11/24] RISC-V: Update E order and I extension order Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 12/24] RISC-V: Make some header guards more specific Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 13/24] RISC-V: Make virt header comment title consistent Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 14/24] RISC-V: Use memory_region_is_ram in pte update Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 15/24] RISC-V: Remove EM_RISCV ELF_MACHINE indirection Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 16/24] RISC-V: Hardwire satp to 0 for no-mmu case Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 17/24] RISC-V: Remove braces from satp case statement Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 18/24] RISC-V: riscv-qemu port supports sv39 and sv48 Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 19/24] RISC-V: vectored traps are optional Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 20/24] RISC-V: No traps on writes to misa, minstret, mcycle Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 21/24] RISC-V: Remove support for adhoc X_COP interrupt Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 22/24] RISC-V: Convert cpu definition towards future model Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 23/24] RISC-V: Clear mtval/stval on exceptions without info Michael Clark
2018-03-21 20:47 ` [Qemu-devel] [PULL 24/24] RISC-V: Remove erroneous comment from translate.c Michael Clark
2018-03-24 18:54 ` [Qemu-devel] [PULL 00/24] RISC-V: Post-merge spec conformance and cleanup v5 Michael Clark
2018-03-24 19:06   ` Michael Clark

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