From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Cc: patches@groups.riscv.org, Michael Clark <mjc@sifive.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-devel] [PULL 07/24] RISC-V: Remove unused class definitions
Date: Wed, 21 Mar 2018 13:46:43 -0700 [thread overview]
Message-ID: <1521665220-3869-8-git-send-email-mjc@sifive.com> (raw)
In-Reply-To: <1521665220-3869-1-git-send-email-mjc@sifive.com>
Removes a whole lot of unnecessary boilerplate code. Machines
don't need to be objects. The expansion of the SOC object model
for the RISC-V machines will happen in the future as SiFive
plans to add their FE310 and FU540 SOCs to QEMU. However, it
seems that this present boilerplate is complete unnecessary.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/riscv/riscv_hart.c | 6 ------
hw/riscv/sifive_e.c | 25 -------------------------
hw/riscv/sifive_u.c | 25 -------------------------
hw/riscv/spike.c | 20 --------------------
hw/riscv/virt.c | 25 -------------------------
include/hw/riscv/sifive_e.h | 5 -----
include/hw/riscv/sifive_u.h | 5 -----
include/hw/riscv/spike.h | 7 ++++---
include/hw/riscv/virt.h | 5 -----
9 files changed, 4 insertions(+), 119 deletions(-)
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index 14e3c18..75ba7ed 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -68,16 +68,10 @@ static void riscv_harts_class_init(ObjectClass *klass, void *data)
dc->realize = riscv_harts_realize;
}
-static void riscv_harts_init(Object *obj)
-{
- /* RISCVHartArrayState *s = SIFIVE_COREPLEX(obj); */
-}
-
static const TypeInfo riscv_harts_info = {
.name = TYPE_RISCV_HART_ARRAY,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(RISCVHartArrayState),
- .instance_init = riscv_harts_init,
.class_init = riscv_harts_class_init,
};
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 09c9d49..4872b68 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -194,24 +194,6 @@ static void riscv_sifive_e_init(MachineState *machine)
}
}
-static int riscv_sifive_e_sysbus_device_init(SysBusDevice *sysbusdev)
-{
- return 0;
-}
-
-static void riscv_sifive_e_class_init(ObjectClass *klass, void *data)
-{
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- k->init = riscv_sifive_e_sysbus_device_init;
-}
-
-static const TypeInfo riscv_sifive_e_device = {
- .name = TYPE_SIFIVE_E,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(SiFiveEState),
- .class_init = riscv_sifive_e_class_init,
-};
-
static void riscv_sifive_e_machine_init(MachineClass *mc)
{
mc->desc = "RISC-V Board compatible with SiFive E SDK";
@@ -220,10 +202,3 @@ static void riscv_sifive_e_machine_init(MachineClass *mc)
}
DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
-
-static void riscv_sifive_e_register_types(void)
-{
- type_register_static(&riscv_sifive_e_device);
-}
-
-type_init(riscv_sifive_e_register_types);
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 25df16c..083043a 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -302,31 +302,6 @@ static void riscv_sifive_u_init(MachineState *machine)
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
}
-static int riscv_sifive_u_sysbus_device_init(SysBusDevice *sysbusdev)
-{
- return 0;
-}
-
-static void riscv_sifive_u_class_init(ObjectClass *klass, void *data)
-{
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- k->init = riscv_sifive_u_sysbus_device_init;
-}
-
-static const TypeInfo riscv_sifive_u_device = {
- .name = TYPE_SIFIVE_U,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(SiFiveUState),
- .class_init = riscv_sifive_u_class_init,
-};
-
-static void riscv_sifive_u_register_types(void)
-{
- type_register_static(&riscv_sifive_u_device);
-}
-
-type_init(riscv_sifive_u_register_types);
-
static void riscv_sifive_u_machine_init(MachineClass *mc)
{
mc->desc = "RISC-V Board compatible with SiFive U SDK";
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 74edf33..64e585e 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -336,18 +336,6 @@ static void spike_v1_09_1_board_init(MachineState *machine)
smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
}
-static const TypeInfo spike_v_1_09_1_device = {
- .name = TYPE_RISCV_SPIKE_V1_09_1_BOARD,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(SpikeState),
-};
-
-static const TypeInfo spike_v_1_10_0_device = {
- .name = TYPE_RISCV_SPIKE_V1_10_0_BOARD,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(SpikeState),
-};
-
static void spike_v1_09_1_machine_init(MachineClass *mc)
{
mc->desc = "RISC-V Spike Board (Privileged ISA v1.9.1)";
@@ -365,11 +353,3 @@ static void spike_v1_10_0_machine_init(MachineClass *mc)
DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init)
DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init)
-
-static void riscv_spike_board_register_types(void)
-{
- type_register_static(&spike_v_1_09_1_device);
- type_register_static(&spike_v_1_10_0_device);
-}
-
-type_init(riscv_spike_board_register_types);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index f1e3641..5913100 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -380,24 +380,6 @@ static void riscv_virt_board_init(MachineState *machine)
serial_hds[0], DEVICE_LITTLE_ENDIAN);
}
-static int riscv_virt_board_sysbus_device_init(SysBusDevice *sysbusdev)
-{
- return 0;
-}
-
-static void riscv_virt_board_class_init(ObjectClass *klass, void *data)
-{
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- k->init = riscv_virt_board_sysbus_device_init;
-}
-
-static const TypeInfo riscv_virt_board_device = {
- .name = TYPE_RISCV_VIRT_BOARD,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(RISCVVirtState),
- .class_init = riscv_virt_board_class_init,
-};
-
static void riscv_virt_board_machine_init(MachineClass *mc)
{
mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)";
@@ -406,10 +388,3 @@ static void riscv_virt_board_machine_init(MachineClass *mc)
}
DEFINE_MACHINE("virt", riscv_virt_board_machine_init)
-
-static void riscv_virt_board_register_types(void)
-{
- type_register_static(&riscv_virt_board_device);
-}
-
-type_init(riscv_virt_board_register_types);
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 0aebc57..12ad6d2 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -19,11 +19,6 @@
#ifndef HW_SIFIVE_E_H
#define HW_SIFIVE_E_H
-#define TYPE_SIFIVE_E "riscv.sifive_e"
-
-#define SIFIVE_E(obj) \
- OBJECT_CHECK(SiFiveEState, (obj), TYPE_SIFIVE_E)
-
typedef struct SiFiveEState {
/*< private >*/
SysBusDevice parent_obj;
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index be38aa0..94a3905 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -19,11 +19,6 @@
#ifndef HW_SIFIVE_U_H
#define HW_SIFIVE_U_H
-#define TYPE_SIFIVE_U "riscv.sifive_u"
-
-#define SIFIVE_U(obj) \
- OBJECT_CHECK(SiFiveUState, (obj), TYPE_SIFIVE_U)
-
typedef struct SiFiveUState {
/*< private >*/
SysBusDevice parent_obj;
diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
index 179b6cf..8410430 100644
--- a/include/hw/riscv/spike.h
+++ b/include/hw/riscv/spike.h
@@ -19,10 +19,11 @@
#ifndef HW_SPIKE_H
#define HW_SPIKE_H
-#define TYPE_RISCV_SPIKE_V1_09_1_BOARD "riscv.spike_v1_9_1"
-#define TYPE_RISCV_SPIKE_V1_10_0_BOARD "riscv.spike_v1_10"
-
typedef struct {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
RISCVHartArrayState soc;
void *fdt;
int fdt_size;
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 655e85d..b91a412 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -19,10 +19,6 @@
#ifndef HW_VIRT_H
#define HW_VIRT_H
-#define TYPE_RISCV_VIRT_BOARD "riscv.virt"
-#define VIRT(obj) \
- OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD)
-
typedef struct {
/*< private >*/
SysBusDevice parent_obj;
@@ -45,7 +41,6 @@ enum {
VIRT_DRAM
};
-
enum {
UART0_IRQ = 10,
VIRTIO_IRQ = 1, /* 1 to 8 */
--
2.7.0
next prev parent reply other threads:[~2018-03-21 20:47 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-21 20:46 [Qemu-devel] [PULL 00/24] RISC-V: Post-merge spec conformance and cleanup v5 Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 01/24] RISC-V: Make virt create_fdt interface consistent Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 02/24] RISC-V: Replace hardcoded constants with enum values Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 03/24] RISC-V: Make virt board description match spike Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 04/24] RISC-V: Use ROM base address and size from memmap Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 05/24] RISC-V: Remove identity_translate from load_elf Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 06/24] RISC-V: Mark ROM read-only after copying in code Michael Clark
2018-03-21 20:46 ` Michael Clark [this message]
2018-03-21 20:46 ` [Qemu-devel] [PULL 08/24] RISC-V: Make sure rom has space for fdt Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 09/24] RISC-V: Include intruction hex in disassembly Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 10/24] RISC-V: Improve page table walker spec compliance Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 11/24] RISC-V: Update E order and I extension order Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 12/24] RISC-V: Make some header guards more specific Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 13/24] RISC-V: Make virt header comment title consistent Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 14/24] RISC-V: Use memory_region_is_ram in pte update Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 15/24] RISC-V: Remove EM_RISCV ELF_MACHINE indirection Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 16/24] RISC-V: Hardwire satp to 0 for no-mmu case Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 17/24] RISC-V: Remove braces from satp case statement Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 18/24] RISC-V: riscv-qemu port supports sv39 and sv48 Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 19/24] RISC-V: vectored traps are optional Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 20/24] RISC-V: No traps on writes to misa, minstret, mcycle Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 21/24] RISC-V: Remove support for adhoc X_COP interrupt Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 22/24] RISC-V: Convert cpu definition towards future model Michael Clark
2018-03-21 20:46 ` [Qemu-devel] [PULL 23/24] RISC-V: Clear mtval/stval on exceptions without info Michael Clark
2018-03-21 20:47 ` [Qemu-devel] [PULL 24/24] RISC-V: Remove erroneous comment from translate.c Michael Clark
2018-03-24 18:54 ` [Qemu-devel] [PULL 00/24] RISC-V: Post-merge spec conformance and cleanup v5 Michael Clark
2018-03-24 19:06 ` Michael Clark
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