[Qemu-devel] [PULL 0/2] RISC-V: Important fixes for QEMU 2.12

[Michael Clark <mjc@sifive.com>]

The following changes since commit 043289bef4d9c0d277c45695c676a6cc9fca48a0:

  Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20180328' into staging (2018-03-28 13:30:10 +0100)

are available in the git repository at:

  https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-2.12-important-fixes

for you to fetch changes up to 33b4f859f1e1ea6722d10c3e9c0e3d85afb44ff4:

  RISC-V: Fix incorrect disassembly for addiw (2018-03-28 11:12:02 -0700)

----------------------------------------------------------------
RISC-V: Important fixes for QEMU 2.12

This series includes changes that are considered important.
i.e. correct user-visible bugs that are exercised by common
operations such as -cpu list (CPU model changes) or -d in_asm
(fix for disassembly of addiw)

----------------------------------------------------------------
Michael Clark (2):
      RISC-V: Convert cpu definition to future model
      RISC-V: Fix incorrect disassembly for addiw

 disas/riscv.c      |   2 +-
 target/riscv/cpu.c | 123 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++---------------------------------------------------
 2 files changed, 70 insertions(+), 55 deletions(-)