From: Aaron Lindsay <alindsay@codeaurora.org>
To: qemu-arm@nongnu.org, Peter Maydell <peter.maydell@linaro.org>,
Alistair Francis <alistair.francis@xilinx.com>,
Wei Huang <wei@redhat.com>,
Peter Crosthwaite <crosthwaite.peter@gmail.com>
Cc: qemu-devel@nongnu.org,
Michael Spradling <mspradli@codeaurora.org>,
Digant Desai <digantd@codeaurora.org>,
Aaron Lindsay <alindsay@codeaurora.org>
Subject: [Qemu-devel] [PATCH v4 05/21] target/arm: Fetch GICv3 state directly from CPUARMState
Date: Tue, 17 Apr 2018 16:37:49 -0400 [thread overview]
Message-ID: <1523997485-1905-6-git-send-email-alindsay@codeaurora.org> (raw)
In-Reply-To: <1523997485-1905-1-git-send-email-alindsay@codeaurora.org>
This eliminates the need for fetching it from el_change_hook_opaque, and
allows for supporting multiple el_change_hooks without having to hack
something together to find the registered opaque belonging to GICv3.
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gicv3_cpuif.c | 10 ++--------
target/arm/cpu.h | 10 ----------
2 files changed, 2 insertions(+), 18 deletions(-)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 26f5eed..cb9a3a5 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -29,11 +29,7 @@ void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s)
static GICv3CPUState *icc_cs_from_env(CPUARMState *env)
{
- /* Given the CPU, find the right GICv3CPUState struct.
- * Since we registered the CPU interface with the EL change hook as
- * the opaque pointer, we can just directly get from the CPU to it.
- */
- return arm_get_el_change_hook_opaque(arm_env_get_cpu(env));
+ return env->gicv3state;
}
static bool gicv3_use_ns_bank(CPUARMState *env)
@@ -2615,9 +2611,7 @@ void gicv3_init_cpuif(GICv3State *s)
* it might be with code translated by CPU 0 but run by CPU 1, in
* which case we'd get the wrong value.
* So instead we define the regs with no ri->opaque info, and
- * get back to the GICv3CPUState from the ARMCPU by reading back
- * the opaque pointer from the el_change_hook, which we're going
- * to need to register anyway.
+ * get back to the GICv3CPUState from the CPUARMState.
*/
define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
if (arm_feature(&cpu->env, ARM_FEATURE_EL2)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 04041db..ff349f5 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2915,16 +2915,6 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook,
void *opaque);
/**
- * arm_get_el_change_hook_opaque:
- * Return the opaque data that will be used by the el_change_hook
- * for this CPU.
- */
-static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu)
-{
- return cpu->el_change_hook_opaque;
-}
-
-/**
* aa32_vfp_dreg:
* Return a pointer to the Dn register within env in 32-bit mode.
*/
--
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
next prev parent reply other threads:[~2018-04-17 20:39 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-17 20:37 [Qemu-devel] [PATCH v4 00/21] More fully implement ARM PMUv3 Aaron Lindsay
2018-04-17 20:37 ` [Qemu-devel] [PATCH v4 01/21] target/arm: Check PMCNTEN for whether PMCCNTR is enabled Aaron Lindsay
2018-04-17 20:37 ` [Qemu-devel] [PATCH v4 02/21] target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0 Aaron Lindsay
2018-04-17 20:37 ` [Qemu-devel] [PATCH v4 03/21] target/arm: Reorganize PMCCNTR accesses Aaron Lindsay
2018-04-20 10:17 ` Peter Maydell
2018-06-22 13:50 ` Aaron Lindsay
2018-06-22 14:08 ` Peter Maydell
2018-06-22 20:36 ` Aaron Lindsay
2018-04-20 10:41 ` Peter Maydell
2018-04-17 20:37 ` [Qemu-devel] [PATCH v4 04/21] target/arm: Mask PMU register writes based on PMCR_EL0.N Aaron Lindsay
2018-04-17 20:37 ` Aaron Lindsay [this message]
2018-04-17 20:37 ` [Qemu-devel] [PATCH v4 06/21] target/arm: Support multiple EL change hooks Aaron Lindsay
2018-04-17 20:37 ` [Qemu-devel] [PATCH v4 07/21] target/arm: Add pre-EL " Aaron Lindsay
2018-04-17 20:37 ` [Qemu-devel] [PATCH v4 08/21] target/arm: Allow EL change hooks to do IO Aaron Lindsay
2018-04-17 20:37 ` [Qemu-devel] [PATCH v4 09/21] target/arm: Fix bitmask for PMCCFILTR writes Aaron Lindsay
2018-04-17 20:37 ` [Qemu-devel] [PATCH v4 10/21] target/arm: Filter cycle counter based on PMCCFILTR_EL0 Aaron Lindsay
2018-04-17 20:37 ` [Qemu-devel] [PATCH v4 11/21] target/arm: Allow AArch32 access for PMCCFILTR Aaron Lindsay
2018-04-17 20:37 ` [Qemu-devel] [PATCH v4 12/21] target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide Aaron Lindsay
2018-04-17 20:37 ` [Qemu-devel] [PATCH v4 13/21] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions Aaron Lindsay
2018-04-17 20:37 ` [Qemu-devel] [PATCH v4 14/21] target/arm: Implement PMOVSSET Aaron Lindsay
2018-04-17 20:37 ` [Qemu-devel] [PATCH v4 15/21] target/arm: Add array for supported PMU events, generate PMCEID[01] Aaron Lindsay
2018-04-17 20:38 ` [Qemu-devel] [PATCH v4 16/21] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER Aaron Lindsay
2018-04-17 20:38 ` [Qemu-devel] [PATCH v4 17/21] target/arm: PMU: Add instruction and cycle events Aaron Lindsay
2018-04-17 20:38 ` [Qemu-devel] [PATCH v4 18/21] target/arm: PMU: Set PMCR.N to 4 Aaron Lindsay
2018-04-17 20:38 ` [Qemu-devel] [PATCH v4 19/21] target/arm: Implement PMSWINC Aaron Lindsay
2018-04-17 20:38 ` [Qemu-devel] [PATCH v4 20/21] target/arm: Mark PMINTENSET accesses as possibly doing IO Aaron Lindsay
2018-04-17 20:38 ` [Qemu-devel] [PATCH v4 21/21] target/arm: Send interrupts on PMU counter overflow Aaron Lindsay
2018-04-18 14:31 ` Aaron Lindsay
2018-04-20 10:55 ` [Qemu-devel] [PATCH v4 00/21] More fully implement ARM PMUv3 Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1523997485-1905-6-git-send-email-alindsay@codeaurora.org \
--to=alindsay@codeaurora.org \
--cc=alistair.francis@xilinx.com \
--cc=crosthwaite.peter@gmail.com \
--cc=digantd@codeaurora.org \
--cc=mspradli@codeaurora.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=wei@redhat.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).