From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 85527C83F1A for ; Mon, 14 Jul 2025 23:23:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ubSMX-0003c1-C2; Mon, 14 Jul 2025 19:13:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ubSJX-00061r-Px for qemu-devel@nongnu.org; Mon, 14 Jul 2025 19:10:33 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ubSJV-00063x-5H for qemu-devel@nongnu.org; Mon, 14 Jul 2025 19:10:27 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1752534624; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0emX3foBSaMfgiHljy/XlvaxHB8yz/2mJJkSgtv0EAA=; b=Z+DWzhXsoURcVKOACl9Z+CwMz6j8gumSrp3ztHrnmxlnWY8YVpDcZr5mFznG0j14/fjn2k slHDtoDRoWenXSu+ao0qBttjzTvXVzlfbcWcGAEnaCLLwyzqRLYv61xqGqYCrgqL5BpqQE m/MGRS+Q0Oiq5VGalTT9mIHNkIdfWtw= Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-664-E2FnStoYMW2rkYELmxUqBQ-1; Mon, 14 Jul 2025 19:10:23 -0400 X-MC-Unique: E2FnStoYMW2rkYELmxUqBQ-1 X-Mimecast-MFC-AGG-ID: E2FnStoYMW2rkYELmxUqBQ_1752534622 Received: by mail-wr1-f72.google.com with SMTP id ffacd0b85a97d-3a4eee2398bso2324268f8f.1 for ; Mon, 14 Jul 2025 16:10:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752534622; x=1753139422; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=0emX3foBSaMfgiHljy/XlvaxHB8yz/2mJJkSgtv0EAA=; b=hMnUaxJxSDtpTJ2pqrKsaLoB2LZHOoVGO0Obzu9QkmgvEBsXBVl0svxMGlGGOaQvMJ ABDeI6wGWhT/lRfiDYmiYwlvlL+PjrBztKdO2QVK+KKduT9Ak9vsyLpMF2vIeLZ1/NDW Rz5awvk1pf4zR8MEWX7jT1JjnOV34zbpQEjOaejv1Qs2x7qS/HQzRArcvOpeWamgYQlU wZDkr1mnkk+uGwqKL1kxVKlZMi8jv+uqxytXmQbKzxYN+U+k4r6PSwAlbZH5ulo87S3U tqziBmFQVZVRHjuT/2PJM5Jm18gpn6taXKEALx46NOYSEtpQVVux8RK1jklOjjNDuhQy X+HQ== X-Gm-Message-State: AOJu0Yz8+QbfUVU6DrwUtx6znIxKwqtfOoTar0r3FCQgsKEydzYY8nll GfOY+FnObgBfSqLmG9fHTosSJ1Pi4CQjZg7uOuCROEDv8zBrv7yzu7qZSg36N2LZLIgio0/jQW5 JsQ9QMXZBYHih+HtOxoLbw56cKBa3WkduJpD30SbXVKhXoBSg25Jq1MqKd2+ROJpn+NjkxfLC0R t+cEng0D/wTluah/TXGuwZIepjvq5C6VeqDQ== X-Gm-Gg: ASbGncshZMofSajnxXmbL81eCatmmJhhhDt8jZrgf2PfRHHjMGSnhy2veHzsVhkOSmQ dDkEWJtGCwstPFKyfZaYwUuEiNOd+LZxgzRcOTHiMIbb8sbZ1+8eKQuZx8Bn1GrtuLkpZNvKsrH 0CeVLlXSrakMPiD8plJVOz4anlH4CJ7vEq+Jmu7wseHxqhI1NJag8S0tEFDKMUd+kvMDbH/LUNa Bo00f5S015asQJBnuSq5jOyGdAGzcmxt9sik+RhhbuZnzbHFR7dWejchYjFj/10eIbVLaQN7RoF z1NGSWull1HwKUtEPJw09QxyxdYVlkvc X-Received: by 2002:a05:6000:4025:b0:3b4:9b82:d432 with SMTP id ffacd0b85a97d-3b5f338ff26mr11358435f8f.0.1752534621722; Mon, 14 Jul 2025 16:10:21 -0700 (PDT) X-Google-Smtp-Source: AGHT+IESPjNHlATpk2d0DtlU8n6DPaL1vZPayEsym3jQBjtV47SLr7rFPm62KmGXjS/O4t81D0mr3A== X-Received: by 2002:a05:6000:4025:b0:3b4:9b82:d432 with SMTP id ffacd0b85a97d-3b5f338ff26mr11358408f8f.0.1752534621196; Mon, 14 Jul 2025 16:10:21 -0700 (PDT) Received: from redhat.com ([2a0d:6fc0:150d:fc00:de3:4725:47c6:6809]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b5e8e26938sm13407891f8f.89.2025.07.14.16.10.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Jul 2025 16:10:20 -0700 (PDT) Date: Mon, 14 Jul 2025 19:10:19 -0400 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Anisa Su , Fan Ni , Jonathan Cameron Subject: [PULL 93/97] hw/cxl: mailbox-utils: 0x5602 - FMAPI Set DC Region Config Message-ID: <15239e2f76f262d6692aa651cafdd1f77a8970c9.1752534227.git.mst@redhat.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Anisa Su FM DCD Management command 0x5602 implemented per CXL r3.2 Spec Section 7.6.7.6.3 Reviewed-by: Fan Ni Signed-off-by: Anisa Su Signed-off-by: Jonathan Cameron Message-Id: <20250714174509.1984430-8-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/cxl/cxl_device.h | 3 ++ include/hw/cxl/cxl_mailbox.h | 6 +++ hw/cxl/cxl-mailbox-utils.c | 87 ++++++++++++++++++++++++++++++++++++ hw/mem/cxl_type3.c | 6 +-- 4 files changed, 99 insertions(+), 3 deletions(-) diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 42ae5b7479..c836fc17f0 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -721,4 +721,7 @@ void ct3_clear_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa, uint64_t len); bool ct3_test_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa, uint64_t len); +void cxl_assign_event_header(CXLEventRecordHdr *hdr, + const QemuUUID *uuid, uint32_t flags, + uint8_t length, uint64_t timestamp); #endif diff --git a/include/hw/cxl/cxl_mailbox.h b/include/hw/cxl/cxl_mailbox.h index 9008402d1c..a05d7cb5b7 100644 --- a/include/hw/cxl/cxl_mailbox.h +++ b/include/hw/cxl/cxl_mailbox.h @@ -8,6 +8,7 @@ #ifndef CXL_MAILBOX_H #define CXL_MAILBOX_H +#define CXL_MBOX_CONFIG_CHANGE_COLD_RESET (1) #define CXL_MBOX_IMMEDIATE_CONFIG_CHANGE (1 << 1) #define CXL_MBOX_IMMEDIATE_DATA_CHANGE (1 << 2) #define CXL_MBOX_IMMEDIATE_POLICY_CHANGE (1 << 3) @@ -15,5 +16,10 @@ #define CXL_MBOX_SECURITY_STATE_CHANGE (1 << 5) #define CXL_MBOX_BACKGROUND_OPERATION (1 << 6) #define CXL_MBOX_BACKGROUND_OPERATION_ABORT (1 << 7) +#define CXL_MBOX_SECONDARY_MBOX_SUPPORTED (1 << 8) +#define CXL_MBOX_REQUEST_ABORT_BACKGROUND_OP_SUPPORTED (1 << 9) +#define CXL_MBOX_CEL_10_TO_11_VALID (1 << 10) +#define CXL_MBOX_CONFIG_CHANGE_CONV_RESET (1 << 11) +#define CXL_MBOX_CONFIG_CHANGE_CXL_RESET (1 << 12) #endif diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index bf1710b251..b4a0f7d664 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -18,6 +18,7 @@ #include "hw/pci/pci.h" #include "hw/pci-bridge/cxl_upstream_port.h" #include "qemu/cutils.h" +#include "qemu/host-utils.h" #include "qemu/log.h" #include "qemu/units.h" #include "qemu/uuid.h" @@ -121,6 +122,7 @@ enum { FMAPI_DCD_MGMT = 0x56, #define GET_DCD_INFO 0x0 #define GET_HOST_DC_REGION_CONFIG 0x1 + #define SET_DC_REGION_CONFIG 0x2 }; /* CCI Message Format CXL r3.1 Figure 7-19 */ @@ -3390,6 +3392,84 @@ static CXLRetCode cmd_fm_get_host_dc_region_config(const struct cxl_cmd *cmd, return CXL_MBOX_SUCCESS; } +/* CXL r3.2 section 7.6.7.6.3: Set Host DC Region Configuration (Opcode 5602) */ +static CXLRetCode cmd_fm_set_dc_region_config(const struct cxl_cmd *cmd, + uint8_t *payload_in, + size_t len_in, + uint8_t *payload_out, + size_t *len_out, + CXLCCI *cci) +{ + struct { + uint8_t reg_id; + uint8_t rsvd[3]; + uint64_t block_sz; + uint8_t flags; + uint8_t rsvd2[3]; + } QEMU_PACKED *in = (void *)payload_in; + CXLType3Dev *ct3d = CXL_TYPE3(cci->d); + CXLEventDynamicCapacity dcEvent = {}; + CXLDCRegion *region = &ct3d->dc.regions[in->reg_id]; + + /* + * CXL r3.2 7.6.7.6.3: Set DC Region Configuration + * This command shall fail with Unsupported when the Sanitize on Release + * field does not match the region’s configuration... and the device + * does not support reconfiguration of the Sanitize on Release setting. + * + * Currently not reconfigurable, so always fail if sanitize bit (bit 0) + * doesn't match. + */ + if ((in->flags & 0x1) != (region->flags & 0x1)) { + return CXL_MBOX_UNSUPPORTED; + } + + if (in->reg_id >= DCD_MAX_NUM_REGION) { + return CXL_MBOX_UNSUPPORTED; + } + + /* Check that no extents are in the region being reconfigured */ + if (!bitmap_empty(region->blk_bitmap, region->len / region->block_size)) { + return CXL_MBOX_UNSUPPORTED; + } + + /* Check that new block size is supported */ + if (!is_power_of_2(in->block_sz) || + !(in->block_sz & region->supported_blk_size_bitmask)) { + return CXL_MBOX_INVALID_INPUT; + } + + /* Return success if new block size == current block size */ + if (in->block_sz == region->block_size) { + return CXL_MBOX_SUCCESS; + } + + /* Free bitmap and create new one for new block size. */ + qemu_mutex_lock(®ion->bitmap_lock); + g_free(region->blk_bitmap); + region->blk_bitmap = bitmap_new(region->len / in->block_sz); + qemu_mutex_unlock(®ion->bitmap_lock); + region->block_size = in->block_sz; + + /* Create event record and insert into event log */ + cxl_assign_event_header(&dcEvent.hdr, + &dynamic_capacity_uuid, + (1 << CXL_EVENT_TYPE_INFO), + sizeof(dcEvent), + cxl_device_get_timestamp(&ct3d->cxl_dstate)); + dcEvent.type = DC_EVENT_REGION_CONFIG_UPDATED; + dcEvent.validity_flags = 1; + dcEvent.host_id = 0; + dcEvent.updated_region_id = in->reg_id; + + if (cxl_event_insert(&ct3d->cxl_dstate, + CXL_EVENT_TYPE_DYNAMIC_CAP, + (CXLEventRecordRaw *)&dcEvent)) { + cxl_event_irq_assert(ct3d); + } + return CXL_MBOX_SUCCESS; +} + static const struct cxl_cmd cxl_cmd_set[256][256] = { [INFOSTAT][BACKGROUND_OPERATION_ABORT] = { "BACKGROUND_OPERATION_ABORT", cmd_infostat_bg_op_abort, 0, 0 }, @@ -3508,6 +3588,13 @@ static const struct cxl_cmd cxl_cmd_set_fm_dcd[256][256] = { cmd_fm_get_dcd_info, 0, 0 }, [FMAPI_DCD_MGMT][GET_HOST_DC_REGION_CONFIG] = { "GET_HOST_DC_REGION_CONFIG", cmd_fm_get_host_dc_region_config, 4, 0 }, + [FMAPI_DCD_MGMT][SET_DC_REGION_CONFIG] = { "SET_DC_REGION_CONFIG", + cmd_fm_set_dc_region_config, 16, + (CXL_MBOX_CONFIG_CHANGE_COLD_RESET | + CXL_MBOX_CONFIG_CHANGE_CONV_RESET | + CXL_MBOX_CONFIG_CHANGE_CXL_RESET | + CXL_MBOX_IMMEDIATE_CONFIG_CHANGE | + CXL_MBOX_IMMEDIATE_DATA_CHANGE) }, }; /* diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index a7a1857a0c..4a45b4510e 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -1590,9 +1590,9 @@ void qmp_cxl_inject_correctable_error(const char *path, CxlCorErrorType type, pcie_aer_inject_error(PCI_DEVICE(obj), &err); } -static void cxl_assign_event_header(CXLEventRecordHdr *hdr, - const QemuUUID *uuid, uint32_t flags, - uint8_t length, uint64_t timestamp) +void cxl_assign_event_header(CXLEventRecordHdr *hdr, + const QemuUUID *uuid, uint32_t flags, + uint8_t length, uint64_t timestamp) { st24_le_p(&hdr->flags, flags); hdr->length = length; -- MST