From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45029) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBjjg-0000L6-2d for qemu-devel@nongnu.org; Thu, 26 Apr 2018 12:27:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBjjc-0003Fu-J3 for qemu-devel@nongnu.org; Thu, 26 Apr 2018 12:27:08 -0400 Received: from mail-sn1nam01on0075.outbound.protection.outlook.com ([104.47.32.75]:12173 helo=NAM01-SN1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBjjc-0003Be-E7 for qemu-devel@nongnu.org; Thu, 26 Apr 2018 12:27:04 -0400 From: Babu Moger Date: Thu, 26 Apr 2018 11:26:42 -0500 Message-Id: <1524760009-24710-3-git-send-email-babu.moger@amd.com> In-Reply-To: <1524760009-24710-1-git-send-email-babu.moger@amd.com> References: <1524760009-24710-1-git-send-email-babu.moger@amd.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v7 2/9] i386: Add cache information in X86CPUDefinition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: mst@redhat.com, marcel@redhat.com, pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com, mtosatti@redhat.com Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, kash@tripleback.net, geoff@hostfission.com, babu.moger@amd.com Add cache information in X86CPUDefinition and CPUX86State. Signed-off-by: Babu Moger Tested-by: Geoffrey McRae --- target/i386/cpu.c | 4 ++++ target/i386/cpu.h | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b6c1592..a518a0f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1105,6 +1105,7 @@ struct X86CPUDefinition { int stepping; FeatureWordArray features; const char *model_id; + CPUCaches cache_info; }; static X86CPUDefinition builtin_x86_defs[] = { @@ -3242,6 +3243,9 @@ static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp) env->features[w] = def->features[w]; } + /* Load Cache information from the X86CPUDefinition */ + memcpy(&env->cache_info, &def->cache_info, sizeof(CPUCaches)); + /* Special cases not set in the X86CPUDefinition structs: */ /* TODO: in-kernel irqchip for hvf */ if (kvm_enabled()) { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index fa03e2c..1213bb7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1096,6 +1096,13 @@ typedef struct CPUCacheInfo { } CPUCacheInfo; +typedef struct CPUCaches { + bool valid; + CPUCacheInfo l1d_cache; + CPUCacheInfo l1i_cache; + CPUCacheInfo l2_cache; + CPUCacheInfo l3_cache; +} CPUCaches; typedef struct CPUX86State { /* standard registers */ @@ -1282,6 +1289,7 @@ typedef struct CPUX86State { /* Features that were explicitly enabled/disabled */ FeatureWordArray user_features; uint32_t cpuid_model[12]; + CPUCaches cache_info; /* MTRRs */ uint64_t mtrr_fixed[11]; -- 2.7.4