From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45076) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBjjj-0000Qo-S9 for qemu-devel@nongnu.org; Thu, 26 Apr 2018 12:27:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBjjf-0003JB-Sw for qemu-devel@nongnu.org; Thu, 26 Apr 2018 12:27:11 -0400 Received: from mail-sn1nam01on0066.outbound.protection.outlook.com ([104.47.32.66]:63008 helo=NAM01-SN1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fBjjf-0003Io-M4 for qemu-devel@nongnu.org; Thu, 26 Apr 2018 12:27:07 -0400 From: Babu Moger Date: Thu, 26 Apr 2018 11:26:45 -0500 Message-Id: <1524760009-24710-6-git-send-email-babu.moger@amd.com> In-Reply-To: <1524760009-24710-1-git-send-email-babu.moger@amd.com> References: <1524760009-24710-1-git-send-email-babu.moger@amd.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v7 5/9] i386: Use the statically loaded cache definitions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: mst@redhat.com, marcel@redhat.com, pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com, mtosatti@redhat.com Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, kash@tripleback.net, geoff@hostfission.com, babu.moger@amd.com Use the statically loaded cache definitions if available and legacy-cache parameter is not set. Signed-off-by: Babu Moger Tested-by: Geoffrey McRae --- target/i386/cpu.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a27b658..56d2f0b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3941,8 +3941,13 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \ (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); - *ecx = encode_cache_cpuid80000005(&l1d_cache_amd); - *edx = encode_cache_cpuid80000005(&l1i_cache_amd); + if (env->cache_info.valid && !cpu->legacy_cache) { + *ecx = encode_cache_cpuid80000005(&env->cache_info.l1d_cache); + *edx = encode_cache_cpuid80000005(&env->cache_info.l1i_cache); + } else { + *ecx = encode_cache_cpuid80000005(&l1d_cache_amd); + *edx = encode_cache_cpuid80000005(&l1i_cache_amd); + } break; case 0x80000006: /* cache info (L2 cache) */ @@ -3958,9 +3963,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, (L2_DTLB_4K_ENTRIES << 16) | \ (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \ (L2_ITLB_4K_ENTRIES); - encode_cache_cpuid80000006(&l2_cache_amd, - cpu->enable_l3_cache ? &l3_cache : NULL, - ecx, edx); + if (env->cache_info.valid && !cpu->legacy_cache) { + encode_cache_cpuid80000006(&env->cache_info.l2_cache, + cpu->enable_l3_cache ? + &env->cache_info.l3_cache : NULL, + ecx, edx); + } else { + encode_cache_cpuid80000006(&l2_cache_amd, + cpu->enable_l3_cache ? &l3_cache : NULL, + ecx, edx); + } break; case 0x80000007: *eax = 0; -- 2.7.4