From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Cc: patches@groups.riscv.org, Michael Clark <mjc@sifive.com>,
Palmer Dabbelt <palmer@sifive.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Peter Maydell <peter.maydell@linaro.org>
Subject: [Qemu-devel] [PATCH] RISC-V: Fix missing break statement in disassembler
Date: Mon, 30 Apr 2018 11:18:08 +1200 [thread overview]
Message-ID: <1525043888-90983-1-git-send-email-mjc@sifive.com> (raw)
This fixes an issue when disassembling rv128 c.sqsp,
where the code erroneously fell through to c.swsp.
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
---
disas/riscv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 74ad16eacdd3..ea19f6fbe2b1 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1470,8 +1470,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
if (isa == rv128) {
op = rv_op_c_sqsp;
} else {
- op = rv_op_c_fsdsp; break;
+ op = rv_op_c_fsdsp;
}
+ break;
case 6: op = rv_op_c_swsp; break;
case 7:
if (isa == rv32) {
--
2.7.0
next reply other threads:[~2018-04-29 23:19 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-29 23:18 Michael Clark [this message]
2018-05-01 18:41 ` [Qemu-devel] [PATCH] RISC-V: Fix missing break statement in disassembler Richard Henderson
2018-05-01 22:54 ` Philippe Mathieu-Daudé
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