* [Qemu-devel] [PATCH] RISC-V: Fix missing break statement in disassembler
@ 2018-04-29 23:18 Michael Clark
2018-05-01 18:41 ` Richard Henderson
2018-05-01 22:54 ` Philippe Mathieu-Daudé
0 siblings, 2 replies; 3+ messages in thread
From: Michael Clark @ 2018-04-29 23:18 UTC (permalink / raw)
To: qemu-devel
Cc: patches, Michael Clark, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann, Peter Maydell
This fixes an issue when disassembling rv128 c.sqsp,
where the code erroneously fell through to c.swsp.
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
---
disas/riscv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 74ad16eacdd3..ea19f6fbe2b1 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1470,8 +1470,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
if (isa == rv128) {
op = rv_op_c_sqsp;
} else {
- op = rv_op_c_fsdsp; break;
+ op = rv_op_c_fsdsp;
}
+ break;
case 6: op = rv_op_c_swsp; break;
case 7:
if (isa == rv32) {
--
2.7.0
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [Qemu-devel] [PATCH] RISC-V: Fix missing break statement in disassembler
2018-04-29 23:18 [Qemu-devel] [PATCH] RISC-V: Fix missing break statement in disassembler Michael Clark
@ 2018-05-01 18:41 ` Richard Henderson
2018-05-01 22:54 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 3+ messages in thread
From: Richard Henderson @ 2018-05-01 18:41 UTC (permalink / raw)
To: Michael Clark, qemu-devel
Cc: Peter Maydell, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, patches
On 04/29/2018 04:18 PM, Michael Clark wrote:
> This fixes an issue when disassembling rv128 c.sqsp,
> where the code erroneously fell through to c.swsp.
>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> ---
> disas/riscv.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH] RISC-V: Fix missing break statement in disassembler
2018-04-29 23:18 [Qemu-devel] [PATCH] RISC-V: Fix missing break statement in disassembler Michael Clark
2018-05-01 18:41 ` Richard Henderson
@ 2018-05-01 22:54 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 3+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-05-01 22:54 UTC (permalink / raw)
To: Michael Clark, qemu-devel
Cc: Peter Maydell, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, patches
On 04/29/2018 08:18 PM, Michael Clark wrote:
> This fixes an issue when disassembling rv128 c.sqsp,
> where the code erroneously fell through to c.swsp.
>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> disas/riscv.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 74ad16eacdd3..ea19f6fbe2b1 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1470,8 +1470,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> if (isa == rv128) {
> op = rv_op_c_sqsp;
> } else {
> - op = rv_op_c_fsdsp; break;
> + op = rv_op_c_fsdsp;
> }
> + break;
> case 6: op = rv_op_c_swsp; break;
> case 7:
> if (isa == rv32) {
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2018-04-29 23:18 [Qemu-devel] [PATCH] RISC-V: Fix missing break statement in disassembler Michael Clark
2018-05-01 18:41 ` Richard Henderson
2018-05-01 22:54 ` Philippe Mathieu-Daudé
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