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From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Cc: patches@groups.riscv.org, Michael Clark <mjc@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Palmer Dabbelt <palmer@sifive.com>,
	Alistair Francis <Alistair.Francis@wdc.com>
Subject: [Qemu-devel] [PULL 18/20] RISC-V: Make mtvec/stvec ignore vectored traps
Date: Sun,  6 May 2018 11:35:23 +1200	[thread overview]
Message-ID: <1525563325-62963-19-git-send-email-mjc@sifive.com> (raw)
In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com>

Vectored traps for asynchrounous interrupts are optional.
The mtvec/stvec mode field is WARL and hence does not trap
if an illegal value is written. Illegal values are ignored.

Later we can add RISCV_FEATURE_VECTORED_TRAPS however
until then the correct behavior for WARL (Write Any, Read
Legal) fields is to drop writes to unsupported bits.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
---
 target/riscv/op_helper.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 3512462f4fd8..af0c52a48418 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -287,11 +287,12 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
         env->sepc = val_to_write;
         break;
     case CSR_STVEC:
-        if (val_to_write & 1) {
+        /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
+        if ((val_to_write & 3) == 0) {
+            env->stvec = val_to_write >> 2 << 2;
+        } else {
             qemu_log_mask(LOG_UNIMP, "CSR_STVEC: vectored traps not supported");
-            goto do_illegal;
         }
-        env->stvec = val_to_write >> 2 << 2;
         break;
     case CSR_SCOUNTEREN:
         if (env->priv_ver >= PRIV_VERSION_1_10_0) {
@@ -313,11 +314,12 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
         env->mepc = val_to_write;
         break;
     case CSR_MTVEC:
-        if (val_to_write & 1) {
+        /* bits [1:0] indicate mode; 0 = direct, 1 = vectored, 2 >= reserved */
+        if ((val_to_write & 3) == 0) {
+            env->mtvec = val_to_write >> 2 << 2;
+        } else {
             qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: vectored traps not supported");
-            goto do_illegal;
         }
-        env->mtvec = val_to_write >> 2 << 2;
         break;
     case CSR_MCOUNTEREN:
         if (env->priv_ver >= PRIV_VERSION_1_10_0) {
-- 
2.7.0

  parent reply	other threads:[~2018-05-05 23:37 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-05 23:35 [Qemu-devel] [PULL 00/20] RISC-V: QEMU 2.13 Privileged ISA emulation updates Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 01/20] RISC-V: Replace hardcoded constants with enum values Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 02/20] RISC-V: Make virt board description match spike Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 03/20] RISC-V: Use ROM base address and size from memmap Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 04/20] RISC-V: Remove identity_translate from load_elf Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 05/20] RISC-V: Remove unused class definitions Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 06/20] RISC-V: Include instruction hex in disassembly Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 07/20] RISC-V: Fix missing break statement in disassembler Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 08/20] RISC-V: Make some header guards more specific Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 09/20] RISC-V: Make virt header comment title consistent Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 10/20] RISC-V: Remove EM_RISCV ELF_MACHINE indirection Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 11/20] RISC-V: Remove erroneous comment from translate.c Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 12/20] RISC-V: Update E and I extension order Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 13/20] RISC-V: Hardwire satp to 0 for no-mmu case Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 14/20] RISC-V: Clear mtval/stval on exceptions without info Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 15/20] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10 Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 16/20] RISC-V: Use [ms]counteren CSRs " Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 17/20] RISC-V: Add mcycle/minstret support for -icount auto Michael Clark
2018-05-05 23:35 ` Michael Clark [this message]
2018-05-05 23:35 ` [Qemu-devel] [PULL 19/20] RISC-V: No traps on writes to misa, minstret, mcycle Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 20/20] RISC-V: Mark ROM read-only after copying in code Michael Clark
2018-05-08 13:22 ` [Qemu-devel] [PULL 00/20] RISC-V: QEMU 2.13 Privileged ISA emulation updates Peter Maydell
2018-05-08 22:52   ` Michael Clark

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