From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Cc: patches@groups.riscv.org, Michael Clark <mjc@sifive.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmer@sifive.com>,
Alistair Francis <Alistair.Francis@wdc.com>
Subject: [Qemu-devel] [PULL 19/20] RISC-V: No traps on writes to misa, minstret, mcycle
Date: Sun, 6 May 2018 11:35:24 +1200 [thread overview]
Message-ID: <1525563325-62963-20-git-send-email-mjc@sifive.com> (raw)
In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com>
These fields are marked WARL (Write Any Values, Reads
Legal Values) in the RISC-V Privileged Architecture
Specification so instead of raising exceptions,
illegal writes are silently dropped.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
---
target/riscv/op_helper.c | 25 +++++++++++++------------
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index af0c52a48418..3abf52453cfc 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -213,17 +213,19 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
break;
}
case CSR_MINSTRET:
- qemu_log_mask(LOG_UNIMP, "CSR_MINSTRET: write not implemented");
- goto do_illegal;
+ /* minstret is WARL so unsupported writes are ignored */
+ break;
case CSR_MCYCLE:
- qemu_log_mask(LOG_UNIMP, "CSR_MCYCLE: write not implemented");
- goto do_illegal;
+ /* mcycle is WARL so unsupported writes are ignored */
+ break;
+#if defined(TARGET_RISCV32)
case CSR_MINSTRETH:
- qemu_log_mask(LOG_UNIMP, "CSR_MINSTRETH: write not implemented");
- goto do_illegal;
+ /* minstreth is WARL so unsupported writes are ignored */
+ break;
case CSR_MCYCLEH:
- qemu_log_mask(LOG_UNIMP, "CSR_MCYCLEH: write not implemented");
- goto do_illegal;
+ /* mcycleh is WARL so unsupported writes are ignored */
+ break;
+#endif
case CSR_MUCOUNTEREN:
if (env->priv_ver <= PRIV_VERSION_1_09_1) {
env->scounteren = val_to_write;
@@ -337,10 +339,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
case CSR_MBADADDR:
env->mbadaddr = val_to_write;
break;
- case CSR_MISA: {
- qemu_log_mask(LOG_UNIMP, "CSR_MISA: misa writes not supported");
- goto do_illegal;
- }
+ case CSR_MISA:
+ /* misa is WARL so unsupported writes are ignored */
+ break;
case CSR_PMPCFG0:
case CSR_PMPCFG1:
case CSR_PMPCFG2:
--
2.7.0
next prev parent reply other threads:[~2018-05-05 23:38 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-05 23:35 [Qemu-devel] [PULL 00/20] RISC-V: QEMU 2.13 Privileged ISA emulation updates Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 01/20] RISC-V: Replace hardcoded constants with enum values Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 02/20] RISC-V: Make virt board description match spike Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 03/20] RISC-V: Use ROM base address and size from memmap Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 04/20] RISC-V: Remove identity_translate from load_elf Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 05/20] RISC-V: Remove unused class definitions Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 06/20] RISC-V: Include instruction hex in disassembly Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 07/20] RISC-V: Fix missing break statement in disassembler Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 08/20] RISC-V: Make some header guards more specific Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 09/20] RISC-V: Make virt header comment title consistent Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 10/20] RISC-V: Remove EM_RISCV ELF_MACHINE indirection Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 11/20] RISC-V: Remove erroneous comment from translate.c Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 12/20] RISC-V: Update E and I extension order Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 13/20] RISC-V: Hardwire satp to 0 for no-mmu case Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 14/20] RISC-V: Clear mtval/stval on exceptions without info Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 15/20] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10 Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 16/20] RISC-V: Use [ms]counteren CSRs " Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 17/20] RISC-V: Add mcycle/minstret support for -icount auto Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 18/20] RISC-V: Make mtvec/stvec ignore vectored traps Michael Clark
2018-05-05 23:35 ` Michael Clark [this message]
2018-05-05 23:35 ` [Qemu-devel] [PULL 20/20] RISC-V: Mark ROM read-only after copying in code Michael Clark
2018-05-08 13:22 ` [Qemu-devel] [PULL 00/20] RISC-V: QEMU 2.13 Privileged ISA emulation updates Peter Maydell
2018-05-08 22:52 ` Michael Clark
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