From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54210) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6jb-0003mw-2h for qemu-devel@nongnu.org; Sat, 05 May 2018 19:36:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fF6ja-0003Yg-5H for qemu-devel@nongnu.org; Sat, 05 May 2018 19:36:59 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:41311) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fF6jZ-0003YO-Vo for qemu-devel@nongnu.org; Sat, 05 May 2018 19:36:58 -0400 Received: by mail-pg0-x244.google.com with SMTP id m21-v6so17783729pgv.8 for ; Sat, 05 May 2018 16:36:57 -0700 (PDT) From: Michael Clark Date: Sun, 6 May 2018 11:35:07 +1200 Message-Id: <1525563325-62963-3-git-send-email-mjc@sifive.com> In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com> References: <1525563325-62963-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 02/20] RISC-V: Make virt board description match spike List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@groups.riscv.org, Michael Clark , Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt This makes 'qemu-system-riscv64 -machine help' output more tidy and consistent. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 2480dad11f08..df06fc720755 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -407,7 +407,7 @@ static const TypeInfo riscv_virt_board_device = { static void riscv_virt_board_machine_init(MachineClass *mc) { - mc->desc = "RISC-V VirtIO Board (Privileged spec v1.10)"; + mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)"; mc->init = riscv_virt_board_init; mc->max_cpus = 8; /* hardcoded limit in BBL */ } -- 2.7.0