From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Cc: patches@groups.riscv.org, Michael Clark <mjc@sifive.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-devel] [PULL 03/20] RISC-V: Use ROM base address and size from memmap
Date: Sun, 6 May 2018 11:35:08 +1200 [thread overview]
Message-ID: <1525563325-62963-4-git-send-email-mjc@sifive.com> (raw)
In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com>
Another case of replacing hard coded constants, this time
referring to the definition in the virt machine's memmap.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 4 ++--
include/hw/riscv/virt.h | 2 --
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index df06fc720755..3cc9c8090bfb 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -341,11 +341,11 @@ static void riscv_virt_board_init(MachineState *machine)
};
/* copy in the reset vector */
- copy_le32_to_phys(ROM_BASE, reset_vec, sizeof(reset_vec));
+ copy_le32_to_phys(memmap[VIRT_MROM].base, reset_vec, sizeof(reset_vec));
/* copy in the device tree */
qemu_fdt_dumpdtb(s->fdt, s->fdt_size);
- cpu_physical_memory_write(ROM_BASE + sizeof(reset_vec),
+ cpu_physical_memory_write(memmap[VIRT_MROM].base + sizeof(reset_vec),
s->fdt, s->fdt_size);
/* create PLIC hart topology configuration string */
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 2fbe808da5f6..655e85ddbd3c 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -23,8 +23,6 @@
#define VIRT(obj) \
OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD)
-enum { ROM_BASE = 0x1000 };
-
typedef struct {
/*< private >*/
SysBusDevice parent_obj;
--
2.7.0
next prev parent reply other threads:[~2018-05-05 23:37 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-05 23:35 [Qemu-devel] [PULL 00/20] RISC-V: QEMU 2.13 Privileged ISA emulation updates Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 01/20] RISC-V: Replace hardcoded constants with enum values Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 02/20] RISC-V: Make virt board description match spike Michael Clark
2018-05-05 23:35 ` Michael Clark [this message]
2018-05-05 23:35 ` [Qemu-devel] [PULL 04/20] RISC-V: Remove identity_translate from load_elf Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 05/20] RISC-V: Remove unused class definitions Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 06/20] RISC-V: Include instruction hex in disassembly Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 07/20] RISC-V: Fix missing break statement in disassembler Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 08/20] RISC-V: Make some header guards more specific Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 09/20] RISC-V: Make virt header comment title consistent Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 10/20] RISC-V: Remove EM_RISCV ELF_MACHINE indirection Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 11/20] RISC-V: Remove erroneous comment from translate.c Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 12/20] RISC-V: Update E and I extension order Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 13/20] RISC-V: Hardwire satp to 0 for no-mmu case Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 14/20] RISC-V: Clear mtval/stval on exceptions without info Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 15/20] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10 Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 16/20] RISC-V: Use [ms]counteren CSRs " Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 17/20] RISC-V: Add mcycle/minstret support for -icount auto Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 18/20] RISC-V: Make mtvec/stvec ignore vectored traps Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 19/20] RISC-V: No traps on writes to misa, minstret, mcycle Michael Clark
2018-05-05 23:35 ` [Qemu-devel] [PULL 20/20] RISC-V: Mark ROM read-only after copying in code Michael Clark
2018-05-08 13:22 ` [Qemu-devel] [PULL 00/20] RISC-V: QEMU 2.13 Privileged ISA emulation updates Peter Maydell
2018-05-08 22:52 ` Michael Clark
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