From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org, qemu-trivial@nongnu.org
Cc: patches@groups.riscv.org, Michael Clark <mjc@sifive.com>,
Michael Tokarev <mjt@tls.msk.ru>,
Laurent Vivier <laurent@vivier.eu>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <Alistair.Francis@wdc.com>
Subject: [Qemu-devel] [PATCH v2] elf: Add RISC-V PSABI ELF header defines
Date: Fri, 25 May 2018 19:22:40 +1200 [thread overview]
Message-ID: <1527232960-51123-1-git-send-email-mjc@sifive.com> (raw)
Refer to the RISC-V PSABI specification for details:
- https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
Cc: Michael Tokarev <mjt@tls.msk.ru>
Cc: Laurent Vivier <laurent@vivier.eu>
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
---
include/elf.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index 934dbbd6b3ae..bd0493f43d19 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -1285,6 +1285,14 @@ typedef struct {
#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */
#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */
+/* RISC-V specific definitions. */
+#define EF_RISCV_RVC 0x0001
+#define EF_RISCV_FLOAT_ABI_SINGLE 0x0002
+#define EF_RISCV_FLOAT_ABI_DOUBLE 0x0004
+#define EF_RISCV_FLOAT_ABI_QUAD 0x0006
+#define EF_RISCV_RVE 0x0008
+#define EF_RISCV_TSO 0x0010
+
typedef struct elf32_rel {
Elf32_Addr r_offset;
Elf32_Word r_info;
--
2.7.0
next reply other threads:[~2018-05-25 7:24 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-25 7:22 Michael Clark [this message]
2018-05-25 7:53 ` [Qemu-devel] [PATCH v2] elf: Add RISC-V PSABI ELF header defines Laurent Vivier
2018-05-25 9:25 ` Michael Clark
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