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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4f88aa58d6fsm60724173.89.2025.05.01.14.49.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 01 May 2025 14:49:49 -0700 (PDT) Message-ID: <1528a021-d3ec-495e-a42b-6614d60b0666@linaro.org> Date: Thu, 1 May 2025 23:49:45 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC qemu 1/6] hw/pci-bridge/cxl_root_port: Provide x-speed and x-width properties. To: Jonathan Cameron , mst@redhat.com, Markus Armbruster , qemu-devel@nongnu.org Cc: linuxarm@huawei.com, linux-cxl@vger.kernel.org, marcel.apfelbaum@gmail.com, Dave Jiang , Huang Ying , Michael Roth , fan.ni@samsung.com, Alex Williamson , =?UTF-8?Q?Daniel_P=2E_Berrang=C3=A9?= References: <20240712122414.1448284-1-Jonathan.Cameron@huawei.com> <20240712122414.1448284-2-Jonathan.Cameron@huawei.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240712122414.1448284-2-Jonathan.Cameron@huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::131; envelope-from=philmd@linaro.org; helo=mail-il1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Jonathan and Alex. (This patch is now merged as commit 1478b560902). On 12/7/24 14:24, Jonathan Cameron via wrote: > Approach copied from gen_pcie_root_port.c > Previously the link defaulted to a maximum of 2.5GT/s and 1x. Enable setting > it's maximum values. The actual value after 'training' will depend on the > downstream device configuration. > > Signed-off-by: Jonathan Cameron > --- > hw/pci-bridge/cxl_root_port.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c > index 2dd10239bd..5e2156d7ba 100644 > --- a/hw/pci-bridge/cxl_root_port.c > +++ b/hw/pci-bridge/cxl_root_port.c > @@ -24,6 +24,7 @@ > #include "hw/pci/pcie_port.h" > #include "hw/pci/msi.h" > #include "hw/qdev-properties.h" > +#include "hw/qdev-properties-system.h" > #include "hw/sysbus.h" > #include "qapi/error.h" > #include "hw/cxl/cxl.h" > @@ -206,6 +207,10 @@ static Property gen_rp_props[] = { > -1), > DEFINE_PROP_SIZE("pref64-reserve", CXLRootPort, res_reserve.mem_pref_64, > -1), > + DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot, > + speed, PCIE_LINK_SPEED_64), > + DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, > + width, PCIE_LINK_WIDTH_32), Per the documentation: We commonly use a ``x-`` command name prefix to make lack of stability obvious to human users. Are these properties meant to be stable? You mentioned "Approach copied from gen_pcie_root_port.c". There they were added because of: commit c2a490e344b4e231cf9488c67df7ee46977b1ebe Author: Alex Williamson Date: Wed Dec 12 12:39:43 2018 -0700 pcie: Allow generic PCIe root port to specify link speed and width Allow users to experimentally specify speed and width values for the generic PCIe root port. Defaults remain at 2.5GT/s & x1 for compatiblity with the intent to only support changing defaults via machine types for now. This was 6 years ago, are we still experimenting? > DEFINE_PROP_END_OF_LIST() > }; >