* [Qemu-devel] [PULL v2 00/50] More misc patches for 3.0 soft freeze
@ 2018-07-02 15:45 Paolo Bonzini
2018-07-02 15:45 ` [Qemu-devel] [PULL 07/50] hw: Use IEC binary prefix definitions from "qemu/units.h" Paolo Bonzini
` (4 more replies)
0 siblings, 5 replies; 7+ messages in thread
From: Paolo Bonzini @ 2018-07-02 15:45 UTC (permalink / raw)
To: qemu-devel
The following changes since commit 646f34fa5482e495483de230b4cf0f2ae4fd2781:
tcg: Fix --disable-tcg build breakage (2018-07-02 13:42:05 +0100)
are available in the git repository at:
git://github.com/bonzini/qemu.git tags/for-upstream
for you to fetch changes up to c40d479207b1bb6569ffde06e9a58e85cd529de0:
tcg: simplify !CONFIG_TCG handling of tb_invalidate_* (2018-07-02 15:41:18 +0200)
----------------------------------------------------------------
* IEC units series (Philippe)
* Hyper-V PV TLB flush (Vitaly)
* git archive detection (Daniel)
* host serial passthrough fix (David)
* NPT support for SVM emulation (Jan)
* x86 "info mem" and "info tlb" fix (Doug)
----------------------------------------------------------------
Daniel P. Berrangé (1):
configure: add sanity check to catch builds from "git archive"
Doug Gale (1):
i386/monitor.c: make addresses canonical for "info mem" and "info tlb"
Dr. David Alan Gilbert (1):
serial: Open non-block
Jan Kiszka (1):
target-i386: Add NPT support
Paolo Bonzini (2):
hw/i386: Use the IEC binary prefix definitions
tcg: simplify !CONFIG_TCG handling of tb_invalidate_*
Philippe Mathieu-Daudé (43):
include: Add IEC binary prefixes in "qemu/units.h"
vdi: Use definitions from "qemu/units.h"
x86/cpu: Use definitions from "qemu/units.h"
checkpatch: Recognize IEC binary prefix definitions
hw: Use IEC binary prefix definitions from "qemu/units.h"
hw: Directly use "qemu/units.h" instead of "qemu/cutils.h"
hw/ivshmem: Use the IEC binary prefix definitions
hw/ipack: Use the IEC binary prefix definitions
hw/scsi: Use the IEC binary prefix definitions
hw/smbios: Use the IEC binary prefix definitions
hw/xen: Use the IEC binary prefix definitions
hw/tpm: Use the IEC binary prefix definitions
hw/block: Use the IEC binary prefix definitions
hw/display: Use the IEC binary prefix definitions
hw/misc: Use the IEC binary prefix definitions
hw/riscv: Use the IEC binary prefix definitions
hw/m68k: Use the IEC binary prefix definitions
hw/sparc: Use the IEC binary prefix definitions
hw/s390x: Use the IEC binary prefix definitions
hw/hppa: Use the IEC binary prefix definitions
hw/xtensa: Use the IEC binary prefix definitions
hw/alpha: Use the IEC binary prefix definitions
hw/tricore: Use the IEC binary prefix definitions
hw/microblaze: Use the IEC binary prefix definitions
hw/nios2: Use the IEC binary prefix definitions
hw/cris: Use the IEC binary prefix definitions
hw/lm32: Use the IEC binary prefix definitions
hw/sh4: Use the IEC binary prefix definitions
hw/mips/r4k: Constify params_size
hw/mips: Use the IEC binary prefix definitions
hw/ppc: Use the IEC binary prefix definitions
hw/net: Use the IEC binary prefix definitions
hw/usb: Use the IEC binary prefix definitions
hw/sd: Use the IEC binary prefix definitions
hw/vfio: Use the IEC binary prefix definitions
hw/virtio: Use the IEC binary prefix definitions
hw/rdma: Use the IEC binary prefix definitions
cutils: Do not include "qemu/units.h" directly
monitor: Use the IEC binary prefix definitions
vl: Use the IEC binary prefix definitions
tests/crypto: Use the IEC binary prefix definitions
linux-user: Use the IEC binary prefix definitions
bsd-user: Use the IEC binary prefix definitions
Vitaly Kuznetsov (1):
i386/kvm: add support for Hyper-V TLB flush
accel/stubs/tcg-stub.c | 6 -
block/vdi.c | 7 +-
bsd-user/main.c | 5 +-
chardev/char-serial.c | 3 +-
configure | 18 +++
exec.c | 6 +-
hw/alpha/typhoon.c | 17 ++-
hw/arm/msf2-soc.c | 6 +-
hw/arm/msf2-som.c | 8 +-
hw/block/m25p80.c | 5 +-
hw/block/nvme.c | 3 +-
hw/block/tc58128.c | 3 +-
hw/block/xen_disk.c | 3 +-
hw/core/loader-fit.c | 3 +-
hw/core/machine.c | 4 +-
hw/cris/axis_dev88.c | 3 +-
hw/display/bochs-display.c | 9 +-
hw/display/cirrus_vga.c | 10 +-
hw/display/g364fb.c | 4 +-
hw/display/qxl.c | 30 ++---
hw/display/sm501.c | 16 +--
hw/display/vga-isa-mm.c | 5 +-
hw/display/vga.c | 5 +-
hw/display/virtio-gpu.c | 4 +-
hw/display/vmware_vga.c | 3 +-
hw/display/xenfb.c | 3 +-
hw/hppa/dino.c | 3 +-
hw/hppa/machine.c | 12 +-
hw/i386/acpi-build.c | 4 +-
hw/i386/pc.c | 23 ++--
hw/i386/pc_piix.c | 3 +-
hw/i386/pc_q35.c | 3 +-
hw/i386/pc_sysfw.c | 10 +-
hw/i386/xen/xen-mapcache.c | 3 +-
hw/ipack/tpci200.c | 5 +-
hw/lm32/lm32_boards.c | 13 +-
hw/lm32/milkymist.c | 10 +-
hw/m68k/mcf5208.c | 3 +-
hw/microblaze/petalogix_ml605_mmu.c | 7 +-
hw/microblaze/petalogix_s3adsp1800_mmu.c | 7 +-
hw/mips/boston.c | 30 ++---
hw/mips/mips_fulong2e.c | 7 +-
hw/mips/mips_malta.c | 25 ++--
hw/mips/mips_r4k.c | 15 ++-
hw/misc/auxbus.c | 3 +-
hw/misc/edu.c | 3 +-
hw/misc/ivshmem.c | 3 +-
hw/misc/mips_itu.c | 3 +-
hw/net/e1000e.c | 7 +-
hw/net/e1000x_common.c | 3 +-
hw/net/eepro100.c | 3 +-
hw/net/ne2000.h | 5 +-
hw/nios2/boot.c | 6 +-
hw/nvram/spapr_nvram.c | 11 +-
hw/pci-host/prep.c | 3 +-
hw/pci-host/xilinx-pcie.c | 5 +-
hw/ppc/e500.c | 13 +-
hw/ppc/e500plat.c | 3 +-
hw/ppc/mac.h | 3 +-
hw/ppc/mac_newworld.c | 1 -
hw/ppc/mac_oldworld.c | 9 +-
hw/ppc/pnv.c | 6 +-
hw/ppc/ppc405_boards.c | 9 +-
hw/ppc/ppc405_uc.c | 7 +-
hw/ppc/ppc440_bamboo.c | 5 +-
hw/ppc/ppc440_uc.c | 28 ++--
hw/ppc/ppc4xx_devs.c | 22 ++--
hw/ppc/ppce500_spin.c | 3 +-
hw/ppc/prep.c | 6 +-
hw/ppc/rs6000_mc.c | 13 +-
hw/ppc/sam460ex.c | 18 +--
hw/ppc/spapr.c | 18 +--
hw/ppc/spapr_rtas.c | 4 +-
hw/ppc/virtex_ml507.c | 7 +-
hw/rdma/vmw/pvrdma.h | 3 +-
hw/riscv/virt.c | 3 +-
hw/s390x/s390-skeys.c | 3 +-
hw/s390x/s390-stattrib.c | 3 +-
hw/s390x/sclp.c | 3 +-
hw/scsi/scsi-disk.c | 9 +-
hw/sd/sd.c | 8 +-
hw/sd/sdhci.c | 8 +-
hw/sh4/r2d.c | 3 +-
hw/smbios/smbios.c | 15 +--
hw/sparc/leon3.c | 10 +-
hw/sparc/sun4m.c | 10 +-
hw/sparc64/niagara.c | 3 +-
hw/sparc64/sun4u.c | 4 +-
hw/tricore/tricore_testboard.c | 13 +-
hw/usb/ccid-card-passthru.c | 9 +-
hw/usb/combined-packet.c | 3 +-
hw/usb/dev-smartcard-reader.c | 3 +-
hw/usb/redirect.c | 3 +-
hw/vfio/pci-quirks.c | 9 +-
hw/vfio/pci.c | 3 +-
hw/xenpv/xen_domainbuild.c | 13 +-
hw/xtensa/xtfpga.c | 9 +-
include/exec/exec-all.h | 8 +-
include/hw/acpi/tpm.h | 3 +-
include/hw/display/xlnx_dp.h | 5 +-
include/hw/intc/mips_gic.h | 3 +-
include/hw/mips/bios.h | 3 +-
include/hw/net/allwinner_emac.h | 5 +-
include/hw/ppc/spapr.h | 5 +-
include/hw/virtio/virtio-net.h | 3 +-
include/qemu/cutils.h | 7 -
include/qemu/units.h | 20 +++
linux-user/main.c | 5 +-
monitor.c | 3 +-
scripts/checkpatch.pl | 1 +
target/i386/cpu.c | 7 +-
target/i386/cpu.h | 7 +
target/i386/excp_helper.c | 216 ++++++++++++++++++++++++++++++-
target/i386/hyperv-proto.h | 1 +
target/i386/kvm.c | 15 ++-
target/i386/machine.c | 21 +++
target/i386/mem_helper.c | 6 +-
target/i386/monitor.c | 76 ++++++-----
target/i386/svm.h | 14 ++
target/i386/svm_helper.c | 22 ++++
target/ppc/mmu_helper.c | 8 +-
target/xtensa/helper.c | 5 +-
tests/benchmark-crypto-cipher.c | 6 +-
tests/benchmark-crypto-hash.c | 5 +-
tests/benchmark-crypto-hmac.c | 6 +-
tests/test-cutils.c | 21 +--
tests/test-keyval.c | 7 +-
tests/test-qemu-opts.c | 9 +-
vl.c | 5 +-
129 files changed, 840 insertions(+), 440 deletions(-)
create mode 100644 include/qemu/units.h
--
1.8.3.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Qemu-devel] [PULL 07/50] hw: Use IEC binary prefix definitions from "qemu/units.h"
2018-07-02 15:45 [Qemu-devel] [PULL v2 00/50] More misc patches for 3.0 soft freeze Paolo Bonzini
@ 2018-07-02 15:45 ` Paolo Bonzini
2018-07-02 15:45 ` [Qemu-devel] [PULL 48/50] target-i386: Add NPT support Paolo Bonzini
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Paolo Bonzini @ 2018-07-02 15:45 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Code change produced with:
$ git ls-files | egrep '\.[ch]$' | \
xargs sed -i -e 's/\(\W[KMGTPE]\)_BYTE/\1iB/g'
Suggested-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc parts)
Message-Id: <20180625124238.25339-6-f4bug@amsat.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
hw/arm/msf2-soc.c | 4 ++--
hw/arm/msf2-som.c | 6 +++---
hw/core/loader-fit.c | 3 ++-
hw/core/machine.c | 2 +-
hw/display/sm501.c | 14 +++++++-------
hw/hppa/machine.c | 2 +-
hw/mips/boston.c | 28 ++++++++++++++--------------
hw/ppc/pnv.c | 4 ++--
hw/ppc/ppc440_uc.c | 26 +++++++++++++-------------
hw/ppc/prep.c | 2 +-
hw/ppc/sam460ex.c | 2 +-
hw/ppc/spapr.c | 10 +++++-----
hw/ppc/spapr_rtas.c | 2 +-
hw/sd/sd.c | 4 ++--
hw/sd/sdhci.c | 2 +-
include/qemu/cutils.h | 8 +-------
tests/test-cutils.c | 21 +++++++++++----------
tests/test-keyval.c | 7 ++++---
tests/test-qemu-opts.c | 9 ++++-----
19 files changed, 76 insertions(+), 80 deletions(-)
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
index 75c44ad..530e461 100644
--- a/hw/arm/msf2-soc.c
+++ b/hw/arm/msf2-soc.c
@@ -40,14 +40,14 @@
#define SRAM_BASE_ADDRESS 0x20000000
-#define MSF2_ENVM_MAX_SIZE (512 * K_BYTE)
+#define MSF2_ENVM_MAX_SIZE (512 * KiB)
/*
* eSRAM max size is 80k without SECDED(Single error correction and
* dual error detection) feature and 64k with SECDED.
* We do not support SECDED now.
*/
-#define MSF2_ESRAM_MAX_SIZE (80 * K_BYTE)
+#define MSF2_ESRAM_MAX_SIZE (80 * KiB)
static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
index 0795a3a..ed533bb 100644
--- a/hw/arm/msf2-som.c
+++ b/hw/arm/msf2-som.c
@@ -33,10 +33,10 @@
#include "cpu.h"
#define DDR_BASE_ADDRESS 0xA0000000
-#define DDR_SIZE (64 * M_BYTE)
+#define DDR_SIZE (64 * MiB)
-#define M2S010_ENVM_SIZE (256 * K_BYTE)
-#define M2S010_ESRAM_SIZE (64 * K_BYTE)
+#define M2S010_ENVM_SIZE (256 * KiB)
+#define M2S010_ESRAM_SIZE (64 * KiB)
static void emcraft_sf2_s2s010_init(MachineState *machine)
{
diff --git a/hw/core/loader-fit.c b/hw/core/loader-fit.c
index 6387854..447f608 100644
--- a/hw/core/loader-fit.c
+++ b/hw/core/loader-fit.c
@@ -18,6 +18,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/units.h"
#include "exec/memory.h"
#include "hw/loader.h"
#include "hw/loader-fit.h"
@@ -194,7 +195,7 @@ static int fit_load_fdt(const struct fit_loader *ldr, const void *itb,
err = fit_image_addr(itb, img_off, "load", &load_addr);
if (err == -ENOENT) {
- load_addr = ROUND_UP(kernel_end, 64 * K_BYTE) + (10 * M_BYTE);
+ load_addr = ROUND_UP(kernel_end, 64 * KiB) + (10 * MiB);
} else if (err) {
ret = err;
goto out;
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 617e5f8..ccf3a4b 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -522,7 +522,7 @@ static void machine_class_init(ObjectClass *oc, void *data)
MachineClass *mc = MACHINE_CLASS(oc);
/* Default 128 MB as guest ram size */
- mc->default_ram_size = 128 * M_BYTE;
+ mc->default_ram_size = 128 * MiB;
mc->rom_file_has_mr = true;
/* numa node memory size aligned on 8MB by default.
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 8206ae8..3bd8716 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -452,12 +452,12 @@
/* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */
static const uint32_t sm501_mem_local_size[] = {
- [0] = 4 * M_BYTE,
- [1] = 8 * M_BYTE,
- [2] = 16 * M_BYTE,
- [3] = 32 * M_BYTE,
- [4] = 64 * M_BYTE,
- [5] = 2 * M_BYTE,
+ [0] = 4 * MiB,
+ [1] = 8 * MiB,
+ [2] = 16 * MiB,
+ [3] = 32 * MiB,
+ [4] = 64 * MiB,
+ [5] = 2 * MiB,
};
#define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
@@ -1829,7 +1829,7 @@ static void sm501_realize_pci(PCIDevice *dev, Error **errp)
}
static Property sm501_pci_properties[] = {
- DEFINE_PROP_UINT32("vram-size", SM501PCIState, vram_size, 64 * M_BYTE),
+ DEFINE_PROP_UINT32("vram-size", SM501PCIState, vram_size, 64 * MiB),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index aba269b..2ba2696 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -275,7 +275,7 @@ static void machine_hppa_machine_init(MachineClass *mc)
mc->max_cpus = HPPA_MAX_CPUS;
mc->default_cpus = 1;
mc->is_default = 1;
- mc->default_ram_size = 512 * M_BYTE;
+ mc->default_ram_size = 512 * MiB;
mc->default_boot_order = "cd";
}
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index 14e6f95..939cef5 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -200,7 +200,7 @@ static uint64_t boston_platreg_read(void *opaque, hwaddr addr,
val |= PLAT_BUILD_CFG_PCIE2_EN;
return val;
case PLAT_DDR_CFG:
- val = s->mach->ram_size / G_BYTE;
+ val = s->mach->ram_size / GiB;
assert(!(val & ~PLAT_DDR_CFG_SIZE));
val |= PLAT_DDR_CFG_MHZ;
return val;
@@ -355,7 +355,7 @@ static const void *boston_fdt_filter(void *opaque, const void *fdt_orig,
return NULL;
}
- ram_low_sz = MIN(256 * M_BYTE, machine->ram_size);
+ ram_low_sz = MIN(256 * MiB, machine->ram_size);
ram_high_sz = machine->ram_size - ram_low_sz;
qemu_fdt_setprop_sized_cells(fdt, "/memory@0", "reg",
1, 0x00000000, 1, ram_low_sz,
@@ -436,8 +436,8 @@ static void boston_mach_init(MachineState *machine)
int fw_size, fit_err;
bool is_64b;
- if ((machine->ram_size % G_BYTE) ||
- (machine->ram_size > (2 * G_BYTE))) {
+ if ((machine->ram_size % GiB) ||
+ (machine->ram_size > (2 * GiB))) {
error_report("Memory size must be 1GB or 2GB");
exit(1);
}
@@ -471,7 +471,7 @@ static void boston_mach_init(MachineState *machine)
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1);
flash = g_new(MemoryRegion, 1);
- memory_region_init_rom(flash, NULL, "boston.flash", 128 * M_BYTE, &err);
+ memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB, &err);
memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0);
ddr = g_new(MemoryRegion, 1);
@@ -481,22 +481,22 @@ static void boston_mach_init(MachineState *machine)
ddr_low_alias = g_new(MemoryRegion, 1);
memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr",
- ddr, 0, MIN(machine->ram_size, (256 * M_BYTE)));
+ ddr, 0, MIN(machine->ram_size, (256 * MiB)));
memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0);
xilinx_pcie_init(sys_mem, 0,
- 0x10000000, 32 * M_BYTE,
- 0x40000000, 1 * G_BYTE,
+ 0x10000000, 32 * MiB,
+ 0x40000000, 1 * GiB,
get_cps_irq(s->cps, 2), false);
xilinx_pcie_init(sys_mem, 1,
- 0x12000000, 32 * M_BYTE,
- 0x20000000, 512 * M_BYTE,
+ 0x12000000, 32 * MiB,
+ 0x20000000, 512 * MiB,
get_cps_irq(s->cps, 1), false);
pcie2 = xilinx_pcie_init(sys_mem, 2,
- 0x14000000, 32 * M_BYTE,
- 0x16000000, 1 * M_BYTE,
+ 0x14000000, 32 * MiB,
+ 0x16000000, 1 * MiB,
get_cps_irq(s->cps, 0), true);
platreg = g_new(MemoryRegion, 1);
@@ -526,7 +526,7 @@ static void boston_mach_init(MachineState *machine)
if (machine->firmware) {
fw_size = load_image_targphys(machine->firmware,
- 0x1fc00000, 4 * M_BYTE);
+ 0x1fc00000, 4 * MiB);
if (fw_size == -1) {
error_printf("unable to load firmware image '%s'\n",
machine->firmware);
@@ -552,7 +552,7 @@ static void boston_mach_class_init(MachineClass *mc)
mc->desc = "MIPS Boston";
mc->init = boston_mach_init;
mc->block_default_type = IF_IDE;
- mc->default_ram_size = 1 * G_BYTE;
+ mc->default_ram_size = 1 * GiB;
mc->max_cpus = 16;
mc->default_cpu_type = MIPS_CPU_TYPE_NAME("I6400");
}
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 7401ffe..5fdac62 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -556,7 +556,7 @@ static void pnv_init(MachineState *machine)
char *chip_typename;
/* allocate RAM */
- if (machine->ram_size < (1 * G_BYTE)) {
+ if (machine->ram_size < (1 * GiB)) {
warn_report("skiboot may not work with < 1GB of RAM");
}
@@ -1174,7 +1174,7 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data)
* storage */
mc->no_parallel = 1;
mc->default_boot_order = NULL;
- mc->default_ram_size = 1 * G_BYTE;
+ mc->default_ram_size = 1 * GiB;
xic->icp_get = pnv_icp_get;
xic->ics_get = pnv_ics_get;
xic->ics_resend = pnv_ics_resend;
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 123f4ac..b5b31b4 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -215,13 +215,13 @@ void ppc4xx_l2sram_init(CPUPPCState *env)
l2sram = g_malloc0(sizeof(*l2sram));
/* XXX: Size is 4*64kB for 460ex, cf. U-Boot, ppc4xx-isram.h */
memory_region_init_ram(&l2sram->bank[0], NULL, "ppc4xx.l2sram_bank0",
- 64 * K_BYTE, &error_abort);
+ 64 * KiB, &error_abort);
memory_region_init_ram(&l2sram->bank[1], NULL, "ppc4xx.l2sram_bank1",
- 64 * K_BYTE, &error_abort);
+ 64 * KiB, &error_abort);
memory_region_init_ram(&l2sram->bank[2], NULL, "ppc4xx.l2sram_bank2",
- 64 * K_BYTE, &error_abort);
+ 64 * KiB, &error_abort);
memory_region_init_ram(&l2sram->bank[3], NULL, "ppc4xx.l2sram_bank3",
- 64 * K_BYTE, &error_abort);
+ 64 * KiB, &error_abort);
qemu_register_reset(&l2sram_reset, l2sram);
ppc_dcr_register(env, DCR_L2CACHE_CFG,
l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
@@ -513,28 +513,28 @@ static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
uint32_t bcr;
switch (ram_size) {
- case (8 * M_BYTE):
+ case (8 * MiB):
bcr = 0xffc0;
break;
- case (16 * M_BYTE):
+ case (16 * MiB):
bcr = 0xff80;
break;
- case (32 * M_BYTE):
+ case (32 * MiB):
bcr = 0xff00;
break;
- case (64 * M_BYTE):
+ case (64 * MiB):
bcr = 0xfe00;
break;
- case (128 * M_BYTE):
+ case (128 * MiB):
bcr = 0xfc00;
break;
- case (256 * M_BYTE):
+ case (256 * MiB):
bcr = 0xf800;
break;
- case (512 * M_BYTE):
+ case (512 * MiB):
bcr = 0xf000;
break;
- case (1 * G_BYTE):
+ case (1 * GiB):
bcr = 0xe000;
break;
default:
@@ -561,7 +561,7 @@ static target_ulong sdram_size(uint32_t bcr)
if (sh == 0) {
size = -1;
} else {
- size = 8 * M_BYTE * sh;
+ size = 8 * MiB * sh;
}
return size;
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index 5ed0bcd..25ae533 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -884,7 +884,7 @@ static void ibm_40p_machine_init(MachineClass *mc)
mc->desc = "IBM RS/6000 7020 (40p)",
mc->init = ibm_40p_init;
mc->max_cpus = 1;
- mc->default_ram_size = 128 * M_BYTE;
+ mc->default_ram_size = 128 * MiB;
mc->block_default_type = IF_SCSI;
mc->default_boot_order = "c";
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604");
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index bdc53d2..2a98c10 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -597,7 +597,7 @@ static void sam460ex_machine_init(MachineClass *mc)
mc->desc = "aCube Sam460ex";
mc->init = sam460ex_init;
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb");
- mc->default_ram_size = 512 * M_BYTE;
+ mc->default_ram_size = 512 * MiB;
}
DEFINE_MACHINE("sam460ex", sam460ex_machine_init)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index b32b971..7dbdb4e 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -2324,7 +2324,7 @@ static void spapr_validate_node_memory(MachineState *machine, Error **errp)
error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
" is not aligned to %llu MiB",
machine->ram_size,
- SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
+ SPAPR_MEMORY_BLOCK_SIZE / MiB);
return;
}
@@ -2332,7 +2332,7 @@ static void spapr_validate_node_memory(MachineState *machine, Error **errp)
error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
" is not aligned to %llu MiB",
machine->ram_size,
- SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
+ SPAPR_MEMORY_BLOCK_SIZE / MiB);
return;
}
@@ -2342,7 +2342,7 @@ static void spapr_validate_node_memory(MachineState *machine, Error **errp)
"Node %d memory size 0x%" PRIx64
" is not aligned to %llu MiB",
i, numa_info[i].node_mem,
- SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
+ SPAPR_MEMORY_BLOCK_SIZE / MiB);
return;
}
}
@@ -3209,7 +3209,7 @@ static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
if (size % SPAPR_MEMORY_BLOCK_SIZE) {
error_setg(errp, "Hotplugged memory size must be a multiple of "
- "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
+ "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / MiB);
return;
}
@@ -3961,7 +3961,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
mc->max_cpus = 1024;
mc->no_parallel = 1;
mc->default_boot_order = "";
- mc->default_ram_size = 512 * M_BYTE;
+ mc->default_ram_size = 512 * MiB;
mc->kvm_type = spapr_kvm_type;
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE);
mc->pci_allow_0_address = true;
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index 7f9738d..f32740b 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -241,7 +241,7 @@ static void rtas_ibm_get_system_parameter(PowerPCCPU *cpu,
"DesProcs=%d,"
"MaxPlatProcs=%d",
max_cpus,
- current_machine->ram_size / M_BYTE,
+ current_machine->ram_size / MiB,
smp_cpus,
max_cpus);
ret = sysparm_st(buffer, length, param_val, strlen(param_val) + 1);
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index 540bccb..9a16b76 100644
--- a/hw/sd/sd.c
+++ b/hw/sd/sd.c
@@ -305,7 +305,7 @@ static void sd_ocr_powerup(void *opaque)
/* card power-up OK */
sd->ocr = FIELD_DP32(sd->ocr, OCR, CARD_POWER_UP, 1);
- if (sd->size > 1 * G_BYTE) {
+ if (sd->size > 1 * GiB) {
sd->ocr = FIELD_DP32(sd->ocr, OCR, CARD_CAPACITY, 1);
}
}
@@ -377,7 +377,7 @@ static void sd_set_csd(SDState *sd, uint64_t size)
uint32_t sectsize = (1 << (SECTOR_SHIFT + 1)) - 1;
uint32_t wpsize = (1 << (WPGROUP_SHIFT + 1)) - 1;
- if (size <= 1 * G_BYTE) { /* Standard Capacity SD */
+ if (size <= 1 * GiB) { /* Standard Capacity SD */
sd->csd[0] = 0x00; /* CSD structure */
sd->csd[1] = 0x26; /* Data read access-time-1 */
sd->csd[2] = 0x00; /* Data read access-time-2 */
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 321d02d..c74025b 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -409,7 +409,7 @@ static void sdhci_end_transfer(SDHCIState *s)
/*
* Programmed i/o data transfer
*/
-#define BLOCK_SIZE_MASK (4 * K_BYTE - 1)
+#define BLOCK_SIZE_MASK (4 * KiB - 1)
/* Fill host controller's read buffer with BLKSIZE bytes of data from card */
static void sdhci_read_block_from_card(SDHCIState *s)
diff --git a/include/qemu/cutils.h b/include/qemu/cutils.h
index 274d419..6d5ea83 100644
--- a/include/qemu/cutils.h
+++ b/include/qemu/cutils.h
@@ -2,6 +2,7 @@
#define QEMU_CUTILS_H
#include "qemu/fprintf-fn.h"
+#include "qemu/units.h"
/**
* pstrcpy:
@@ -155,13 +156,6 @@ int qemu_strtosz(const char *nptr, char **end, uint64_t *result);
int qemu_strtosz_MiB(const char *nptr, char **end, uint64_t *result);
int qemu_strtosz_metric(const char *nptr, char **end, uint64_t *result);
-#define K_BYTE (1ULL << 10)
-#define M_BYTE (1ULL << 20)
-#define G_BYTE (1ULL << 30)
-#define T_BYTE (1ULL << 40)
-#define P_BYTE (1ULL << 50)
-#define E_BYTE (1ULL << 60)
-
/* used to print char* safely */
#define STR_OR_NULL(str) ((str) ? (str) : "null")
diff --git a/tests/test-cutils.c b/tests/test-cutils.c
index 64a489c..d85c3e0 100644
--- a/tests/test-cutils.c
+++ b/tests/test-cutils.c
@@ -26,8 +26,9 @@
*/
#include "qemu/osdep.h"
-
+#include "qemu/units.h"
#include "qemu/cutils.h"
+#include "qemu/units.h"
static void test_parse_uint_null(void)
{
@@ -2022,7 +2023,7 @@ static void test_qemu_strtosz_units(void)
/* default is M */
err = qemu_strtosz_MiB(none, &endptr, &res);
g_assert_cmpint(err, ==, 0);
- g_assert_cmpint(res, ==, M_BYTE);
+ g_assert_cmpint(res, ==, MiB);
g_assert(endptr == none + 1);
err = qemu_strtosz(b, &endptr, &res);
@@ -2032,32 +2033,32 @@ static void test_qemu_strtosz_units(void)
err = qemu_strtosz(k, &endptr, &res);
g_assert_cmpint(err, ==, 0);
- g_assert_cmpint(res, ==, K_BYTE);
+ g_assert_cmpint(res, ==, KiB);
g_assert(endptr == k + 2);
err = qemu_strtosz(m, &endptr, &res);
g_assert_cmpint(err, ==, 0);
- g_assert_cmpint(res, ==, M_BYTE);
+ g_assert_cmpint(res, ==, MiB);
g_assert(endptr == m + 2);
err = qemu_strtosz(g, &endptr, &res);
g_assert_cmpint(err, ==, 0);
- g_assert_cmpint(res, ==, G_BYTE);
+ g_assert_cmpint(res, ==, GiB);
g_assert(endptr == g + 2);
err = qemu_strtosz(t, &endptr, &res);
g_assert_cmpint(err, ==, 0);
- g_assert_cmpint(res, ==, T_BYTE);
+ g_assert_cmpint(res, ==, TiB);
g_assert(endptr == t + 2);
err = qemu_strtosz(p, &endptr, &res);
g_assert_cmpint(err, ==, 0);
- g_assert_cmpint(res, ==, P_BYTE);
+ g_assert_cmpint(res, ==, PiB);
g_assert(endptr == p + 2);
err = qemu_strtosz(e, &endptr, &res);
g_assert_cmpint(err, ==, 0);
- g_assert_cmpint(res, ==, E_BYTE);
+ g_assert_cmpint(res, ==, EiB);
g_assert(endptr == e + 2);
}
@@ -2070,7 +2071,7 @@ static void test_qemu_strtosz_float(void)
err = qemu_strtosz(str, &endptr, &res);
g_assert_cmpint(err, ==, 0);
- g_assert_cmpint(res, ==, 12.345 * M_BYTE);
+ g_assert_cmpint(res, ==, 12.345 * MiB);
g_assert(endptr == str + 7);
}
@@ -2106,7 +2107,7 @@ static void test_qemu_strtosz_trailing(void)
str = "123xxx";
err = qemu_strtosz_MiB(str, &endptr, &res);
- g_assert_cmpint(res, ==, 123 * M_BYTE);
+ g_assert_cmpint(res, ==, 123 * MiB);
g_assert(endptr == str + 3);
err = qemu_strtosz(str, NULL, &res);
diff --git a/tests/test-keyval.c b/tests/test-keyval.c
index 63cb146..09b0ae3 100644
--- a/tests/test-keyval.c
+++ b/tests/test-keyval.c
@@ -11,6 +11,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/units.h"
#include "qapi/error.h"
#include "qapi/qmp/qdict.h"
#include "qapi/qmp/qlist.h"
@@ -457,11 +458,11 @@ static void test_keyval_visit_size(void)
visit_type_size(v, "sz2", &sz, &error_abort);
g_assert_cmpuint(sz, ==, 1536);
visit_type_size(v, "sz3", &sz, &error_abort);
- g_assert_cmphex(sz, ==, 2 * M_BYTE);
+ g_assert_cmphex(sz, ==, 2 * MiB);
visit_type_size(v, "sz4", &sz, &error_abort);
- g_assert_cmphex(sz, ==, G_BYTE / 10);
+ g_assert_cmphex(sz, ==, GiB / 10);
visit_type_size(v, "sz5", &sz, &error_abort);
- g_assert_cmphex(sz, ==, 16777215 * T_BYTE);
+ g_assert_cmphex(sz, ==, 16777215ULL * TiB);
visit_check_struct(v, &error_abort);
visit_end_struct(v, NULL);
visit_free(v);
diff --git a/tests/test-qemu-opts.c b/tests/test-qemu-opts.c
index 7092e21..ef96e84 100644
--- a/tests/test-qemu-opts.c
+++ b/tests/test-qemu-opts.c
@@ -8,7 +8,7 @@
*/
#include "qemu/osdep.h"
-#include "qemu/cutils.h"
+#include "qemu/units.h"
#include "qemu/option.h"
#include "qemu/option_int.h"
#include "qapi/error.h"
@@ -704,13 +704,12 @@ static void test_opts_parse_size(void)
g_assert_cmpuint(opts_count(opts), ==, 3);
g_assert_cmphex(qemu_opt_get_size(opts, "size1", 0), ==, 8);
g_assert_cmphex(qemu_opt_get_size(opts, "size2", 0), ==, 1536);
- g_assert_cmphex(qemu_opt_get_size(opts, "size3", 0), ==, 2 * M_BYTE);
+ g_assert_cmphex(qemu_opt_get_size(opts, "size3", 0), ==, 2 * MiB);
opts = qemu_opts_parse(&opts_list_02, "size1=0.1G,size2=16777215T",
false, &error_abort);
g_assert_cmpuint(opts_count(opts), ==, 2);
- g_assert_cmphex(qemu_opt_get_size(opts, "size1", 0), ==, G_BYTE / 10);
- g_assert_cmphex(qemu_opt_get_size(opts, "size2", 0),
- ==, 16777215 * T_BYTE);
+ g_assert_cmphex(qemu_opt_get_size(opts, "size1", 0), ==, GiB / 10);
+ g_assert_cmphex(qemu_opt_get_size(opts, "size2", 0), ==, 16777215ULL * TiB);
/* Beyond limit with suffix */
opts = qemu_opts_parse(&opts_list_02, "size1=16777216T",
--
1.8.3.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Qemu-devel] [PULL 48/50] target-i386: Add NPT support
2018-07-02 15:45 [Qemu-devel] [PULL v2 00/50] More misc patches for 3.0 soft freeze Paolo Bonzini
2018-07-02 15:45 ` [Qemu-devel] [PULL 07/50] hw: Use IEC binary prefix definitions from "qemu/units.h" Paolo Bonzini
@ 2018-07-02 15:45 ` Paolo Bonzini
2018-07-02 15:45 ` [Qemu-devel] [PULL 49/50] i386/monitor.c: make addresses canonical for "info mem" and "info tlb" Paolo Bonzini
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Paolo Bonzini @ 2018-07-02 15:45 UTC (permalink / raw)
To: qemu-devel; +Cc: Jan Kiszka
From: Jan Kiszka <jan.kiszka@siemens.com>
This implements NPT suport for SVM by hooking into
x86_cpu_handle_mmu_fault where it reads the stage-1 page table. Whether
we need to perform this 2nd stage translation, and how, is decided
during vmrun and stored in hflags2, along with nested_cr3 and
nested_pg_mode.
As get_hphys performs a direct cpu_vmexit in case of NPT faults, we need
retaddr in that function. To avoid changing the signature of
cpu_handle_mmu_fault, this passes the value from tlb_fill to get_hphys
via the CPU state.
This was tested successfully via the Jailhouse hypervisor.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Message-Id: <567473a0-6005-5843-4c73-951f476085ca@web.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 6 ++
target/i386/excp_helper.c | 216 +++++++++++++++++++++++++++++++++++++++++++++-
target/i386/machine.c | 21 +++++
target/i386/mem_helper.c | 6 +-
target/i386/svm.h | 14 +++
target/i386/svm_helper.c | 22 +++++
7 files changed, 281 insertions(+), 6 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index bdbd446..b0b87c3 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -749,7 +749,7 @@ static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
#define TCG_EXT4_FEATURES 0
-#define TCG_SVM_FEATURES 0
+#define TCG_SVM_FEATURES CPUID_SVM_NPT
#define TCG_KVM_FEATURES 0
#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 8b1ddfe..2c5a0d9 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -211,6 +211,7 @@ typedef enum X86Seg {
#define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */
#define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */
#define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */
+#define HF2_NPT_SHIFT 6 /* Nested Paging enabled */
#define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
#define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
@@ -218,6 +219,7 @@ typedef enum X86Seg {
#define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
#define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
#define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
+#define HF2_NPT_MASK (1 << HF2_NPT_SHIFT)
#define CR0_PE_SHIFT 0
#define CR0_MP_SHIFT 1
@@ -1265,12 +1267,16 @@ typedef struct CPUX86State {
uint16_t intercept_dr_read;
uint16_t intercept_dr_write;
uint32_t intercept_exceptions;
+ uint64_t nested_cr3;
+ uint32_t nested_pg_mode;
uint8_t v_tpr;
/* KVM states, automatically cleared on reset */
uint8_t nmi_injected;
uint8_t nmi_pending;
+ uintptr_t retaddr;
+
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
diff --git a/target/i386/excp_helper.c b/target/i386/excp_helper.c
index cb4d1b7..37a33d5 100644
--- a/target/i386/excp_helper.c
+++ b/target/i386/excp_helper.c
@@ -157,6 +157,209 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size,
#else
+static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type,
+ int *prot)
+{
+ CPUX86State *env = &X86_CPU(cs)->env;
+ uint64_t rsvd_mask = PG_HI_RSVD_MASK;
+ uint64_t ptep, pte;
+ uint64_t exit_info_1 = 0;
+ target_ulong pde_addr, pte_addr;
+ uint32_t page_offset;
+ int page_size;
+
+ if (likely(!(env->hflags2 & HF2_NPT_MASK))) {
+ return gphys;
+ }
+
+ if (!(env->nested_pg_mode & SVM_NPT_NXE)) {
+ rsvd_mask |= PG_NX_MASK;
+ }
+
+ if (env->nested_pg_mode & SVM_NPT_PAE) {
+ uint64_t pde, pdpe;
+ target_ulong pdpe_addr;
+
+#ifdef TARGET_X86_64
+ if (env->nested_pg_mode & SVM_NPT_LMA) {
+ uint64_t pml5e;
+ uint64_t pml4e_addr, pml4e;
+
+ pml5e = env->nested_cr3;
+ ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
+
+ pml4e_addr = (pml5e & PG_ADDRESS_MASK) +
+ (((gphys >> 39) & 0x1ff) << 3);
+ pml4e = x86_ldq_phys(cs, pml4e_addr);
+ if (!(pml4e & PG_PRESENT_MASK)) {
+ goto do_fault;
+ }
+ if (pml4e & (rsvd_mask | PG_PSE_MASK)) {
+ goto do_fault_rsvd;
+ }
+ if (!(pml4e & PG_ACCESSED_MASK)) {
+ pml4e |= PG_ACCESSED_MASK;
+ x86_stl_phys_notdirty(cs, pml4e_addr, pml4e);
+ }
+ ptep &= pml4e ^ PG_NX_MASK;
+ pdpe_addr = (pml4e & PG_ADDRESS_MASK) +
+ (((gphys >> 30) & 0x1ff) << 3);
+ pdpe = x86_ldq_phys(cs, pdpe_addr);
+ if (!(pdpe & PG_PRESENT_MASK)) {
+ goto do_fault;
+ }
+ if (pdpe & rsvd_mask) {
+ goto do_fault_rsvd;
+ }
+ ptep &= pdpe ^ PG_NX_MASK;
+ if (!(pdpe & PG_ACCESSED_MASK)) {
+ pdpe |= PG_ACCESSED_MASK;
+ x86_stl_phys_notdirty(cs, pdpe_addr, pdpe);
+ }
+ if (pdpe & PG_PSE_MASK) {
+ /* 1 GB page */
+ page_size = 1024 * 1024 * 1024;
+ pte_addr = pdpe_addr;
+ pte = pdpe;
+ goto do_check_protect;
+ }
+ } else
+#endif
+ {
+ pdpe_addr = (env->nested_cr3 & ~0x1f) + ((gphys >> 27) & 0x18);
+ pdpe = x86_ldq_phys(cs, pdpe_addr);
+ if (!(pdpe & PG_PRESENT_MASK)) {
+ goto do_fault;
+ }
+ rsvd_mask |= PG_HI_USER_MASK;
+ if (pdpe & (rsvd_mask | PG_NX_MASK)) {
+ goto do_fault_rsvd;
+ }
+ ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
+ }
+
+ pde_addr = (pdpe & PG_ADDRESS_MASK) + (((gphys >> 21) & 0x1ff) << 3);
+ pde = x86_ldq_phys(cs, pde_addr);
+ if (!(pde & PG_PRESENT_MASK)) {
+ goto do_fault;
+ }
+ if (pde & rsvd_mask) {
+ goto do_fault_rsvd;
+ }
+ ptep &= pde ^ PG_NX_MASK;
+ if (pde & PG_PSE_MASK) {
+ /* 2 MB page */
+ page_size = 2048 * 1024;
+ pte_addr = pde_addr;
+ pte = pde;
+ goto do_check_protect;
+ }
+ /* 4 KB page */
+ if (!(pde & PG_ACCESSED_MASK)) {
+ pde |= PG_ACCESSED_MASK;
+ x86_stl_phys_notdirty(cs, pde_addr, pde);
+ }
+ pte_addr = (pde & PG_ADDRESS_MASK) + (((gphys >> 12) & 0x1ff) << 3);
+ pte = x86_ldq_phys(cs, pte_addr);
+ if (!(pte & PG_PRESENT_MASK)) {
+ goto do_fault;
+ }
+ if (pte & rsvd_mask) {
+ goto do_fault_rsvd;
+ }
+ /* combine pde and pte nx, user and rw protections */
+ ptep &= pte ^ PG_NX_MASK;
+ page_size = 4096;
+ } else {
+ uint32_t pde;
+
+ /* page directory entry */
+ pde_addr = (env->nested_cr3 & ~0xfff) + ((gphys >> 20) & 0xffc);
+ pde = x86_ldl_phys(cs, pde_addr);
+ if (!(pde & PG_PRESENT_MASK)) {
+ goto do_fault;
+ }
+ ptep = pde | PG_NX_MASK;
+
+ /* if PSE bit is set, then we use a 4MB page */
+ if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
+ page_size = 4096 * 1024;
+ pte_addr = pde_addr;
+
+ /* Bits 20-13 provide bits 39-32 of the address, bit 21 is reserved.
+ * Leave bits 20-13 in place for setting accessed/dirty bits below.
+ */
+ pte = pde | ((pde & 0x1fe000LL) << (32 - 13));
+ rsvd_mask = 0x200000;
+ goto do_check_protect_pse36;
+ }
+
+ if (!(pde & PG_ACCESSED_MASK)) {
+ pde |= PG_ACCESSED_MASK;
+ x86_stl_phys_notdirty(cs, pde_addr, pde);
+ }
+
+ /* page directory entry */
+ pte_addr = (pde & ~0xfff) + ((gphys >> 10) & 0xffc);
+ pte = x86_ldl_phys(cs, pte_addr);
+ if (!(pte & PG_PRESENT_MASK)) {
+ goto do_fault;
+ }
+ /* combine pde and pte user and rw protections */
+ ptep &= pte | PG_NX_MASK;
+ page_size = 4096;
+ rsvd_mask = 0;
+ }
+
+ do_check_protect:
+ rsvd_mask |= (page_size - 1) & PG_ADDRESS_MASK & ~PG_PSE_PAT_MASK;
+ do_check_protect_pse36:
+ if (pte & rsvd_mask) {
+ goto do_fault_rsvd;
+ }
+ ptep ^= PG_NX_MASK;
+
+ if (!(ptep & PG_USER_MASK)) {
+ goto do_fault_protect;
+ }
+ if (ptep & PG_NX_MASK) {
+ if (access_type == MMU_INST_FETCH) {
+ goto do_fault_protect;
+ }
+ *prot &= ~PAGE_EXEC;
+ }
+ if (!(ptep & PG_RW_MASK)) {
+ if (access_type == MMU_DATA_STORE) {
+ goto do_fault_protect;
+ }
+ *prot &= ~PAGE_WRITE;
+ }
+
+ pte &= PG_ADDRESS_MASK & ~(page_size - 1);
+ page_offset = gphys & (page_size - 1);
+ return pte + page_offset;
+
+ do_fault_rsvd:
+ exit_info_1 |= SVM_NPTEXIT_RSVD;
+ do_fault_protect:
+ exit_info_1 |= SVM_NPTEXIT_P;
+ do_fault:
+ x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
+ gphys);
+ exit_info_1 |= SVM_NPTEXIT_US;
+ if (access_type == MMU_DATA_STORE) {
+ exit_info_1 |= SVM_NPTEXIT_RW;
+ } else if (access_type == MMU_INST_FETCH) {
+ exit_info_1 |= SVM_NPTEXIT_ID;
+ }
+ if (prot) {
+ exit_info_1 |= SVM_NPTEXIT_GPA;
+ } else { /* page table access */
+ exit_info_1 |= SVM_NPTEXIT_GPT;
+ }
+ cpu_vmexit(env, SVM_EXIT_NPF, exit_info_1, env->retaddr);
+}
+
/* return value:
* -1 = cannot handle fault
* 0 = nothing more to do
@@ -224,6 +427,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size,
if (la57) {
pml5e_addr = ((env->cr[3] & ~0xfff) +
(((addr >> 48) & 0x1ff) << 3)) & a20_mask;
+ pml5e_addr = get_hphys(cs, pml5e_addr, MMU_DATA_STORE, NULL);
pml5e = x86_ldq_phys(cs, pml5e_addr);
if (!(pml5e & PG_PRESENT_MASK)) {
goto do_fault;
@@ -243,6 +447,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size,
pml4e_addr = ((pml5e & PG_ADDRESS_MASK) +
(((addr >> 39) & 0x1ff) << 3)) & a20_mask;
+ pml4e_addr = get_hphys(cs, pml4e_addr, MMU_DATA_STORE, false);
pml4e = x86_ldq_phys(cs, pml4e_addr);
if (!(pml4e & PG_PRESENT_MASK)) {
goto do_fault;
@@ -257,6 +462,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size,
ptep &= pml4e ^ PG_NX_MASK;
pdpe_addr = ((pml4e & PG_ADDRESS_MASK) + (((addr >> 30) & 0x1ff) << 3)) &
a20_mask;
+ pdpe_addr = get_hphys(cs, pdpe_addr, MMU_DATA_STORE, NULL);
pdpe = x86_ldq_phys(cs, pdpe_addr);
if (!(pdpe & PG_PRESENT_MASK)) {
goto do_fault;
@@ -282,6 +488,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size,
/* XXX: load them when cr3 is loaded ? */
pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
a20_mask;
+ pdpe_addr = get_hphys(cs, pdpe_addr, MMU_DATA_STORE, false);
pdpe = x86_ldq_phys(cs, pdpe_addr);
if (!(pdpe & PG_PRESENT_MASK)) {
goto do_fault;
@@ -295,6 +502,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size,
pde_addr = ((pdpe & PG_ADDRESS_MASK) + (((addr >> 21) & 0x1ff) << 3)) &
a20_mask;
+ pde_addr = get_hphys(cs, pde_addr, MMU_DATA_STORE, NULL);
pde = x86_ldq_phys(cs, pde_addr);
if (!(pde & PG_PRESENT_MASK)) {
goto do_fault;
@@ -317,6 +525,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size,
}
pte_addr = ((pde & PG_ADDRESS_MASK) + (((addr >> 12) & 0x1ff) << 3)) &
a20_mask;
+ pte_addr = get_hphys(cs, pte_addr, MMU_DATA_STORE, NULL);
pte = x86_ldq_phys(cs, pte_addr);
if (!(pte & PG_PRESENT_MASK)) {
goto do_fault;
@@ -333,6 +542,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size,
/* page directory entry */
pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) &
a20_mask;
+ pde_addr = get_hphys(cs, pde_addr, MMU_DATA_STORE, NULL);
pde = x86_ldl_phys(cs, pde_addr);
if (!(pde & PG_PRESENT_MASK)) {
goto do_fault;
@@ -360,6 +570,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size,
/* page directory entry */
pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) &
a20_mask;
+ pte_addr = get_hphys(cs, pte_addr, MMU_DATA_STORE, NULL);
pte = x86_ldl_phys(cs, pte_addr);
if (!(pte & PG_PRESENT_MASK)) {
goto do_fault;
@@ -442,12 +653,13 @@ do_check_protect_pse36:
/* align to page_size */
pte &= PG_ADDRESS_MASK & ~(page_size - 1);
+ page_offset = addr & (page_size - 1);
+ paddr = get_hphys(cs, pte + page_offset, is_write1, &prot);
/* Even if 4MB pages, we map only one 4KB page in the cache to
avoid filling it too fast */
vaddr = addr & TARGET_PAGE_MASK;
- page_offset = vaddr & (page_size - 1);
- paddr = pte + page_offset;
+ paddr &= TARGET_PAGE_MASK;
assert(prot & (1 << is_write1));
tlb_set_page_with_attrs(cs, vaddr, paddr, cpu_get_mem_attrs(env),
diff --git a/target/i386/machine.c b/target/i386/machine.c
index 4d98d36..8b64dff 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -935,6 +935,26 @@ static const VMStateDescription vmstate_msr_virt_ssbd = {
}
};
+static bool svm_npt_needed(void *opaque)
+{
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
+
+ return !!(env->hflags2 & HF2_NPT_MASK);
+}
+
+static const VMStateDescription vmstate_svm_npt = {
+ .name = "cpu/svn_npt",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = svm_npt_needed,
+ .fields = (VMStateField[]){
+ VMSTATE_UINT64(env.nested_cr3, X86CPU),
+ VMSTATE_UINT32(env.nested_pg_mode, X86CPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
VMStateDescription vmstate_x86_cpu = {
.name = "cpu",
.version_id = 12,
@@ -1059,6 +1079,7 @@ VMStateDescription vmstate_x86_cpu = {
&vmstate_mcg_ext_ctl,
&vmstate_msr_intel_pt,
&vmstate_msr_virt_ssbd,
+ &vmstate_svm_npt,
NULL
}
};
diff --git a/target/i386/mem_helper.c b/target/i386/mem_helper.c
index a8ae694..30c26b9 100644
--- a/target/i386/mem_helper.c
+++ b/target/i386/mem_helper.c
@@ -202,13 +202,13 @@ void helper_boundl(CPUX86State *env, target_ulong a0, int v)
void tlb_fill(CPUState *cs, target_ulong addr, int size,
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
int ret;
+ env->retaddr = retaddr;
ret = x86_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx);
if (ret) {
- X86CPU *cpu = X86_CPU(cs);
- CPUX86State *env = &cpu->env;
-
raise_exception_err_ra(env, cs->exception_index, env->error_code, retaddr);
}
}
diff --git a/target/i386/svm.h b/target/i386/svm.h
index 922c8fd..23a3a04 100644
--- a/target/i386/svm.h
+++ b/target/i386/svm.h
@@ -130,6 +130,20 @@
#define SVM_CR0_SELECTIVE_MASK (1 << 3 | 1) /* TS and MP */
+#define SVM_NPT_ENABLED (1 << 0)
+
+#define SVM_NPT_PAE (1 << 0)
+#define SVM_NPT_LMA (1 << 1)
+#define SVM_NPT_NXE (1 << 2)
+
+#define SVM_NPTEXIT_P (1ULL << 0)
+#define SVM_NPTEXIT_RW (1ULL << 1)
+#define SVM_NPTEXIT_US (1ULL << 2)
+#define SVM_NPTEXIT_RSVD (1ULL << 3)
+#define SVM_NPTEXIT_ID (1ULL << 4)
+#define SVM_NPTEXIT_GPA (1ULL << 32)
+#define SVM_NPTEXIT_GPT (1ULL << 33)
+
struct QEMU_PACKED vmcb_control_area {
uint16_t intercept_cr_read;
uint16_t intercept_cr_write;
diff --git a/target/i386/svm_helper.c b/target/i386/svm_helper.c
index f245aec..342ece0 100644
--- a/target/i386/svm_helper.c
+++ b/target/i386/svm_helper.c
@@ -124,6 +124,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
{
CPUState *cs = CPU(x86_env_get_cpu(env));
target_ulong addr;
+ uint64_t nested_ctl;
uint32_t event_inj;
uint32_t int_ctl;
@@ -206,6 +207,26 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
control.intercept_exceptions
));
+ nested_ctl = x86_ldq_phys(cs, env->vm_vmcb + offsetof(struct vmcb,
+ control.nested_ctl));
+ if (nested_ctl & SVM_NPT_ENABLED) {
+ env->nested_cr3 = x86_ldq_phys(cs,
+ env->vm_vmcb + offsetof(struct vmcb,
+ control.nested_cr3));
+ env->hflags2 |= HF2_NPT_MASK;
+
+ env->nested_pg_mode = 0;
+ if (env->cr[4] & CR4_PAE_MASK) {
+ env->nested_pg_mode |= SVM_NPT_PAE;
+ }
+ if (env->hflags & HF_LMA_MASK) {
+ env->nested_pg_mode |= SVM_NPT_LMA;
+ }
+ if (env->efer & MSR_EFER_NXE) {
+ env->nested_pg_mode |= SVM_NPT_NXE;
+ }
+ }
+
/* enable intercepts */
env->hflags |= HF_SVMI_MASK;
@@ -616,6 +637,7 @@ void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
x86_stl_phys(cs,
env->vm_vmcb + offsetof(struct vmcb, control.int_state), 0);
}
+ env->hflags2 &= ~HF2_NPT_MASK;
/* Save the VM state in the vmcb */
svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.es),
--
1.8.3.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Qemu-devel] [PULL 49/50] i386/monitor.c: make addresses canonical for "info mem" and "info tlb"
2018-07-02 15:45 [Qemu-devel] [PULL v2 00/50] More misc patches for 3.0 soft freeze Paolo Bonzini
2018-07-02 15:45 ` [Qemu-devel] [PULL 07/50] hw: Use IEC binary prefix definitions from "qemu/units.h" Paolo Bonzini
2018-07-02 15:45 ` [Qemu-devel] [PULL 48/50] target-i386: Add NPT support Paolo Bonzini
@ 2018-07-02 15:45 ` Paolo Bonzini
2018-07-02 15:45 ` [Qemu-devel] [PULL 50/50] tcg: simplify !CONFIG_TCG handling of tb_invalidate_* Paolo Bonzini
2018-07-03 8:48 ` [Qemu-devel] [PULL v2 00/50] More misc patches for 3.0 soft freeze Peter Maydell
4 siblings, 0 replies; 7+ messages in thread
From: Paolo Bonzini @ 2018-07-02 15:45 UTC (permalink / raw)
To: qemu-devel; +Cc: Doug Gale
From: Doug Gale <doug16k@gmail.com>
Correct the output of the "info mem" and "info tlb" monitor commands to
correctly show canonical addresses.
In 48-bit addressing mode, the upper 16 bits of linear addresses are
equal to bit 47. In 57-bit addressing mode (LA57), the upper 7 bits of
linear addresses are equal to bit 56.
Signed-off-by: Doug Gale <doug16k@gmail.com>
Message-Id: <20180617084025.29198-1-doug16k@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/monitor.c | 76 +++++++++++++++++++++++++++++----------------------
1 file changed, 44 insertions(+), 32 deletions(-)
diff --git a/target/i386/monitor.c b/target/i386/monitor.c
index 6bbb3a9..74a13c5 100644
--- a/target/i386/monitor.c
+++ b/target/i386/monitor.c
@@ -35,21 +35,28 @@
#include "sev_i386.h"
#include "qapi/qapi-commands-misc.h"
-
-static void print_pte(Monitor *mon, CPUArchState *env, hwaddr addr,
- hwaddr pte, hwaddr mask)
+/* Perform linear address sign extension */
+static hwaddr addr_canonical(CPUArchState *env, hwaddr addr)
{
#ifdef TARGET_X86_64
if (env->cr[4] & CR4_LA57_MASK) {
if (addr & (1ULL << 56)) {
- addr |= -1LL << 57;
+ addr |= (hwaddr)-(1LL << 57);
}
} else {
if (addr & (1ULL << 47)) {
- addr |= -1LL << 48;
+ addr |= (hwaddr)-(1LL << 48);
}
}
#endif
+ return addr;
+}
+
+static void print_pte(Monitor *mon, CPUArchState *env, hwaddr addr,
+ hwaddr pte, hwaddr mask)
+{
+ addr = addr_canonical(env, addr);
+
monitor_printf(mon, TARGET_FMT_plx ": " TARGET_FMT_plx
" %c%c%c%c%c%c%c%c%c\n",
addr,
@@ -243,8 +250,8 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)
}
}
-static void mem_print(Monitor *mon, hwaddr *pstart,
- int *plast_prot,
+static void mem_print(Monitor *mon, CPUArchState *env,
+ hwaddr *pstart, int *plast_prot,
hwaddr end, int prot)
{
int prot1;
@@ -253,7 +260,9 @@ static void mem_print(Monitor *mon, hwaddr *pstart,
if (*pstart != -1) {
monitor_printf(mon, TARGET_FMT_plx "-" TARGET_FMT_plx " "
TARGET_FMT_plx " %c%c%c\n",
- *pstart, end, end - *pstart,
+ addr_canonical(env, *pstart),
+ addr_canonical(env, end),
+ addr_canonical(env, end - *pstart),
prot1 & PG_USER_MASK ? 'u' : '-',
'r',
prot1 & PG_RW_MASK ? 'w' : '-');
@@ -283,7 +292,7 @@ static void mem_info_32(Monitor *mon, CPUArchState *env)
if (pde & PG_PRESENT_MASK) {
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
prot = pde & (PG_USER_MASK | PG_RW_MASK | PG_PRESENT_MASK);
- mem_print(mon, &start, &last_prot, end, prot);
+ mem_print(mon, env, &start, &last_prot, end, prot);
} else {
for(l2 = 0; l2 < 1024; l2++) {
cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4);
@@ -295,16 +304,16 @@ static void mem_info_32(Monitor *mon, CPUArchState *env)
} else {
prot = 0;
}
- mem_print(mon, &start, &last_prot, end, prot);
+ mem_print(mon, env, &start, &last_prot, end, prot);
}
}
} else {
prot = 0;
- mem_print(mon, &start, &last_prot, end, prot);
+ mem_print(mon, env, &start, &last_prot, end, prot);
}
}
/* Flush last range */
- mem_print(mon, &start, &last_prot, (hwaddr)1 << 32, 0);
+ mem_print(mon, env, &start, &last_prot, (hwaddr)1 << 32, 0);
}
static void mem_info_pae32(Monitor *mon, CPUArchState *env)
@@ -332,7 +341,7 @@ static void mem_info_pae32(Monitor *mon, CPUArchState *env)
if (pde & PG_PSE_MASK) {
prot = pde & (PG_USER_MASK | PG_RW_MASK |
PG_PRESENT_MASK);
- mem_print(mon, &start, &last_prot, end, prot);
+ mem_print(mon, env, &start, &last_prot, end, prot);
} else {
pt_addr = pde & 0x3fffffffff000ULL;
for (l3 = 0; l3 < 512; l3++) {
@@ -345,21 +354,21 @@ static void mem_info_pae32(Monitor *mon, CPUArchState *env)
} else {
prot = 0;
}
- mem_print(mon, &start, &last_prot, end, prot);
+ mem_print(mon, env, &start, &last_prot, end, prot);
}
}
} else {
prot = 0;
- mem_print(mon, &start, &last_prot, end, prot);
+ mem_print(mon, env, &start, &last_prot, end, prot);
}
}
} else {
prot = 0;
- mem_print(mon, &start, &last_prot, end, prot);
+ mem_print(mon, env, &start, &last_prot, end, prot);
}
}
/* Flush last range */
- mem_print(mon, &start, &last_prot, (hwaddr)1 << 32, 0);
+ mem_print(mon, env, &start, &last_prot, (hwaddr)1 << 32, 0);
}
@@ -389,7 +398,7 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env)
prot = pdpe & (PG_USER_MASK | PG_RW_MASK |
PG_PRESENT_MASK);
prot &= pml4e;
- mem_print(mon, &start, &last_prot, end, prot);
+ mem_print(mon, env, &start, &last_prot, end, prot);
} else {
pd_addr = pdpe & 0x3fffffffff000ULL;
for (l3 = 0; l3 < 512; l3++) {
@@ -401,7 +410,8 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env)
prot = pde & (PG_USER_MASK | PG_RW_MASK |
PG_PRESENT_MASK);
prot &= pml4e & pdpe;
- mem_print(mon, &start, &last_prot, end, prot);
+ mem_print(mon, env, &start,
+ &last_prot, end, prot);
} else {
pt_addr = pde & 0x3fffffffff000ULL;
for (l4 = 0; l4 < 512; l4++) {
@@ -418,27 +428,29 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env)
} else {
prot = 0;
}
- mem_print(mon, &start, &last_prot, end, prot);
+ mem_print(mon, env, &start,
+ &last_prot, end, prot);
}
}
} else {
prot = 0;
- mem_print(mon, &start, &last_prot, end, prot);
+ mem_print(mon, env, &start,
+ &last_prot, end, prot);
}
}
}
} else {
prot = 0;
- mem_print(mon, &start, &last_prot, end, prot);
+ mem_print(mon, env, &start, &last_prot, end, prot);
}
}
} else {
prot = 0;
- mem_print(mon, &start, &last_prot, end, prot);
+ mem_print(mon, env, &start, &last_prot, end, prot);
}
}
/* Flush last range */
- mem_print(mon, &start, &last_prot, (hwaddr)1 << 48, 0);
+ mem_print(mon, env, &start, &last_prot, (hwaddr)1 << 48, 0);
}
static void mem_info_la57(Monitor *mon, CPUArchState *env)
@@ -457,7 +469,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env)
end = l0 << 48;
if (!(pml5e & PG_PRESENT_MASK)) {
prot = 0;
- mem_print(mon, &start, &last_prot, end, prot);
+ mem_print(mon, env, &start, &last_prot, end, prot);
continue;
}
@@ -468,7 +480,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env)
end = (l0 << 48) + (l1 << 39);
if (!(pml4e & PG_PRESENT_MASK)) {
prot = 0;
- mem_print(mon, &start, &last_prot, end, prot);
+ mem_print(mon, env, &start, &last_prot, end, prot);
continue;
}
@@ -479,7 +491,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env)
end = (l0 << 48) + (l1 << 39) + (l2 << 30);
if (pdpe & PG_PRESENT_MASK) {
prot = 0;
- mem_print(mon, &start, &last_prot, end, prot);
+ mem_print(mon, env, &start, &last_prot, end, prot);
continue;
}
@@ -487,7 +499,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env)
prot = pdpe & (PG_USER_MASK | PG_RW_MASK |
PG_PRESENT_MASK);
prot &= pml5e & pml4e;
- mem_print(mon, &start, &last_prot, end, prot);
+ mem_print(mon, env, &start, &last_prot, end, prot);
continue;
}
@@ -498,7 +510,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env)
end = (l0 << 48) + (l1 << 39) + (l2 << 30) + (l3 << 21);
if (pde & PG_PRESENT_MASK) {
prot = 0;
- mem_print(mon, &start, &last_prot, end, prot);
+ mem_print(mon, env, &start, &last_prot, end, prot);
continue;
}
@@ -506,7 +518,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env)
prot = pde & (PG_USER_MASK | PG_RW_MASK |
PG_PRESENT_MASK);
prot &= pml5e & pml4e & pdpe;
- mem_print(mon, &start, &last_prot, end, prot);
+ mem_print(mon, env, &start, &last_prot, end, prot);
continue;
}
@@ -523,14 +535,14 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env)
} else {
prot = 0;
}
- mem_print(mon, &start, &last_prot, end, prot);
+ mem_print(mon, env, &start, &last_prot, end, prot);
}
}
}
}
}
/* Flush last range */
- mem_print(mon, &start, &last_prot, (hwaddr)1 << 57, 0);
+ mem_print(mon, env, &start, &last_prot, (hwaddr)1 << 57, 0);
}
#endif /* TARGET_X86_64 */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Qemu-devel] [PULL 50/50] tcg: simplify !CONFIG_TCG handling of tb_invalidate_*
2018-07-02 15:45 [Qemu-devel] [PULL v2 00/50] More misc patches for 3.0 soft freeze Paolo Bonzini
` (2 preceding siblings ...)
2018-07-02 15:45 ` [Qemu-devel] [PULL 49/50] i386/monitor.c: make addresses canonical for "info mem" and "info tlb" Paolo Bonzini
@ 2018-07-02 15:45 ` Paolo Bonzini
2018-07-02 16:14 ` Philippe Mathieu-Daudé
2018-07-03 8:48 ` [Qemu-devel] [PULL v2 00/50] More misc patches for 3.0 soft freeze Peter Maydell
4 siblings, 1 reply; 7+ messages in thread
From: Paolo Bonzini @ 2018-07-02 15:45 UTC (permalink / raw)
To: qemu-devel
There is no need for a stub, since tb_invalidate_phys_addr can be excised
altogether when TCG is disabled. This is a bit cleaner since it avoids
using code that is clearly specific to user-mode emulation (it calls
mmap_lock/unlock) for the !CONFIG_TCG case.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
accel/stubs/tcg-stub.c | 6 ------
exec.c | 6 +++++-
include/exec/exec-all.h | 8 +++-----
3 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c
index 8ee85ed..76ae461 100644
--- a/accel/stubs/tcg-stub.c
+++ b/accel/stubs/tcg-stub.c
@@ -16,7 +16,6 @@
#include "tcg/tcg.h"
#include "exec/cpu-common.h"
#include "exec/exec-all.h"
-#include "translate-all.h"
void tb_flush(CPUState *cpu)
{
@@ -25,8 +24,3 @@ void tb_flush(CPUState *cpu)
void tlb_set_dirty(CPUState *cpu, target_ulong vaddr)
{
}
-
-void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
- int is_cpu_write_access)
-{
-}
diff --git a/exec.c b/exec.c
index ee72688..4f5df07 100644
--- a/exec.c
+++ b/exec.c
@@ -1027,7 +1027,7 @@ const char *parse_cpu_model(const char *cpu_model)
return cpu_type;
}
-#if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG)
+#if defined(CONFIG_USER_ONLY)
void tb_invalidate_phys_addr(target_ulong addr)
{
mmap_lock();
@@ -1046,6 +1046,10 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
MemoryRegion *mr;
hwaddr l = 1;
+ if (!tcg_enabled()) {
+ return;
+ }
+
rcu_read_lock();
mr = address_space_translate(as, addr, &addr, &l, false, attrs);
if (!(memory_region_is_ram(mr)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index cb497de..da73e3b 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -412,13 +412,11 @@ static inline uint32_t curr_cflags(void)
}
/* TranslationBlock invalidate API */
-#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
-void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
-#else
-void tb_invalidate_phys_addr(target_ulong addr);
-#endif
#if defined(CONFIG_USER_ONLY)
+void tb_invalidate_phys_addr(target_ulong addr);
void tb_invalidate_phys_range(target_ulong start, target_ulong end);
+#else
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
#endif
void tb_flush(CPUState *cpu);
void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PULL 50/50] tcg: simplify !CONFIG_TCG handling of tb_invalidate_*
2018-07-02 15:45 ` [Qemu-devel] [PULL 50/50] tcg: simplify !CONFIG_TCG handling of tb_invalidate_* Paolo Bonzini
@ 2018-07-02 16:14 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 7+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-07-02 16:14 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 07/02/2018 12:45 PM, Paolo Bonzini wrote:
> There is no need for a stub, since tb_invalidate_phys_addr can be excised
> altogether when TCG is disabled. This is a bit cleaner since it avoids
> using code that is clearly specific to user-mode emulation (it calls
> mmap_lock/unlock) for the !CONFIG_TCG case.
Cleaner :)
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> accel/stubs/tcg-stub.c | 6 ------
> exec.c | 6 +++++-
> include/exec/exec-all.h | 8 +++-----
> 3 files changed, 8 insertions(+), 12 deletions(-)
>
> diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c
> index 8ee85ed..76ae461 100644
> --- a/accel/stubs/tcg-stub.c
> +++ b/accel/stubs/tcg-stub.c
> @@ -16,7 +16,6 @@
> #include "tcg/tcg.h"
> #include "exec/cpu-common.h"
> #include "exec/exec-all.h"
> -#include "translate-all.h"
>
> void tb_flush(CPUState *cpu)
> {
> @@ -25,8 +24,3 @@ void tb_flush(CPUState *cpu)
> void tlb_set_dirty(CPUState *cpu, target_ulong vaddr)
> {
> }
> -
> -void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
> - int is_cpu_write_access)
> -{
> -}
> diff --git a/exec.c b/exec.c
> index ee72688..4f5df07 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -1027,7 +1027,7 @@ const char *parse_cpu_model(const char *cpu_model)
> return cpu_type;
> }
>
> -#if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG)
> +#if defined(CONFIG_USER_ONLY)
> void tb_invalidate_phys_addr(target_ulong addr)
> {
> mmap_lock();
> @@ -1046,6 +1046,10 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
> MemoryRegion *mr;
> hwaddr l = 1;
>
> + if (!tcg_enabled()) {
> + return;
> + }
> +
> rcu_read_lock();
> mr = address_space_translate(as, addr, &addr, &l, false, attrs);
> if (!(memory_region_is_ram(mr)
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index cb497de..da73e3b 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -412,13 +412,11 @@ static inline uint32_t curr_cflags(void)
> }
>
> /* TranslationBlock invalidate API */
> -#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
> -void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
> -#else
> -void tb_invalidate_phys_addr(target_ulong addr);
> -#endif
> #if defined(CONFIG_USER_ONLY)
> +void tb_invalidate_phys_addr(target_ulong addr);
> void tb_invalidate_phys_range(target_ulong start, target_ulong end);
> +#else
> +void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
> #endif
> void tb_flush(CPUState *cpu);
> void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PULL v2 00/50] More misc patches for 3.0 soft freeze
2018-07-02 15:45 [Qemu-devel] [PULL v2 00/50] More misc patches for 3.0 soft freeze Paolo Bonzini
` (3 preceding siblings ...)
2018-07-02 15:45 ` [Qemu-devel] [PULL 50/50] tcg: simplify !CONFIG_TCG handling of tb_invalidate_* Paolo Bonzini
@ 2018-07-03 8:48 ` Peter Maydell
4 siblings, 0 replies; 7+ messages in thread
From: Peter Maydell @ 2018-07-03 8:48 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: QEMU Developers
On 2 July 2018 at 16:45, Paolo Bonzini <pbonzini@redhat.com> wrote:
> The following changes since commit 646f34fa5482e495483de230b4cf0f2ae4fd2781:
>
> tcg: Fix --disable-tcg build breakage (2018-07-02 13:42:05 +0100)
>
> are available in the git repository at:
>
> git://github.com/bonzini/qemu.git tags/for-upstream
>
> for you to fetch changes up to c40d479207b1bb6569ffde06e9a58e85cd529de0:
>
> tcg: simplify !CONFIG_TCG handling of tb_invalidate_* (2018-07-02 15:41:18 +0200)
>
> ----------------------------------------------------------------
> * IEC units series (Philippe)
> * Hyper-V PV TLB flush (Vitaly)
> * git archive detection (Daniel)
> * host serial passthrough fix (David)
> * NPT support for SVM emulation (Jan)
> * x86 "info mem" and "info tlb" fix (Doug)
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2018-07-03 8:49 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-07-02 15:45 [Qemu-devel] [PULL v2 00/50] More misc patches for 3.0 soft freeze Paolo Bonzini
2018-07-02 15:45 ` [Qemu-devel] [PULL 07/50] hw: Use IEC binary prefix definitions from "qemu/units.h" Paolo Bonzini
2018-07-02 15:45 ` [Qemu-devel] [PULL 48/50] target-i386: Add NPT support Paolo Bonzini
2018-07-02 15:45 ` [Qemu-devel] [PULL 49/50] i386/monitor.c: make addresses canonical for "info mem" and "info tlb" Paolo Bonzini
2018-07-02 15:45 ` [Qemu-devel] [PULL 50/50] tcg: simplify !CONFIG_TCG handling of tb_invalidate_* Paolo Bonzini
2018-07-02 16:14 ` Philippe Mathieu-Daudé
2018-07-03 8:48 ` [Qemu-devel] [PULL v2 00/50] More misc patches for 3.0 soft freeze Peter Maydell
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