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From: Robert Hoo <robert.hu@linux.intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: Eduardo Habkost <ehabkost@redhat.com>,
	qemu-devel@nongnu.org, wei.w.wang@intel.com
Subject: Re: [Qemu-devel] [PATCH v2 1/5] i386: Add support for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs
Date: Tue, 03 Jul 2018 19:07:51 +0800	[thread overview]
Message-ID: <1530616071.22880.52.camel@linux.intel.com> (raw)
In-Reply-To: <b7c410af-ebc0-537c-84c4-588842fec111@redhat.com>

On Tue, 2018-07-03 at 11:06 +0200, Paolo Bonzini wrote:
> On 03/07/2018 10:48, Robert Hoo wrote:
> >>
> >> However, I suggest adding it to the FeatureWord enum, since everything
> >> that handles FeatureWord applies to this new kind of MSR as well.
> >> Currently FeatureWord is only for CPUID leaves, but it doesn't have to
> >> be like that.
> >>
> > I think this will be changing struct FeatureWordInfo, which is designed
> > for cpuid enumerations. You must not want to do that. May I know more
> > details about your thought?
> 
> The simplest way is to put CPUIDs first and MSRs second in FeatureWord.
> Then you can do
> 
>      FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
>      FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
> +    FEATURE_WORDS_NUM_CPUID,
> +    FEATURE_WORDS_FIRST_MSR = FEATURE_WORDS_NUM_CPUID,
> +    FEAT_MSR_ARCH_CAPABILITIES = FEATURE_WORDS_FIRST_MSR,
>      FEATURE_WORDS,
> };
> 
> #define FEATURE_WORDS_NUM_MSRS (FEATURE_WORDS - \
>                                 FEATURE_WORDS_FIRST_MSR)
> 
> Then the existing loops that use FeatureWordInfo can go up to
> FEATURE_WORDS_NUM_CPUID.

Emm... Understand your point now. It is a little risky, all references
to FEATURE_WORDS need to be updated carefully.
OK, let me try to think in this way.
Perhaps, I'll need to define a new 'struct FeautureWordMsrInfo' to
describe feature words from MSR, in parallel to current FeatureWordInfo
(or better rename it to FeatureWordCpuidInfo).
> 
> Thanks,
> 
> Paolo
> 
> > And, if I implemented ARCH_CAPABILITIES-bits features in FeatureWord,
> > then no necessity of having it in kvm_msr_entries, right?
> 
And would you help confirm with my this point?

  parent reply	other threads:[~2018-07-03 11:07 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-27 11:27 [Qemu-devel] [PATCH v2 0/5] Add Icelake CPU model Robert Hoo
2018-06-27 11:27 ` [Qemu-devel] [PATCH v2 1/5] i386: Add support for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs Robert Hoo
2018-06-27 17:03   ` Eduardo Habkost
2018-06-28  9:25     ` Robert Hoo
2018-06-28 13:56       ` Eduardo Habkost
2018-06-28 14:20       ` Paolo Bonzini
2018-07-03  8:48         ` Robert Hoo
2018-07-03  9:06           ` Paolo Bonzini
2018-07-03 11:06             ` Eduardo Habkost
2018-07-03 11:07             ` Robert Hoo [this message]
2018-07-03 13:38               ` Paolo Bonzini
2018-07-04  6:33                 ` Robert Hoo
2018-07-04  9:40                   ` Paolo Bonzini
2018-07-13 14:11   ` konrad.wilk
2018-07-13 14:44     ` Paolo Bonzini
2018-07-13 14:52       ` Konrad Rzeszutek Wilk
2018-07-14  0:02     ` Robert Hoo
2018-06-27 11:27 ` [Qemu-devel] [PATCH v2 2/5] i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR Robert Hoo
2018-06-28 18:28   ` Eduardo Habkost
2018-07-03  7:35     ` Robert Hoo
2018-07-03 11:00       ` Eduardo Habkost
2018-07-12  9:18         ` Robert Hoo
2018-07-12 15:47           ` Paolo Bonzini
2018-06-27 11:27 ` [Qemu-devel] [PATCH v2 3/5] i386: Add CPUID bit for PCONFIG Robert Hoo
2018-06-27 11:27 ` [Qemu-devel] [PATCH v2 4/5] i386: Add CPUID bit for WBNOINVD Robert Hoo
2018-06-27 11:27 ` [Qemu-devel] [PATCH v2 5/5] i386: Add new CPU model Icelake-{Server, Client} Robert Hoo
2018-07-02  2:31 ` [Qemu-devel] [PATCH v2 0/5] Add Icelake CPU model no-reply

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