From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50037) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fadkd-0001hK-PK for qemu-devel@nongnu.org; Wed, 04 Jul 2018 05:07:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fadka-0007P7-Im for qemu-devel@nongnu.org; Wed, 04 Jul 2018 05:07:03 -0400 Received: from mga04.intel.com ([192.55.52.120]:53506) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fadka-0007OO-7j for qemu-devel@nongnu.org; Wed, 04 Jul 2018 05:07:00 -0400 From: Robert Hoo Date: Wed, 4 Jul 2018 17:06:38 +0800 Message-Id: <1530695199-27601-5-git-send-email-robert.hu@linux.intel.com> In-Reply-To: <1530695199-27601-1-git-send-email-robert.hu@linux.intel.com> References: <1530695199-27601-1-git-send-email-robert.hu@linux.intel.com> Subject: [Qemu-devel] [PATCH v3 4/5] i386: Add CPUID bit for WBNOINVD List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com Cc: robert.hu@intel.com, Robert Hoo WBNOINVD: Write back and do not invalidate cache, enumerated by CPUID.(EAX=80000008H, ECX=0):EBX[bit 9]. Signed-off-by: Robert Hoo --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 9407071..9ad3f93 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1027,7 +1027,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .feat_names = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + NULL, "wbnoinvd", NULL, NULL, "ibpb", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 12a7e6c..265f428 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -694,6 +694,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/ #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ +#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and + do not invalidate cache */ #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */ #define CPUID_XSAVE_XSAVEOPT (1U << 0) -- 1.8.3.1