From: Robert Hoo <robert.hu@linux.intel.com>
To: qemu-devel@nongnu.org, pbonzini@redhat.com, rth@twiddle.net,
ehabkost@redhat.com
Cc: robert.hu@intel.com, wei.w.wang@intel.com, jingqi.liu@intel.com,
Robert Hoo <robert.hu@linux.intel.com>
Subject: [Qemu-devel] [PATCH v4 1/5] i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES
Date: Thu, 5 Jul 2018 17:09:54 +0800 [thread overview]
Message-ID: <1530781798-183214-2-git-send-email-robert.hu@linux.intel.com> (raw)
In-Reply-To: <1530781798-183214-1-git-send-email-robert.hu@linux.intel.com>
IA32_PRED_CMD MSR gives software a way to issue commands that affect the state
of indirect branch predictors. Enumerated by CPUID.(EAX=7H,ECX=0):EDX[26].
IA32_ARCH_CAPABILITIES MSR enumerates architectural features of RDCL_NO and
IBRS_ALL. Enumerated by CPUID.(EAX=07H, ECX=0):EDX[29].
https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
---
target/i386/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 2c5a0d9..ae97005 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -354,6 +354,8 @@ typedef enum X86Seg {
#define MSR_TSC_ADJUST 0x0000003b
#define MSR_IA32_SPEC_CTRL 0x48
#define MSR_VIRT_SSBD 0xc001011f
+#define MSR_IA32_PRED_CMD 0x49
+#define MSR_IA32_ARCH_CAPABILITIES 0x10a
#define MSR_IA32_TSCDEADLINE 0x6e0
#define FEATURE_CONTROL_LOCKED (1<<0)
--
1.8.3.1
next prev parent reply other threads:[~2018-07-05 9:10 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-05 9:09 [Qemu-devel] [PATCH v4 0/5] Add Icelake CPU model Robert Hoo
2018-07-05 9:09 ` Robert Hoo [this message]
2018-07-05 9:09 ` [Qemu-devel] [PATCH v4 2/5] i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR Robert Hoo
2018-07-05 9:09 ` [Qemu-devel] [PATCH v4 3/5] i386: Add CPUID bit for PCONFIG Robert Hoo
2018-07-05 9:09 ` [Qemu-devel] [PATCH v4 4/5] i386: Add CPUID bit for WBNOINVD Robert Hoo
2018-07-05 9:09 ` [Qemu-devel] [PATCH v4 5/5] i386: Add new CPU model Icelake-{Server, Client} Robert Hoo
2018-07-05 9:54 ` [Qemu-devel] [PATCH v4 0/5] Add Icelake CPU model no-reply
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