* [Qemu-devel] [PATCH v4 0/8] Maintenance and misc fixes and improvements
@ 2018-07-06 11:48 Aleksandar Markovic
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 1/8] target/mips: Update maintainer's email addresses Aleksandar Markovic
` (7 more replies)
0 siblings, 8 replies; 15+ messages in thread
From: Aleksandar Markovic @ 2018-07-06 11:48 UTC (permalink / raw)
To: qemu-devel
Cc: philippe.mathieu.daude, aurelien, richard.henderson, amarkovic,
smarkovic, pjovanovic, pburton
From: Aleksandar Markovic <amarkovic@wavecomp.com>
v3->v4:
- accepted suggestion on better format of bit definitions in patch 3
- fixed build errors caused by a mistake in patch 4
- removed spurious comments in patch 4
- added setting lower 16 bits to 0 in patch 5
- used proper email address for a reviewer in patch 7 commit message
v2->v3:
- replaced invalid @imgtec.com and @mips.com in "From:",,
"Signed-off-by:", "Reviewed-by:" lines with the most current
email addresses for a particular person
- fixed build errors that appeared because of a mistake during
integration
v1->v2:
- fixed recipient's email addresses
Maintenance issues, fixes, and improvements collected during recent
development. Some of them are related to the upcoming nanoMIPS changes.
Note: These patches are, of course, supposed to be applied AFTER soft
freeze.
Aleksandar Markovic (4):
target/mips: Update maintainer's email addresses
target/mips: Workaround for checkpatch.pl hanging on msa_helper.c
target/mips: Update some CP0 registers bit definitions
target/mips: Avoid case statements formulated by ranges
Stefan Markovic (1):
target/mips: Add CP0 BadInstrX register
Yongbok Kim (3):
target/mips: Amend CP0 WatchHi register implementation
target/mips: Don't update BadVAddr register in Debug Mode
target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0
.mailmap | 7 +-
MAINTAINERS | 9 +-
target/mips/cpu.h | 41 +++---
target/mips/helper.c | 4 +-
target/mips/helper.h | 3 +
target/mips/machine.c | 7 +-
target/mips/msa_helper.c | 4 +-
target/mips/op_helper.c | 35 +++++-
target/mips/translate.c | 315 ++++++++++++++++++++++++++++++++++++++---------
9 files changed, 339 insertions(+), 86 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v4 1/8] target/mips: Update maintainer's email addresses
2018-07-06 11:48 [Qemu-devel] [PATCH v4 0/8] Maintenance and misc fixes and improvements Aleksandar Markovic
@ 2018-07-06 11:48 ` Aleksandar Markovic
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 2/8] target/mips: Workaround for checkpatch.pl hanging on msa_helper.c Aleksandar Markovic
` (6 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Aleksandar Markovic @ 2018-07-06 11:48 UTC (permalink / raw)
To: qemu-devel
Cc: philippe.mathieu.daude, aurelien, richard.henderson, amarkovic,
smarkovic, pjovanovic, pburton
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Update email addresses of Aleksandar Markovic and Paul Burton in the
MAINTAINERS file. Also, add corresponding items in the .mailmap file.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
.mailmap | 7 +++++--
MAINTAINERS | 9 +++++----
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/.mailmap b/.mailmap
index 778a4d4..2c2b9b1 100644
--- a/.mailmap
+++ b/.mailmap
@@ -12,8 +12,11 @@ Fabrice Bellard <fabrice@bellard.org> bellard <bellard@c046a42c-6fe2-441c-8c8c-7
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
Jocelyn Mayer <l_indien@magic.fr> j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162>
Paul Brook <paul@codesourcery.com> pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>
-Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
-Paul Burton <paul.burton@mips.com> <paul@archlinuxmips.org>
+Aleksandar Markovic <amarkovic@wavecomp.com> <aleksandar.markovic@mips.com>
+Aleksandar Markovic <amarkovic@wavecomp.com> <aleksandar.markovic@imgtec.com>
+Paul Burton <pburton@wavecomp.com> <paul.burton@mips.com>
+Paul Burton <pburton@wavecomp.com> <paul.burton@imgtec.com>
+Paul Burton <pburton@wavecomp.com> <paul@archlinuxmips.org>
Thiemo Seufer <ths@networkno.de> ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>
malc <av1474@comtv.ru> malc <malc@c046a42c-6fe2-441c-8c8c-71466251a162>
diff --git a/MAINTAINERS b/MAINTAINERS
index 6630d69..f3863b1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -187,7 +187,7 @@ F: disas/microblaze.c
MIPS
M: Aurelien Jarno <aurelien@aurel32.net>
-M: Aleksandar Markovic <aleksandar.markovic@mips.com>
+M: Aleksandar Markovic <amarkovic@wavecomp.com>
S: Maintained
F: target/mips/
F: hw/mips/
@@ -718,7 +718,7 @@ S: Maintained
F: hw/mips/mips_malta.c
Mipssim
-M: Aleksandar Markovic <aleksandar.markovic@mips.com>
+M: Aleksandar Markovic <amarkovic@wavecomp.com>
S: Odd Fixes
F: hw/mips/mips_mipssim.c
F: hw/net/mipsnet.c
@@ -729,14 +729,15 @@ S: Maintained
F: hw/mips/mips_r4k.c
Fulong 2E
-M: Aleksandar Markovic <aleksandar.markovic@mips.com>
+M: Aleksandar Markovic <amarkovic@wavecomp.com>
S: Odd Fixes
F: hw/mips/mips_fulong2e.c
F: hw/isa/vt82c686.c
+
F: include/hw/isa/vt82c686.h
Boston
-M: Paul Burton <paul.burton@mips.com>
+M: Paul Burton <pburton@wavecomp.com>
S: Maintained
F: hw/core/loader-fit.c
F: hw/mips/boston.c
--
2.7.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v4 2/8] target/mips: Workaround for checkpatch.pl hanging on msa_helper.c
2018-07-06 11:48 [Qemu-devel] [PATCH v4 0/8] Maintenance and misc fixes and improvements Aleksandar Markovic
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 1/8] target/mips: Update maintainer's email addresses Aleksandar Markovic
@ 2018-07-06 11:48 ` Aleksandar Markovic
2018-07-06 15:38 ` Aleksandar Markovic
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 3/8] target/mips: Update some CP0 registers bit definitions Aleksandar Markovic
` (5 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Aleksandar Markovic @ 2018-07-06 11:48 UTC (permalink / raw)
To: qemu-devel
Cc: philippe.mathieu.daude, aurelien, richard.henderson, amarkovic,
smarkovic, pjovanovic, pburton
From: Aleksandar Markovic <amarkovic@wavecomp.com>
If checkpatch.pl is applied (using switch "-f") on file
target/mips/msa_helper.c, it will hang.
This is a workaround by correcting the source file. The workaround is
found by partial deleting and undeleting of the code in msa_helper.c
in binary search fashion.
The bug (for checkpatch.pl) is already reported to the qemu-devel list.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/msa_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index c74e3cd..1691b70 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -2750,8 +2750,8 @@ void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
#define FMAXMIN_A(F, G, X, _S, _T, BITS, STATUS) \
do { \
- uint## BITS ##_t S = _S, T = _T; \
- uint## BITS ##_t as, at, xs, xt, xd; \
+ uint## BITS ## _t S = _S, T = _T; \
+ uint## BITS ## _t as, at, xs, xt, xd; \
if (NUMBER_QNAN_PAIR(S, T, BITS, STATUS)) { \
T = S; \
} \
--
2.7.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v4 3/8] target/mips: Update some CP0 registers bit definitions
2018-07-06 11:48 [Qemu-devel] [PATCH v4 0/8] Maintenance and misc fixes and improvements Aleksandar Markovic
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 1/8] target/mips: Update maintainer's email addresses Aleksandar Markovic
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 2/8] target/mips: Workaround for checkpatch.pl hanging on msa_helper.c Aleksandar Markovic
@ 2018-07-06 11:48 ` Aleksandar Markovic
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 4/8] target/mips: Avoid case statements formulated by ranges Aleksandar Markovic
` (4 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Aleksandar Markovic @ 2018-07-06 11:48 UTC (permalink / raw)
To: qemu-devel
Cc: philippe.mathieu.daude, aurelien, richard.henderson, amarkovic,
smarkovic, pjovanovic, pburton
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Update CP0 registers Config0, Config1, and Config5 bit definitions.
Some of these bits will be utilized by upcoming nanoMIPS changes.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/cpu.h | 38 +++++++++++++++++++++++++-------------
1 file changed, 25 insertions(+), 13 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index cfe1735..100b5f4 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -388,26 +388,27 @@ struct CPUMIPSState {
target_ulong CP0_CMGCRBase;
int32_t CP0_Config0;
#define CP0C0_M 31
-#define CP0C0_K23 28
-#define CP0C0_KU 25
+#define CP0C0_K23 28 /* 30..28 */
+#define CP0C0_KU 25 /* 27..25 */
#define CP0C0_MDU 20
#define CP0C0_MM 18
#define CP0C0_BM 16
+#define CP0C0_Impl 16 /* 24..16 */
#define CP0C0_BE 15
-#define CP0C0_AT 13
-#define CP0C0_AR 10
-#define CP0C0_MT 7
+#define CP0C0_AT 13 /* 14..13 */
+#define CP0C0_AR 10 /* 12..10 */
+#define CP0C0_MT 7 /* 9..7 */
#define CP0C0_VI 3
-#define CP0C0_K0 0
+#define CP0C0_K0 0 /* 2..0 */
int32_t CP0_Config1;
#define CP0C1_M 31
-#define CP0C1_MMU 25
-#define CP0C1_IS 22
-#define CP0C1_IL 19
-#define CP0C1_IA 16
-#define CP0C1_DS 13
-#define CP0C1_DL 10
-#define CP0C1_DA 7
+#define CP0C1_MMU 25 /* 30..25 */
+#define CP0C1_IS 22 /* 24..22 */
+#define CP0C1_IL 19 /* 21..19 */
+#define CP0C1_IA 16 /* 18..16 */
+#define CP0C1_DS 13 /* 15..13 */
+#define CP0C1_DL 10 /* 12..10 */
+#define CP0C1_DA 7 /* 9..7 */
#define CP0C1_C2 6
#define CP0C1_MD 5
#define CP0C1_PC 4
@@ -468,7 +469,18 @@ struct CPUMIPSState {
#define CP0C5_CV 29
#define CP0C5_EVA 28
#define CP0C5_MSAEn 27
+#define CP0C5_PMJ 23 /* 25..23 */
+#define CP0C5_WR2 22
+#define CP0C5_NMS 21
+#define CP0C5_ULS 20
+#define CP0C5_XPA 19
+#define CP0C5_CRCP 18
+#define CP0C5_MI 17
+#define CP0C5_GI 15 /* 16..15 */
+#define CP0C5_CA2 14
#define CP0C5_XNP 13
+#define CP0C5_DEC 11
+#define CP0C5_L2C 10
#define CP0C5_UFE 9
#define CP0C5_FRE 8
#define CP0C5_VP 7
--
2.7.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v4 4/8] target/mips: Avoid case statements formulated by ranges
2018-07-06 11:48 [Qemu-devel] [PATCH v4 0/8] Maintenance and misc fixes and improvements Aleksandar Markovic
` (2 preceding siblings ...)
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 3/8] target/mips: Update some CP0 registers bit definitions Aleksandar Markovic
@ 2018-07-06 11:48 ` Aleksandar Markovic
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 5/8] target/mips: Add CP0 BadInstrX register Aleksandar Markovic
` (3 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Aleksandar Markovic @ 2018-07-06 11:48 UTC (permalink / raw)
To: qemu-devel
Cc: philippe.mathieu.daude, aurelien, richard.henderson, amarkovic,
smarkovic, pjovanovic, pburton
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Remove "range style" case statements to make code analysis easier.
This is needed also for some upcoming nanoMIPS-related refactorings.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 249 ++++++++++++++++++++++++++++++++++++++----------
1 file changed, 200 insertions(+), 49 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 20b43c0..051dda5 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5494,7 +5494,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 18:
switch (sel) {
- case 0 ... 7:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
gen_helper_1e0i(mfc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -5504,7 +5511,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 19:
switch (sel) {
- case 0 ...7:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
gen_helper_1e0i(mfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -5630,7 +5644,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 27:
switch (sel) {
- case 0 ... 3:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
rn = "CacheErr";
break;
@@ -5701,7 +5718,12 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE";
break;
- case 2 ... 7:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -6167,7 +6189,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 18:
switch (sel) {
- case 0 ... 7:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
gen_helper_0e1i(mtc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -6177,7 +6206,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 19:
switch (sel) {
- case 0 ... 7:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
gen_helper_0e1i(mtc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -6315,7 +6351,10 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 27:
switch (sel) {
- case 0 ... 3:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
/* ignored */
rn = "CacheErr";
break;
@@ -6381,7 +6420,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE";
break;
- case 2 ... 7:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -6842,7 +6886,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 18:
switch (sel) {
- case 0 ... 7:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
gen_helper_1e0i(dmfc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -6852,7 +6903,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 19:
switch (sel) {
- case 0 ... 7:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
gen_helper_1e0i(mfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -6975,7 +7033,10 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 27:
switch (sel) {
/* ignored */
- case 0 ... 3:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
rn = "CacheErr";
break;
@@ -7040,7 +7101,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE";
break;
- case 2 ... 7:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -7497,7 +7563,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 18:
switch (sel) {
- case 0 ... 7:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
gen_helper_0e1i(mtc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -7507,7 +7580,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 19:
switch (sel) {
- case 0 ... 7:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
gen_helper_0e1i(mtc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -7641,7 +7721,10 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 27:
switch (sel) {
- case 0 ... 3:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
/* ignored */
rn = "CacheErr";
break;
@@ -7707,7 +7790,12 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE";
break;
- case 2 ... 7:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -7843,7 +7931,14 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
break;
case 16:
switch (sel) {
- case 0 ... 7:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
gen_helper_mftc0_configx(t0, cpu_env, tcg_const_tl(sel));
break;
default:
@@ -17231,7 +17326,10 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
case OPC_LSA:
gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2));
break;
- case OPC_MULT ... OPC_DIVU:
+ case OPC_MULT:
+ case OPC_MULTU:
+ case OPC_DIV:
+ case OPC_DIVU:
op2 = MASK_R6_MULDIV(ctx->opcode);
switch (op2) {
case R6_OPC_MUL:
@@ -17291,7 +17389,11 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
generate_exception_end(ctx, EXCP_RI);
}
break;
- case OPC_DMULT ... OPC_DDIVU:
+ case OPC_DMULT:
+ case OPC_DMULTU:
+ case OPC_DDIV:
+ case OPC_DDIVU:
+
op2 = MASK_R6_MULDIV(ctx->opcode);
switch (op2) {
case R6_OPC_DMUL:
@@ -17370,7 +17472,10 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
gen_muldiv(ctx, op1, 0, rs, rt);
break;
#if defined(TARGET_MIPS64)
- case OPC_DMULT ... OPC_DDIVU:
+ case OPC_DMULT:
+ case OPC_DMULTU:
+ case OPC_DDIV:
+ case OPC_DDIVU:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_muldiv(ctx, op1, 0, rs, rt);
@@ -17437,7 +17542,10 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
- case OPC_ADD ... OPC_SUBU:
+ case OPC_ADD:
+ case OPC_ADDU:
+ case OPC_SUB:
+ case OPC_SUBU:
gen_arith(ctx, op1, rd, rs, rt);
break;
case OPC_SLLV: /* Shifts */
@@ -17473,7 +17581,11 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
case OPC_JALR:
gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4);
break;
- case OPC_TGE ... OPC_TEQ: /* Traps */
+ case OPC_TGE: /* Traps */
+ case OPC_TGEU:
+ case OPC_TLT:
+ case OPC_TLTU:
+ case OPC_TEQ:
case OPC_TNE:
check_insn(ctx, ISA_MIPS2);
gen_trap(ctx, op1, rs, rt, -1);
@@ -17549,7 +17661,10 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
- case OPC_DADD ... OPC_DSUBU:
+ case OPC_DADD:
+ case OPC_DADDU:
+ case OPC_DSUB:
+ case OPC_DSUBU:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_arith(ctx, op1, rd, rs, rt);
@@ -17607,8 +17722,10 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL2(ctx->opcode);
switch (op1) {
- case OPC_MADD ... OPC_MADDU: /* Multiply and add/sub */
- case OPC_MSUB ... OPC_MSUBU:
+ case OPC_MADD: /* Multiply and add/sub */
+ case OPC_MADDU:
+ case OPC_MSUB:
+ case OPC_MSUBU:
check_insn(ctx, ISA_MIPS32);
gen_muldiv(ctx, op1, rd & 3, rs, rt);
break;
@@ -17705,7 +17822,8 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
}
op2 = MASK_BSHFL(ctx->opcode);
switch (op2) {
- case OPC_ALIGN ... OPC_ALIGN_END:
+ case OPC_ALIGN:
+ case OPC_ALIGN_END:
gen_align(ctx, OPC_ALIGN, rd, rs, rt, sa & 3);
break;
case OPC_BITSWAP:
@@ -17730,7 +17848,8 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
}
op2 = MASK_DBSHFL(ctx->opcode);
switch (op2) {
- case OPC_DALIGN ... OPC_DALIGN_END:
+ case OPC_DALIGN:
+ case OPC_DALIGN_END:
gen_align(ctx, OPC_DALIGN, rd, rs, rt, sa & 7);
break;
case OPC_DBITSWAP:
@@ -17759,9 +17878,12 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL3(ctx->opcode);
switch (op1) {
- case OPC_DIV_G_2E ... OPC_DIVU_G_2E:
- case OPC_MOD_G_2E ... OPC_MODU_G_2E:
- case OPC_MULT_G_2E ... OPC_MULTU_G_2E:
+ case OPC_DIV_G_2E:
+ case OPC_DIVU_G_2E:
+ case OPC_MOD_G_2E:
+ case OPC_MODU_G_2E:
+ case OPC_MULT_G_2E:
+ case OPC_MULTU_G_2E:
/* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
* the same mask and op1. */
if ((ctx->insn_flags & ASE_DSPR2) && (op1 == OPC_MULT_G_2E)) {
@@ -18025,9 +18147,12 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
break;
#if defined(TARGET_MIPS64)
- case OPC_DDIV_G_2E ... OPC_DDIVU_G_2E:
- case OPC_DMULT_G_2E ... OPC_DMULTU_G_2E:
- case OPC_DMOD_G_2E ... OPC_DMODU_G_2E:
+ case OPC_DDIV_G_2E:
+ case OPC_DDIVU_G_2E:
+ case OPC_DMULT_G_2E:
+ case OPC_DMULTU_G_2E:
+ case OPC_DMOD_G_2E:
+ case OPC_DMODU_G_2E:
check_insn(ctx, INSN_LOONGSON2E);
gen_loongson_integer(ctx, op1, rd, rs, rt);
break;
@@ -18289,18 +18414,25 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
*/
if (ctx->eva) {
switch (op1) {
- case OPC_LWLE ... OPC_LWRE:
+ case OPC_LWLE:
+ case OPC_LWRE:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* fall through */
- case OPC_LBUE ... OPC_LHUE:
- case OPC_LBE ... OPC_LWE:
+ case OPC_LBUE:
+ case OPC_LHUE:
+ case OPC_LBE:
+ case OPC_LHE:
+ case OPC_LLE:
+ case OPC_LWE:
check_cp0_enabled(ctx);
gen_ld(ctx, op1, rt, rs, imm);
return;
- case OPC_SWLE ... OPC_SWRE:
+ case OPC_SWLE:
+ case OPC_SWRE:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* fall through */
- case OPC_SBE ... OPC_SHE:
+ case OPC_SBE:
+ case OPC_SHE:
case OPC_SWE:
check_cp0_enabled(ctx);
gen_st(ctx, op1, rt, rs, imm);
@@ -18332,7 +18464,8 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
case OPC_BSHFL:
op2 = MASK_BSHFL(ctx->opcode);
switch (op2) {
- case OPC_ALIGN ... OPC_ALIGN_END:
+ case OPC_ALIGN:
+ case OPC_ALIGN_END:
case OPC_BITSWAP:
check_insn(ctx, ISA_MIPS32R6);
decode_opc_special3_r6(env, ctx);
@@ -18344,8 +18477,12 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
}
break;
#if defined(TARGET_MIPS64)
- case OPC_DEXTM ... OPC_DEXT:
- case OPC_DINSM ... OPC_DINS:
+ case OPC_DEXTM:
+ case OPC_DEXTU:
+ case OPC_DEXT:
+ case OPC_DINSM:
+ case OPC_DINSU:
+ case OPC_DINS:
check_insn(ctx, ISA_MIPS64R2);
check_mips_64(ctx);
gen_bitops(ctx, op1, rt, rs, sa, rd);
@@ -18353,7 +18490,8 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
case OPC_DBSHFL:
op2 = MASK_DBSHFL(ctx->opcode);
switch (op2) {
- case OPC_DALIGN ... OPC_DALIGN_END:
+ case OPC_DALIGN:
+ case OPC_DALIGN_END:
case OPC_DBITSWAP:
check_insn(ctx, ISA_MIPS32R6);
decode_opc_special3_r6(env, ctx);
@@ -19584,7 +19722,12 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);
}
break;
- case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */
+ case OPC_TGEI: /* REGIMM traps */
+ case OPC_TGEIU:
+ case OPC_TLTI:
+ case OPC_TLTIU:
+ case OPC_TEQI:
+
case OPC_TNEI:
check_insn(ctx, ISA_MIPS2);
check_insn_opc_removed(ctx, ISA_MIPS32R6);
@@ -19759,7 +19902,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_XORI:
gen_logic_imm(ctx, op, rt, rs, imm);
break;
- case OPC_J ... OPC_JAL: /* Jump */
+ case OPC_J: /* Jump */
+ case OPC_JAL:
offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
break;
@@ -19826,15 +19970,20 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_LWR:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* Fallthrough */
- case OPC_LB ... OPC_LH:
- case OPC_LW ... OPC_LHU:
+ case OPC_LB:
+ case OPC_LH:
+ case OPC_LW:
+ case OPC_LWPC:
+ case OPC_LBU:
+ case OPC_LHU:
gen_ld(ctx, op, rt, rs, imm);
break;
case OPC_SWL:
case OPC_SWR:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* fall through */
- case OPC_SB ... OPC_SH:
+ case OPC_SB:
+ case OPC_SH:
case OPC_SW:
gen_st(ctx, op, rt, rs, imm);
break;
@@ -20105,7 +20254,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
#if defined(TARGET_MIPS64)
/* MIPS64 opcodes */
- case OPC_LDL ... OPC_LDR:
+ case OPC_LDL:
+ case OPC_LDR:
case OPC_LLD:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* fall through */
@@ -20115,7 +20265,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
check_mips_64(ctx);
gen_ld(ctx, op, rt, rs, imm);
break;
- case OPC_SDL ... OPC_SDR:
+ case OPC_SDL:
+ case OPC_SDR:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* fall through */
case OPC_SD:
--
2.7.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v4 5/8] target/mips: Add CP0 BadInstrX register
2018-07-06 11:48 [Qemu-devel] [PATCH v4 0/8] Maintenance and misc fixes and improvements Aleksandar Markovic
` (3 preceding siblings ...)
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 4/8] target/mips: Avoid case statements formulated by ranges Aleksandar Markovic
@ 2018-07-06 11:48 ` Aleksandar Markovic
2018-07-06 16:54 ` Philippe Mathieu-Daudé
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 6/8] target/mips: Amend CP0 WatchHi register implementation Aleksandar Markovic
` (2 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Aleksandar Markovic @ 2018-07-06 11:48 UTC (permalink / raw)
To: qemu-devel
Cc: philippe.mathieu.daude, aurelien, richard.henderson, amarkovic,
smarkovic, pjovanovic, pburton
From: Stefan Markovic <smarkovic@wavecomp.com>
Add CP0 BadInstrX register. This register will be used in nanoMIPS.
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/cpu.h | 1 +
target/mips/machine.c | 5 +++--
target/mips/translate.c | 30 +++++++++++++++++++++++++++++-
3 files changed, 33 insertions(+), 3 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 100b5f4..4cd918b 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -323,6 +323,7 @@ struct CPUMIPSState {
target_ulong CP0_BadVAddr;
uint32_t CP0_BadInstr;
uint32_t CP0_BadInstrP;
+ uint32_t CP0_BadInstrX;
int32_t CP0_Count;
target_ulong CP0_EntryHi;
#define CP0EnHi_EHINV 10
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 20100d5..5ba78ac 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -212,8 +212,8 @@ const VMStateDescription vmstate_tlb = {
const VMStateDescription vmstate_mips_cpu = {
.name = "cpu",
- .version_id = 10,
- .minimum_version_id = 10,
+ .version_id = 11,
+ .minimum_version_id = 11,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
/* Active TC */
@@ -266,6 +266,7 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
+ VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
VMSTATE_INT32(env.CP0_Count, MIPSCPU),
VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 051dda5..00154d2 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5315,7 +5315,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
rn = "BadInstrP";
break;
- default:
+ case 3:
+ CP0_CHECK(ctx->bi);
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
+#if defined(TARGET_MIPS64)
+ tcg_gen_andi_i64(arg, arg, ~0xffff);
+#else
+ tcg_gen_andi_i32(arg, arg, ~0xffff);
+#endif
+ rn = "BadInstrX";
+ break;
+ default:
goto cp0_unimplemented;
}
break;
@@ -6006,6 +6016,10 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* ignored */
rn = "BadInstrP";
break;
+ case 3:
+ /* ignored */
+ rn = "BadInstrX";
+ break;
default:
goto cp0_unimplemented;
}
@@ -6711,6 +6725,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
rn = "BadInstrP";
break;
+ case 3:
+ CP0_CHECK(ctx->bi);
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
+#if defined(TARGET_MIPS64)
+ tcg_gen_andi_i64(arg, arg, ~0xffff);
+#else
+ tcg_gen_andi_i32(arg, arg, ~0xffff);
+#endif
+ rn = "BadInstrX";
+ break;
default:
goto cp0_unimplemented;
}
@@ -7385,6 +7409,10 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* ignored */
rn = "BadInstrP";
break;
+ case 3:
+ /* ignored */
+ rn = "BadInstrX";
+ break;
default:
goto cp0_unimplemented;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v4 6/8] target/mips: Amend CP0 WatchHi register implementation
2018-07-06 11:48 [Qemu-devel] [PATCH v4 0/8] Maintenance and misc fixes and improvements Aleksandar Markovic
` (4 preceding siblings ...)
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 5/8] target/mips: Add CP0 BadInstrX register Aleksandar Markovic
@ 2018-07-06 11:48 ` Aleksandar Markovic
2018-07-06 13:40 ` Richard Henderson
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 7/8] target/mips: Don't update BadVAddr register in Debug Mode Aleksandar Markovic
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 8/8] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0 Aleksandar Markovic
7 siblings, 1 reply; 15+ messages in thread
From: Aleksandar Markovic @ 2018-07-06 11:48 UTC (permalink / raw)
To: qemu-devel
Cc: philippe.mathieu.daude, aurelien, richard.henderson, amarkovic,
smarkovic, pjovanovic, pburton
From: Yongbok Kim <yongbok.kim@mips.com>
WatchHi is extended by the field MemoryMapID with the GINVT instruction.
The field is accessible by MTHC0/MFHC0 in 32-bit architectures and DMTC0/
DMFC0 in 64-bit architectures.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 2 +-
target/mips/helper.h | 3 +++
target/mips/machine.c | 6 +++---
target/mips/op_helper.c | 23 +++++++++++++++++++++--
target/mips/translate.c | 28 +++++++++++++++++++++++++++-
5 files changed, 55 insertions(+), 7 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 4cd918b..1206dc3 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -503,7 +503,7 @@ struct CPUMIPSState {
uint64_t CP0_LLAddr_rw_bitmask;
int CP0_LLAddr_shift;
target_ulong CP0_WatchLo[8];
- int32_t CP0_WatchHi[8];
+ uint64_t CP0_WatchHi[8];
#define CP0WH_ASID 16
target_ulong CP0_XContext;
int32_t CP0_Framemask;
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 5f49234..151441a 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -74,6 +74,7 @@ DEF_HELPER_1(mfc0_maar, tl, env)
DEF_HELPER_1(mfhc0_maar, tl, env)
DEF_HELPER_2(mfc0_watchlo, tl, env, i32)
DEF_HELPER_2(mfc0_watchhi, tl, env, i32)
+DEF_HELPER_2(mfhc0_watchhi, tl, env, i32)
DEF_HELPER_1(mfc0_debug, tl, env)
DEF_HELPER_1(mftc0_debug, tl, env)
#ifdef TARGET_MIPS64
@@ -85,6 +86,7 @@ DEF_HELPER_1(dmfc0_tcschefback, tl, env)
DEF_HELPER_1(dmfc0_lladdr, tl, env)
DEF_HELPER_1(dmfc0_maar, tl, env)
DEF_HELPER_2(dmfc0_watchlo, tl, env, i32)
+DEF_HELPER_2(dmfc0_watchhi, tl, env, i32)
#endif /* TARGET_MIPS64 */
DEF_HELPER_2(mtc0_index, void, env, tl)
@@ -148,6 +150,7 @@ DEF_HELPER_2(mthc0_maar, void, env, tl)
DEF_HELPER_2(mtc0_maari, void, env, tl)
DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32)
DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32)
+DEF_HELPER_3(mthc0_watchhi, void, env, tl, i32)
DEF_HELPER_2(mtc0_xcontext, void, env, tl)
DEF_HELPER_2(mtc0_framemask, void, env, tl)
DEF_HELPER_2(mtc0_debug, void, env, tl)
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 5ba78ac..5e9c559 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -212,8 +212,8 @@ const VMStateDescription vmstate_tlb = {
const VMStateDescription vmstate_mips_cpu = {
.name = "cpu",
- .version_id = 11,
- .minimum_version_id = 11,
+ .version_id = 12,
+ .minimum_version_id = 12,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
/* Active TC */
@@ -288,7 +288,7 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_INT32(env.CP0_MAARI, MIPSCPU),
VMSTATE_UINT64(env.lladdr, MIPSCPU),
VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8),
- VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
+ VMSTATE_UINT64_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU),
VMSTATE_INT32(env.CP0_Framemask, MIPSCPU),
VMSTATE_INT32(env.CP0_Debug, MIPSCPU),
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 41d3634..0b8ec7d 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -893,7 +893,12 @@ target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
{
- return env->CP0_WatchHi[sel];
+ return (int32_t) env->CP0_WatchHi[sel];
+}
+
+target_ulong helper_mfhc0_watchhi(CPUMIPSState *env, uint32_t sel)
+{
+ return env->CP0_WatchHi[sel] >> 32;
}
target_ulong helper_mfc0_debug(CPUMIPSState *env)
@@ -961,6 +966,11 @@ target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
{
return env->CP0_WatchLo[sel];
}
+
+target_ulong helper_dmfc0_watchhi(CPUMIPSState *env, uint32_t sel)
+{
+ return env->CP0_WatchHi[sel];
+}
#endif /* TARGET_MIPS64 */
void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
@@ -1662,11 +1672,20 @@ void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
{
- int mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
+ uint64_t mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
+ if ((env->CP0_Config5 >> CP0C5_MI) & 1) {
+ mask |= 0xFFFFFFFF00000000ULL; /* MMID */
+ }
env->CP0_WatchHi[sel] = arg1 & mask;
env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
}
+void helper_mthc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
+{
+ env->CP0_WatchHi[sel] = ((uint64_t) (arg1) << 32) |
+ (env->CP0_WatchHi[sel] & 0x00000000ffffffffULL);
+}
+
void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
{
target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 00154d2..7721ed7 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1458,6 +1458,7 @@ typedef struct DisasContext {
bool mrp;
bool nan2008;
bool abs2008;
+ bool mi;
} DisasContext;
#define DISAS_STOP DISAS_TARGET_0
@@ -4923,6 +4924,18 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
+ case 19:
+ switch (sel) {
+ case 0 ...7:
+ /* upper 32 bits are only available when Config5MI != 0 */
+ CP0_CHECK(ctx->mi);
+ gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_WatchHi[sel]), 0);
+ rn = "WatchHi";
+ break;
+ default:
+ goto cp0_unimplemented;
+ }
+ break;
case 28:
switch (sel) {
case 0:
@@ -4995,6 +5008,18 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
+ case 19:
+ switch (sel) {
+ case 0 ...7:
+ /* upper 32 bits are only available when Config5MI != 0 */
+ CP0_CHECK(ctx->mi);
+ gen_helper_0e1i(mthc0_watchhi, arg, sel);
+ rn = "WatchHi";
+ break;
+ default:
+ goto cp0_unimplemented;
+ }
+ break;
case 28:
switch (sel) {
case 0:
@@ -6935,7 +6960,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
- gen_helper_1e0i(mfc0_watchhi, arg, sel);
+ gen_helper_1e0i(dmfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
default:
@@ -20403,6 +20428,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
+ ctx->mi = (env->CP0_Config5 >> CP0C5_MI) & 1;
restore_cpu_state(env, ctx);
#ifdef CONFIG_USER_ONLY
ctx->mem_idx = MIPS_HFLAG_UM;
--
2.7.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v4 7/8] target/mips: Don't update BadVAddr register in Debug Mode
2018-07-06 11:48 [Qemu-devel] [PATCH v4 0/8] Maintenance and misc fixes and improvements Aleksandar Markovic
` (5 preceding siblings ...)
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 6/8] target/mips: Amend CP0 WatchHi register implementation Aleksandar Markovic
@ 2018-07-06 11:48 ` Aleksandar Markovic
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 8/8] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0 Aleksandar Markovic
7 siblings, 0 replies; 15+ messages in thread
From: Aleksandar Markovic @ 2018-07-06 11:48 UTC (permalink / raw)
To: qemu-devel
Cc: philippe.mathieu.daude, aurelien, richard.henderson, amarkovic,
smarkovic, pjovanovic, pburton
From: Yongbok Kim <yongbok.kim@mips.com>
BadVAddr should not be updated if (env->hflags & MIPS_HFLAG_DM) is
set.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/helper.c | 4 +++-
target/mips/op_helper.c | 12 +++++++++---
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 8cf91ce..e215af9 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -502,7 +502,9 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
break;
}
/* Raise exception */
- env->CP0_BadVAddr = address;
+ if (!(env->hflags & MIPS_HFLAG_DM)) {
+ env->CP0_BadVAddr = address;
+ }
env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
((address >> 9) & 0x007ffff0);
env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) |
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 0b8ec7d..a6a57bd 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -271,7 +271,9 @@ static inline hwaddr do_translate_address(CPUMIPSState *env,
target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
{ \
if (arg & almask) { \
- env->CP0_BadVAddr = arg; \
+ if (!(env->hflags & MIPS_HFLAG_DM)) { \
+ env->CP0_BadVAddr = arg; \
+ } \
do_raise_exception(env, EXCP_AdEL, GETPC()); \
} \
env->lladdr = do_translate_address(env, arg, 0, GETPC()); \
@@ -291,7 +293,9 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
target_long tmp; \
\
if (arg2 & almask) { \
- env->CP0_BadVAddr = arg2; \
+ if (!(env->hflags & MIPS_HFLAG_DM)) { \
+ env->CP0_BadVAddr = arg2; \
+ } \
do_raise_exception(env, EXCP_AdES, GETPC()); \
} \
if (do_translate_address(env, arg2, 1, GETPC()) == env->lladdr) { \
@@ -2456,7 +2460,9 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
int error_code = 0;
int excp;
- env->CP0_BadVAddr = addr;
+ if (!(env->hflags & MIPS_HFLAG_DM)) {
+ env->CP0_BadVAddr = addr;
+ }
if (access_type == MMU_DATA_STORE) {
excp = EXCP_AdES;
--
2.7.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v4 8/8] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0
2018-07-06 11:48 [Qemu-devel] [PATCH v4 0/8] Maintenance and misc fixes and improvements Aleksandar Markovic
` (6 preceding siblings ...)
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 7/8] target/mips: Don't update BadVAddr register in Debug Mode Aleksandar Markovic
@ 2018-07-06 11:48 ` Aleksandar Markovic
7 siblings, 0 replies; 15+ messages in thread
From: Aleksandar Markovic @ 2018-07-06 11:48 UTC (permalink / raw)
To: qemu-devel
Cc: philippe.mathieu.daude, aurelien, richard.henderson, amarkovic,
smarkovic, pjovanovic, pburton
From: Yongbok Kim <yongbok.kim@mips.com>
MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only,
and placing ELPA flag checks befor switch statement were technically
correct. However, after adding handling more registers, these checks
should be moved to act only in cases of handling EntryLo0 and
EntryLo1.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 7721ed7..d4cb6fe 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4885,12 +4885,11 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
{
const char *rn = "invalid";
- CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
-
switch (reg) {
case 2:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
rn = "EntryLo0";
break;
@@ -4901,6 +4900,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 3:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
rn = "EntryLo1";
break;
@@ -4965,12 +4965,11 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
const char *rn = "invalid";
uint64_t mask = ctx->PAMask >> 36;
- CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
-
switch (reg) {
case 2:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
tcg_gen_andi_tl(arg, arg, mask);
gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
rn = "EntryLo0";
@@ -4982,6 +4981,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 3:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
tcg_gen_andi_tl(arg, arg, mask);
gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
rn = "EntryLo1";
--
2.7.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [Qemu-devel] [PATCH v4 6/8] target/mips: Amend CP0 WatchHi register implementation
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 6/8] target/mips: Amend CP0 WatchHi register implementation Aleksandar Markovic
@ 2018-07-06 13:40 ` Richard Henderson
2018-07-06 15:20 ` Aleksandar Markovic
0 siblings, 1 reply; 15+ messages in thread
From: Richard Henderson @ 2018-07-06 13:40 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: philippe.mathieu.daude, aurelien, amarkovic, smarkovic,
pjovanovic, pburton
On 07/06/2018 04:48 AM, Aleksandar Markovic wrote:
> +++ b/target/mips/op_helper.c
> @@ -893,7 +893,12 @@ target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
>
> target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
> {
> - return env->CP0_WatchHi[sel];
> + return (int32_t) env->CP0_WatchHi[sel];
> +}
> +
> +target_ulong helper_mfhc0_watchhi(CPUMIPSState *env, uint32_t sel)
> +{
> + return env->CP0_WatchHi[sel] >> 32;
> }
Did you in fact want the high-part sign-extended as well?
It might be more obvious to write
return sextract64(env->CP0_WatchHi[sel], 32, 32);
in that case.
> +void helper_mthc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
> +{
> + env->CP0_WatchHi[sel] = ((uint64_t) (arg1) << 32) |
> + (env->CP0_WatchHi[sel] & 0x00000000ffffffffULL);
Cleaner as
env->CP0_WatchHi[sel] = deposit64(env->CP0_WatchHi[sel], 32, 32, arg1);
For future cleanup, there is nothing in this (or several other) that requires
writing helper code. This could just as easily be expanded inline with one
single load or store operation.
r~
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Qemu-devel] [PATCH v4 6/8] target/mips: Amend CP0 WatchHi register implementation
2018-07-06 13:40 ` Richard Henderson
@ 2018-07-06 15:20 ` Aleksandar Markovic
0 siblings, 0 replies; 15+ messages in thread
From: Aleksandar Markovic @ 2018-07-06 15:20 UTC (permalink / raw)
To: Richard Henderson, Aleksandar Markovic, qemu-devel@nongnu.org
Cc: philippe.mathieu.daude@gmail.com, aurelien@aurel32.net,
Stefan Markovic, Petar Jovanovic, Paul Burton
> > +++ b/target/mips/op_helper.c
> > @@ -893,7 +893,12 @@ target_ulong helper_mfc0_watchlo(CPUMIPSState *env, > uint32_t sel)
> >
> > target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
> > {
> > - return env->CP0_WatchHi[sel];
> > + return (int32_t) env->CP0_WatchHi[sel];
> > +}
> > +
> > +target_ulong helper_mfhc0_watchhi(CPUMIPSState *env, uint32_t sel)
> > +{
> > + return env->CP0_WatchHi[sel] >> 32;
> > }
>
> Did you in fact want the high-part sign-extended as well?
> It might be more obvious to write
>
> return sextract64(env->CP0_WatchHi[sel], 32, 32);
>
> in that case.
>
> > +void helper_mthc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
> > +{
> > + env->CP0_WatchHi[sel] = ((uint64_t) (arg1) << 32) |
> > + (env->CP0_WatchHi[sel] & 0x00000000ffffffffULL);
>
> Cleaner as
>
> env->CP0_WatchHi[sel] = deposit64(env->CP0_WatchHi[sel], 32, 32, arg1);
>
>
> For future cleanup, there is nothing in this (or several other) that requires
> writing helper code. This could just as easily be expanded inline with one
> single load or store operation.
>
>
> r~>
If this all is the case, I am going to remove this patch from this series. There is no hurry. This patch just needs to be thought over a little bit more. It will be sent in some future series.
Regards,
Aleksandar
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Qemu-devel] [PATCH v4 2/8] target/mips: Workaround for checkpatch.pl hanging on msa_helper.c
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 2/8] target/mips: Workaround for checkpatch.pl hanging on msa_helper.c Aleksandar Markovic
@ 2018-07-06 15:38 ` Aleksandar Markovic
2018-07-06 16:52 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 15+ messages in thread
From: Aleksandar Markovic @ 2018-07-06 15:38 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel@nongnu.org, Paolo Bonzini
Cc: philippe.mathieu.daude@gmail.com, aurelien@aurel32.net,
richard.henderson@linaro.org, Stefan Markovic, Petar Jovanovic,
Paul Burton
Hi, Paolo,
It was an incredibly fast fix! :)
I already confirmed that the fix fixes the problem on msa_helper.c. I would nevertheless like to have this workaround applied. Can you perhaps give it "Reviewed-by"?
Regards,
Aleksandar
> Subject: [PATCH v4 2/8] target/mips: Workaround for checkpatch.pl hanging on > msa_helper.c
>
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> If checkpatch.pl is applied (using switch "-f") on file
> target/mips/msa_helper.c, it will hang.
>
> This is a workaround by correcting the source file. The workaround is
> found by partial deleting and undeleting of the code in msa_helper.c
> in binary search fashion.
>
> The bug (for checkpatch.pl) is already reported to the qemu-devel list.
>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
> target/mips/msa_helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
> index c74e3cd..1691b70 100644
> --- a/target/mips/msa_helper.c
> +++ b/target/mips/msa_helper.c
> @@ -2750,8 +2750,8 @@ void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df, > uint32_t wd,
>
> #define FMAXMIN_A(F, G, X, _S, _T, BITS, STATUS) \
> do { \
> - uint## BITS ##_t S = _S, T = _T; \
> - uint## BITS ##_t as, at, xs, xt, xd; \
> + uint## BITS ## _t S = _S, T = _T; \
> + uint## BITS ## _t as, at, xs, xt, xd; \
> if (NUMBER_QNAN_PAIR(S, T, BITS, STATUS)) { \
> T = S; \
> } \
> --
> 2.7.4
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Qemu-devel] [PATCH v4 2/8] target/mips: Workaround for checkpatch.pl hanging on msa_helper.c
2018-07-06 15:38 ` Aleksandar Markovic
@ 2018-07-06 16:52 ` Philippe Mathieu-Daudé
2018-07-06 17:11 ` Aleksandar Markovic
0 siblings, 1 reply; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-07-06 16:52 UTC (permalink / raw)
To: Aleksandar Markovic, Aleksandar Markovic, qemu-devel@nongnu.org,
Paolo Bonzini
Cc: philippe.mathieu.daude@gmail.com, aurelien@aurel32.net,
richard.henderson@linaro.org, Stefan Markovic, Petar Jovanovic,
Paul Burton
Hi Aleksandar,
On 07/06/2018 12:38 PM, Aleksandar Markovic wrote:
> Hi, Paolo,
>
> It was an incredibly fast fix! :)
>
> I already confirmed that the fix fixes the problem on msa_helper.c. I would nevertheless like to have this workaround applied. Can you perhaps give it "Reviewed-by"?
>
> Regards,
> Aleksandar
>
>
>> Subject: [PATCH v4 2/8] target/mips: Workaround for checkpatch.pl hanging on > msa_helper.c
>>
>> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>>
>> If checkpatch.pl is applied (using switch "-f") on file
>> target/mips/msa_helper.c, it will hang.
>>
>> This is a workaround by correcting the source file. The workaround is
>> found by partial deleting and undeleting of the code in msa_helper.c
>> in binary search fashion.
>>
>> The bug (for checkpatch.pl) is already reported to the qemu-devel list.
>>
>> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
>> ---
>> target/mips/msa_helper.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
>> index c74e3cd..1691b70 100644
>> --- a/target/mips/msa_helper.c
>> +++ b/target/mips/msa_helper.c
>> @@ -2750,8 +2750,8 @@ void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df, > uint32_t wd,
>>
>> #define FMAXMIN_A(F, G, X, _S, _T, BITS, STATUS) \
>> do { \
>> - uint## BITS ##_t S = _S, T = _T; \
>> - uint## BITS ##_t as, at, xs, xt, xd; \
>> + uint## BITS ## _t S = _S, T = _T; \
>> + uint## BITS ## _t as, at, xs, xt, xd; \
I'm not sure it's worth having this but you are the maintainer so your
choice :) What is unclear to me is, while changing this, why only fix
the suffix and not also the prefix? That is:
uint<space>## BITS ##<space>_t S = _S, T = _T;
>> if (NUMBER_QNAN_PAIR(S, T, BITS, STATUS)) { \
>> T = S; \
>> } \
>> --
>> 2.7.4
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Qemu-devel] [PATCH v4 5/8] target/mips: Add CP0 BadInstrX register
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 5/8] target/mips: Add CP0 BadInstrX register Aleksandar Markovic
@ 2018-07-06 16:54 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-07-06 16:54 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
pburton
On 07/06/2018 08:48 AM, Aleksandar Markovic wrote:
> From: Stefan Markovic <smarkovic@wavecomp.com>
>
> Add CP0 BadInstrX register. This register will be used in nanoMIPS.
>
> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/cpu.h | 1 +
> target/mips/machine.c | 5 +++--
> target/mips/translate.c | 30 +++++++++++++++++++++++++++++-
> 3 files changed, 33 insertions(+), 3 deletions(-)
>
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 100b5f4..4cd918b 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -323,6 +323,7 @@ struct CPUMIPSState {
> target_ulong CP0_BadVAddr;
> uint32_t CP0_BadInstr;
> uint32_t CP0_BadInstrP;
> + uint32_t CP0_BadInstrX;
> int32_t CP0_Count;
> target_ulong CP0_EntryHi;
> #define CP0EnHi_EHINV 10
> diff --git a/target/mips/machine.c b/target/mips/machine.c
> index 20100d5..5ba78ac 100644
> --- a/target/mips/machine.c
> +++ b/target/mips/machine.c
> @@ -212,8 +212,8 @@ const VMStateDescription vmstate_tlb = {
>
> const VMStateDescription vmstate_mips_cpu = {
> .name = "cpu",
> - .version_id = 10,
> - .minimum_version_id = 10,
> + .version_id = 11,
> + .minimum_version_id = 11,
> .post_load = cpu_post_load,
> .fields = (VMStateField[]) {
> /* Active TC */
> @@ -266,6 +266,7 @@ const VMStateDescription vmstate_mips_cpu = {
> VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
> VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
> VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
> + VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
> VMSTATE_INT32(env.CP0_Count, MIPSCPU),
> VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
> VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 051dda5..00154d2 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -5315,7 +5315,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
> rn = "BadInstrP";
> break;
> - default:
> + case 3:
> + CP0_CHECK(ctx->bi);
> + gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
> +#if defined(TARGET_MIPS64)
> + tcg_gen_andi_i64(arg, arg, ~0xffff);
> +#else
> + tcg_gen_andi_i32(arg, arg, ~0xffff);
> +#endif
Please use tcg_gen_andi_tl() instead, it does exactly that.
> + rn = "BadInstrX";
> + break;
> + default:
> goto cp0_unimplemented;
> }
> break;
> @@ -6006,6 +6016,10 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> /* ignored */
> rn = "BadInstrP";
> break;
> + case 3:
> + /* ignored */
> + rn = "BadInstrX";
> + break;
> default:
> goto cp0_unimplemented;
> }
> @@ -6711,6 +6725,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
> rn = "BadInstrP";
> break;
> + case 3:
> + CP0_CHECK(ctx->bi);
> + gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
> +#if defined(TARGET_MIPS64)
> + tcg_gen_andi_i64(arg, arg, ~0xffff);
> +#else
> + tcg_gen_andi_i32(arg, arg, ~0xffff);
> +#endif
Ditto.
> + rn = "BadInstrX";
> + break;
> default:
> goto cp0_unimplemented;
> }
> @@ -7385,6 +7409,10 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> /* ignored */
> rn = "BadInstrP";
> break;
> + case 3:
> + /* ignored */
> + rn = "BadInstrX";
> + break;
> default:
> goto cp0_unimplemented;
> }
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Qemu-devel] [PATCH v4 2/8] target/mips: Workaround for checkpatch.pl hanging on msa_helper.c
2018-07-06 16:52 ` Philippe Mathieu-Daudé
@ 2018-07-06 17:11 ` Aleksandar Markovic
0 siblings, 0 replies; 15+ messages in thread
From: Aleksandar Markovic @ 2018-07-06 17:11 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Aleksandar Markovic,
qemu-devel@nongnu.org, Paolo Bonzini
Cc: philippe.mathieu.daude@gmail.com, aurelien@aurel32.net,
richard.henderson@linaro.org, Stefan Markovic, Petar Jovanovic,
Paul Burton
> I'm not sure it's worth having this but you are the maintainer so your
> choice :)
If someone in future peruses an older version of this file (let's say, while working on an older version of QEMU), and comes across this problem with checkpatch.pl, by checking the full history of the file, they would be able to see what the problem is. Without this patch, they wouldn't.
> What is unclear to me is, while changing this, why only fix
> the suffix and not also the prefix? That is:
>
> uint<space>## BITS ##<space>_t S = _S, T = _T;
It wouldn't be clear what characters caused the problem (or triggered the bug, if you wish).
Regards,
Aleksandar
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2018-07-06 17:11 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
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2018-07-06 11:48 [Qemu-devel] [PATCH v4 0/8] Maintenance and misc fixes and improvements Aleksandar Markovic
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 1/8] target/mips: Update maintainer's email addresses Aleksandar Markovic
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 2/8] target/mips: Workaround for checkpatch.pl hanging on msa_helper.c Aleksandar Markovic
2018-07-06 15:38 ` Aleksandar Markovic
2018-07-06 16:52 ` Philippe Mathieu-Daudé
2018-07-06 17:11 ` Aleksandar Markovic
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 3/8] target/mips: Update some CP0 registers bit definitions Aleksandar Markovic
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 4/8] target/mips: Avoid case statements formulated by ranges Aleksandar Markovic
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 5/8] target/mips: Add CP0 BadInstrX register Aleksandar Markovic
2018-07-06 16:54 ` Philippe Mathieu-Daudé
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 6/8] target/mips: Amend CP0 WatchHi register implementation Aleksandar Markovic
2018-07-06 13:40 ` Richard Henderson
2018-07-06 15:20 ` Aleksandar Markovic
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 7/8] target/mips: Don't update BadVAddr register in Debug Mode Aleksandar Markovic
2018-07-06 11:48 ` [Qemu-devel] [PATCH v4 8/8] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0 Aleksandar Markovic
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