From: Jingqi Liu <jingqi.liu@intel.com>
To: pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com
Cc: qemu-devel@nongnu.org, wei.w.wang@intel.com,
Jingqi Liu <jingqi.liu@intel.com>
Subject: [Qemu-devel] [PATCH 1/3] x86/cpu: Enable UMONITOR/UMWAIT/TPAUSE cpu features
Date: Tue, 10 Jul 2018 16:57:32 +0800 [thread overview]
Message-ID: <1531213054-63327-2-git-send-email-jingqi.liu@intel.com> (raw)
In-Reply-To: <1531213054-63327-1-git-send-email-jingqi.liu@intel.com>
UMONITOR, UMWAIT, and TPAUSE are a set of user wait instructions.
UMONITOR arms address monitoring hardware using an address. A store
to an address within the specified address range triggers the
monitoring hardware to wake up the processor waiting in umwait.
UMWAIT instructs the processor to enter an implementation-dependent
optimized state while monitoring a range of addresses. The optimized
state may be either a light-weight power/performance optimized state
or an improved power/performance optimized state.
TPAUSE instructs the processor to enter an implementation-dependent
optimized state c0.1 or c0.2 state and wake up when time-stamp counter
reaches specified timeout.
The bit definition:
CPUID.(EAX=7,ECX=0):ECX[bit 05] WAITPKG
The release document ref below link:
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf
Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e0e2f2e..e0d151f 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -978,7 +978,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
[FEAT_7_0_ECX] = {
.feat_names = {
NULL, "avx512vbmi", "umip", "pku",
- NULL /* ospke */, NULL, "avx512vbmi2", NULL,
+ NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
"gfni", "vaes", "vpclmulqdq", "avx512vnni",
"avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
"la57", NULL, NULL, NULL,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 2c5a0d9..f651105 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -674,6 +674,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_ECX_UMIP (1U << 2)
#define CPUID_7_0_ECX_PKU (1U << 3)
#define CPUID_7_0_ECX_OSPKE (1U << 4)
+#define CPUID_7_0_ECX_WAITPKG (1U << 5) /* UMONITOR/UMWAIT/TPAUSE Instructions */
#define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */
#define CPUID_7_0_ECX_GFNI (1U << 8)
#define CPUID_7_0_ECX_VAES (1U << 9)
--
1.8.3.1
next prev parent reply other threads:[~2018-07-10 8:58 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-10 8:57 [Qemu-devel] [PATCH 0/3] x86/cpu: Enable a few new cpu features Jingqi Liu
2018-07-10 8:57 ` Jingqi Liu [this message]
2018-08-06 22:03 ` [Qemu-devel] [PATCH 1/3] x86/cpu: Enable UMONITOR/UMWAIT/TPAUSE " Eduardo Habkost
2018-08-20 12:38 ` Liu, Jingqi
2018-07-10 8:57 ` [Qemu-devel] [PATCH 2/3] x86/cpu: Enable MOVDIRI cpu feature Jingqi Liu
2018-07-10 8:57 ` [Qemu-devel] [PATCH 3/3] x86/cpu: Enable MOVDIR64B " Jingqi Liu
2018-07-16 14:59 ` [Qemu-devel] [PATCH 0/3] x86/cpu: Enable a few new cpu features Paolo Bonzini
2018-07-17 1:12 ` Liu, Jingqi
2018-08-06 8:21 ` Liu, Jingqi
2018-08-06 16:59 ` Paolo Bonzini
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