From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50483) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fcoTR-0003Ce-4i for qemu-devel@nongnu.org; Tue, 10 Jul 2018 04:58:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fcoTO-0003z8-GB for qemu-devel@nongnu.org; Tue, 10 Jul 2018 04:58:17 -0400 Received: from mga03.intel.com ([134.134.136.65]:51105) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fcoTO-0003yN-5z for qemu-devel@nongnu.org; Tue, 10 Jul 2018 04:58:14 -0400 From: Jingqi Liu Date: Tue, 10 Jul 2018 16:57:34 +0800 Message-Id: <1531213054-63327-4-git-send-email-jingqi.liu@intel.com> In-Reply-To: <1531213054-63327-1-git-send-email-jingqi.liu@intel.com> References: <1531213054-63327-1-git-send-email-jingqi.liu@intel.com> Subject: [Qemu-devel] [PATCH 3/3] x86/cpu: Enable MOVDIR64B cpu feature List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com Cc: qemu-devel@nongnu.org, wei.w.wang@intel.com, Jingqi Liu MOVDIR64B moves 64-bytes as direct-store with 64-bytes write atomicity. Direct store is implemented by using write combining (WC) for writing data directly into memory without caching the data. The bit definition: CPUID.(EAX=7,ECX=0):ECX[bit 28] MOVDIR64B The release document ref below link: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Signed-off-by: Jingqi Liu --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 775cfcb..fc0b678 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -984,7 +984,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "la57", NULL, NULL, NULL, NULL, NULL, "rdpid", NULL, NULL, "cldemote", NULL, "movdiri", - NULL, NULL, NULL, NULL, + "movdir64b", NULL, NULL, NULL, }, .cpuid_eax = 7, .cpuid_needs_ecx = true, .cpuid_ecx = 0, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d94bf2d..8014c1c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -686,6 +686,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_ECX_RDPID (1U << 22) #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) /* CLDEMOTE Instruction */ #define CPUID_7_0_ECX_MOVDIRI (1U << 27) /* MOVDIRI Instruction */ +#define CPUID_7_0_ECX_MOVDIR64B (1U << 28) /* MOVDIR64B Instruction */ #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ -- 1.8.3.1