[Qemu-devel] [PATCH 0/3] x86/cpu: Enable a few new cpu features

[Qemu-devel] [PATCH 0/3] x86/cpu: Enable a few new cpu features

[Jingqi Liu]

Enable a few new cpu features including UMONITOR, UMWAIT, TPAUSE,
MOVDIRI and MOVDIR64B.

UMONITOR, UMWAIT, and TPAUSE are a set of user wait instructions.
MOVDIRI moves doubleword or quadword from register to memory through
direct store.
MOVDIR64B moves 64-bytes as direct-store with 64-bytes write atomicity.

The bits definition:
CPUID.(EAX=7,ECX=0):ECX[bit 05] WAITPKG
CPUID.(EAX=7,ECX=0):ECX[bit 27] MOVDIRI
CPUID.(EAX=7,ECX=0):ECX[bit 28] MOVDIR64B

The release document ref below link:
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf

Jingqi Liu (3):
  x86/cpu: Enable UMONITOR/UMWAIT/TPAUSE cpu features
  x86/cpu: Enable MOVDIRI cpu feature
  x86/cpu: Enable MOVDIR64B cpu feature

 target/i386/cpu.c | 6 +++---
 target/i386/cpu.h | 3 +++
 2 files changed, 6 insertions(+), 3 deletions(-)

-- 
1.8.3.1

[Qemu-devel] [PATCH 1/3] x86/cpu: Enable UMONITOR/UMWAIT/TPAUSE cpu features

[Jingqi Liu]

UMONITOR, UMWAIT, and TPAUSE are a set of user wait instructions.

UMONITOR arms address monitoring hardware using an address. A store
to an address within the specified address range triggers the
monitoring hardware to wake up the processor waiting in umwait.

UMWAIT instructs the processor to enter an implementation-dependent
optimized state while monitoring a range of addresses. The optimized
state may be either a light-weight power/performance optimized state
or an improved power/performance optimized state.

TPAUSE instructs the processor to enter an implementation-dependent
optimized state c0.1 or c0.2 state and wake up when time-stamp counter
reaches specified timeout.

The bit definition:
CPUID.(EAX=7,ECX=0):ECX[bit 05] WAITPKG

The release document ref below link:
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf

Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>
---
 target/i386/cpu.c | 2 +-
 target/i386/cpu.h | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e0e2f2e..e0d151f 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -978,7 +978,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
     [FEAT_7_0_ECX] = {
         .feat_names = {
             NULL, "avx512vbmi", "umip", "pku",
-            NULL /* ospke */, NULL, "avx512vbmi2", NULL,
+            NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
             "gfni", "vaes", "vpclmulqdq", "avx512vnni",
             "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
             "la57", NULL, NULL, NULL,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 2c5a0d9..f651105 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -674,6 +674,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
 #define CPUID_7_0_ECX_UMIP     (1U << 2)
 #define CPUID_7_0_ECX_PKU      (1U << 3)
 #define CPUID_7_0_ECX_OSPKE    (1U << 4)
+#define CPUID_7_0_ECX_WAITPKG  (1U << 5) /* UMONITOR/UMWAIT/TPAUSE Instructions */
 #define CPUID_7_0_ECX_VBMI2    (1U << 6) /* Additional VBMI Instrs */
 #define CPUID_7_0_ECX_GFNI     (1U << 8)
 #define CPUID_7_0_ECX_VAES     (1U << 9)
-- 
1.8.3.1

Re: [Qemu-devel] [PATCH 1/3] x86/cpu: Enable UMONITOR/UMWAIT/TPAUSE cpu features

[Eduardo Habkost]

On Tue, Jul 10, 2018 at 04:57:32PM +0800, Jingqi Liu wrote:
> UMONITOR, UMWAIT, and TPAUSE are a set of user wait instructions.
> 
> UMONITOR arms address monitoring hardware using an address. A store
> to an address within the specified address range triggers the
> monitoring hardware to wake up the processor waiting in umwait.
> 
> UMWAIT instructs the processor to enter an implementation-dependent
> optimized state while monitoring a range of addresses. The optimized
> state may be either a light-weight power/performance optimized state
> or an improved power/performance optimized state.
> 
> TPAUSE instructs the processor to enter an implementation-dependent
> optimized state c0.1 or c0.2 state and wake up when time-stamp counter
> reaches specified timeout.
> 
> The bit definition:
> CPUID.(EAX=7,ECX=0):ECX[bit 05] WAITPKG
> 
> The release document ref below link:
> https://software.intel.com/sites/default/files/managed/c5/15/\
> architecture-instruction-set-extensions-programming-reference.pdf
> 
> Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>

Is it really OK to expose these features to the guest without
"-overcommit cpu-pm=on"?

Don't we need code to migrate IA32_UMWAIT_CONTROL?

(I don't see code to handle writes to IA32_UMWAIT_CONTROL on the
KVM patches, either.)

-- 
Eduardo

Re: [Qemu-devel] [PATCH 1/3] x86/cpu: Enable UMONITOR/UMWAIT/TPAUSE cpu features

[Liu, Jingqi]

> -----Original Message-----
> From: Eduardo Habkost [mailto:ehabkost@redhat.com]
> Sent: Tuesday, August 7, 2018 6:03 AM
> To: Liu, Jingqi <jingqi.liu@intel.com>
> Cc: pbonzini@redhat.com; rth@twiddle.net; Wang, Wei W
> <wei.w.wang@intel.com>; qemu-devel@nongnu.org; Michael S. Tsirkin
> <mst@redhat.com>
> Subject: Re: [Qemu-devel] [PATCH 1/3] x86/cpu: Enable
> UMONITOR/UMWAIT/TPAUSE cpu features
> 
> On Tue, Jul 10, 2018 at 04:57:32PM +0800, Jingqi Liu wrote:
> > UMONITOR, UMWAIT, and TPAUSE are a set of user wait instructions.
> >
> > UMONITOR arms address monitoring hardware using an address. A store to
> > an address within the specified address range triggers the monitoring
> > hardware to wake up the processor waiting in umwait.
> >
> > UMWAIT instructs the processor to enter an implementation-dependent
> > optimized state while monitoring a range of addresses. The optimized
> > state may be either a light-weight power/performance optimized state
> > or an improved power/performance optimized state.
> >
> > TPAUSE instructs the processor to enter an implementation-dependent
> > optimized state c0.1 or c0.2 state and wake up when time-stamp counter
> > reaches specified timeout.
> >
> > The bit definition:
> > CPUID.(EAX=7,ECX=0):ECX[bit 05] WAITPKG
> >
> > The release document ref below link:
> > https://software.intel.com/sites/default/files/managed/c5/15/\
> > architecture-instruction-set-extensions-programming-reference.pdf
> >
> > Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>
> 
> Is it really OK to expose these features to the guest without "-overcommit cpu-
> pm=on"?
> 
> Don't we need code to migrate IA32_UMWAIT_CONTROL?
> 
> (I don't see code to handle writes to IA32_UMWAIT_CONTROL on the KVM
> patches, either.)
> 
> --
Hi Eduardo,

Yes, I'll handle IA32_UMWAIT_CONTROL in the second version.
Thanks for your review.

> Eduardo

[Qemu-devel] [PATCH 2/3] x86/cpu: Enable MOVDIRI cpu feature

[Jingqi Liu]

MOVDIRI moves doubleword or quadword from register to memory through
direct store which is implemented by using write combining (WC) for
writing data directly into memory without caching the data.

The bit definition:
CPUID.(EAX=7,ECX=0):ECX[bit 27] MOVDIRI

The release document ref below link:
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf

Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>
---
 target/i386/cpu.c | 2 +-
 target/i386/cpu.h | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e0d151f..775cfcb 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -983,7 +983,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
             "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
             "la57", NULL, NULL, NULL,
             NULL, NULL, "rdpid", NULL,
-            NULL, "cldemote", NULL, NULL,
+            NULL, "cldemote", NULL, "movdiri",
             NULL, NULL, NULL, NULL,
         },
         .cpuid_eax = 7,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index f651105..d94bf2d 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -685,6 +685,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
 #define CPUID_7_0_ECX_LA57     (1U << 16)
 #define CPUID_7_0_ECX_RDPID    (1U << 22)
 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25)  /* CLDEMOTE Instruction */
+#define CPUID_7_0_ECX_MOVDIRI  (1U << 27)  /* MOVDIRI Instruction */
 
 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
-- 
1.8.3.1

[Qemu-devel] [PATCH 3/3] x86/cpu: Enable MOVDIR64B cpu feature

[Jingqi Liu]

MOVDIR64B moves 64-bytes as direct-store with 64-bytes write atomicity.
Direct store is implemented by using write combining (WC) for writing
data directly into memory without caching the data.

The bit definition:
CPUID.(EAX=7,ECX=0):ECX[bit 28] MOVDIR64B

The release document ref below link:
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf

Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>
---
 target/i386/cpu.c | 2 +-
 target/i386/cpu.h | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 775cfcb..fc0b678 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -984,7 +984,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
             "la57", NULL, NULL, NULL,
             NULL, NULL, "rdpid", NULL,
             NULL, "cldemote", NULL, "movdiri",
-            NULL, NULL, NULL, NULL,
+            "movdir64b", NULL, NULL, NULL,
         },
         .cpuid_eax = 7,
         .cpuid_needs_ecx = true, .cpuid_ecx = 0,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index d94bf2d..8014c1c 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -686,6 +686,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
 #define CPUID_7_0_ECX_RDPID    (1U << 22)
 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25)  /* CLDEMOTE Instruction */
 #define CPUID_7_0_ECX_MOVDIRI  (1U << 27)  /* MOVDIRI Instruction */
+#define CPUID_7_0_ECX_MOVDIR64B (1U << 28) /* MOVDIR64B Instruction */
 
 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
-- 
1.8.3.1

Re: [Qemu-devel] [PATCH 0/3] x86/cpu: Enable a few new cpu features

[Paolo Bonzini]

On 10/07/2018 10:57, Jingqi Liu wrote:
> Enable a few new cpu features including UMONITOR, UMWAIT, TPAUSE,
> MOVDIRI and MOVDIR64B.
> 
> UMONITOR, UMWAIT, and TPAUSE are a set of user wait instructions.
> MOVDIRI moves doubleword or quadword from register to memory through
> direct store.
> MOVDIR64B moves 64-bytes as direct-store with 64-bytes write atomicity.

Do you have corresponding KVM changes?

Paolo

> The bits definition:
> CPUID.(EAX=7,ECX=0):ECX[bit 05] WAITPKG
> CPUID.(EAX=7,ECX=0):ECX[bit 27] MOVDIRI
> CPUID.(EAX=7,ECX=0):ECX[bit 28] MOVDIR64B
> 
> The release document ref below link:
> https://software.intel.com/sites/default/files/managed/c5/15/\
> architecture-instruction-set-extensions-programming-reference.pdf
> 
> Jingqi Liu (3):
>   x86/cpu: Enable UMONITOR/UMWAIT/TPAUSE cpu features
>   x86/cpu: Enable MOVDIRI cpu feature
>   x86/cpu: Enable MOVDIR64B cpu feature
> 
>  target/i386/cpu.c | 6 +++---
>  target/i386/cpu.h | 3 +++
>  2 files changed, 6 insertions(+), 3 deletions(-)
> 

Re: [Qemu-devel] [PATCH 0/3] x86/cpu: Enable a few new cpu features

[Liu, Jingqi]

On 7/16/2018 10:59 PM, Paolo Bonzini wrote:
> On 10/07/2018 10:57, Jingqi Liu wrote:
>> Enable a few new cpu features including UMONITOR, UMWAIT, TPAUSE,
>> MOVDIRI and MOVDIR64B.
>>
>> UMONITOR, UMWAIT, and TPAUSE are a set of user wait instructions.
>> MOVDIRI moves doubleword or quadword from register to memory through
>> direct store.
>> MOVDIR64B moves 64-bytes as direct-store with 64-bytes write atomicity.
> Do you have corresponding KVM changes?
Yes, the corresponding links are listed as below.
https://www.spinics.net/lists/kvm/msg171563.html
https://www.spinics.net/lists/kernel/msg2850965.html
The patches had been sent for your review also.
Thanks
Jingqi Liu
>
> Paolo
>
>> The bits definition:
>> CPUID.(EAX=7,ECX=0):ECX[bit 05] WAITPKG
>> CPUID.(EAX=7,ECX=0):ECX[bit 27] MOVDIRI
>> CPUID.(EAX=7,ECX=0):ECX[bit 28] MOVDIR64B
>>
>> The release document ref below link:
>> https://software.intel.com/sites/default/files/managed/c5/15/\
>> architecture-instruction-set-extensions-programming-reference.pdf
>>
>> Jingqi Liu (3):
>>    x86/cpu: Enable UMONITOR/UMWAIT/TPAUSE cpu features
>>    x86/cpu: Enable MOVDIRI cpu feature
>>    x86/cpu: Enable MOVDIR64B cpu feature
>>
>>   target/i386/cpu.c | 6 +++---
>>   target/i386/cpu.h | 3 +++
>>   2 files changed, 6 insertions(+), 3 deletions(-)
>>

Re: [Qemu-devel] [PATCH 0/3] x86/cpu: Enable a few new cpu features

[Liu, Jingqi]

Hi Paolo & Eduardo,

Do you have any comments for the series ?
Thanks

On 7/16/2018 10:59 PM, Paolo Bonzini wrote:
> On 10/07/2018 10:57, Jingqi Liu wrote:
>> Enable a few new cpu features including UMONITOR, UMWAIT, TPAUSE,
>> MOVDIRI and MOVDIR64B.
>>
>> UMONITOR, UMWAIT, and TPAUSE are a set of user wait instructions.
>> MOVDIRI moves doubleword or quadword from register to memory through
>> direct store.
>> MOVDIR64B moves 64-bytes as direct-store with 64-bytes write atomicity.
> Do you have corresponding KVM changes?
>
> Paolo
>
>> The bits definition:
>> CPUID.(EAX=7,ECX=0):ECX[bit 05] WAITPKG
>> CPUID.(EAX=7,ECX=0):ECX[bit 27] MOVDIRI
>> CPUID.(EAX=7,ECX=0):ECX[bit 28] MOVDIR64B
>>
>> The release document ref below link:
>> https://software.intel.com/sites/default/files/managed/c5/15/\
>> architecture-instruction-set-extensions-programming-reference.pdf
>>
>> Jingqi Liu (3):
>>    x86/cpu: Enable UMONITOR/UMWAIT/TPAUSE cpu features
>>    x86/cpu: Enable MOVDIRI cpu feature
>>    x86/cpu: Enable MOVDIR64B cpu feature
>>
>>   target/i386/cpu.c | 6 +++---
>>   target/i386/cpu.h | 3 +++
>>   2 files changed, 6 insertions(+), 3 deletions(-)
>>

Re: [Qemu-devel] [PATCH 0/3] x86/cpu: Enable a few new cpu features

[Paolo Bonzini]

On 06/08/2018 10:21, Liu, Jingqi wrote:
> Hi Paolo & Eduardo,
> 
> Do you have any comments for the series ?
> Thanks
> 

Hi,

QEMU is currently in feature freeze.  We will look at the series soon
after QEMU 3.0 is released.

Paolo