[Qemu-devel] [PATCH] hw/riscv/sifive_u: Fix introspection problem in the "riscv.sifive.u.soc" device

[Qemu-devel] [PATCH] hw/riscv/sifive_u: Fix introspection problem in the "riscv.sifive.u.soc" device

[Thomas Huth]

Valgrind complains:

echo "{'execute':'qmp_capabilities'} {'execute':'device-list-properties'," \
 "'arguments':{'typename':'riscv.sifive.u.soc'}}" \
 "{'execute': 'human-monitor-command', " \
 "'arguments': {'command-line': 'info qtree'}}" | \
 valgrind -q riscv32-softmmu/qemu-system-riscv32 -M none,accel=qtest -qmp stdio
[...]
==28083== Invalid read of size 8
==28083==    at 0x2E036A: qdev_print (qdev-monitor.c:686)
==28083==    by 0x2E036A: qbus_print (qdev-monitor.c:719)
==28083==    by 0x268938: handle_hmp_command (monitor.c:3446)
[...]

Use the new object_initialize_child() and sysbus_init_child_obj() functions
to fix the problem.

Signed-off-by: Thomas Huth <thuth@redhat.com>
---
 hw/riscv/sifive_u.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 3a6ffeb..459ec90 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -303,16 +303,15 @@ static void riscv_sifive_u_soc_init(Object *obj)
 {
     SiFiveUSoCState *s = RISCV_U_SOC(obj);
 
-    object_initialize(&s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY);
-    object_property_add_child(obj, "cpus", OBJECT(&s->cpus),
-                              &error_abort);
+    object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus),
+                            TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
     object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type",
                             &error_abort);
     object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
                             &error_abort);
 
-    object_initialize(&s->gem, sizeof(s->gem), TYPE_CADENCE_GEM);
-    qdev_set_parent_bus(DEVICE(&s->gem), sysbus_get_default());
+    sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
+                          TYPE_CADENCE_GEM);
 }
 
 static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
-- 
1.8.3.1

Re: [Qemu-devel] [PATCH] hw/riscv/sifive_u: Fix introspection problem in the "riscv.sifive.u.soc" device

[Philippe Mathieu-Daudé]

On 07/17/2018 12:02 PM, Thomas Huth wrote:
> Valgrind complains:
> 
> echo "{'execute':'qmp_capabilities'} {'execute':'device-list-properties'," \
>  "'arguments':{'typename':'riscv.sifive.u.soc'}}" \
>  "{'execute': 'human-monitor-command', " \
>  "'arguments': {'command-line': 'info qtree'}}" | \
>  valgrind -q riscv32-softmmu/qemu-system-riscv32 -M none,accel=qtest -qmp stdio
> [...]
> ==28083== Invalid read of size 8
> ==28083==    at 0x2E036A: qdev_print (qdev-monitor.c:686)
> ==28083==    by 0x2E036A: qbus_print (qdev-monitor.c:719)
> ==28083==    by 0x268938: handle_hmp_command (monitor.c:3446)
> [...]
> 
> Use the new object_initialize_child() and sysbus_init_child_obj() functions
> to fix the problem.
> 
> Signed-off-by: Thomas Huth <thuth@redhat.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  hw/riscv/sifive_u.c | 9 ++++-----
>  1 file changed, 4 insertions(+), 5 deletions(-)
> 
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 3a6ffeb..459ec90 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -303,16 +303,15 @@ static void riscv_sifive_u_soc_init(Object *obj)
>  {
>      SiFiveUSoCState *s = RISCV_U_SOC(obj);
>  
> -    object_initialize(&s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY);
> -    object_property_add_child(obj, "cpus", OBJECT(&s->cpus),
> -                              &error_abort);
> +    object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus),
> +                            TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
>      object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type",
>                              &error_abort);
>      object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
>                              &error_abort);
>  
> -    object_initialize(&s->gem, sizeof(s->gem), TYPE_CADENCE_GEM);
> -    qdev_set_parent_bus(DEVICE(&s->gem), sysbus_get_default());
> +    sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
> +                          TYPE_CADENCE_GEM);
>  }
>  
>  static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
>