From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56562) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1flEWy-0005M5-RI for qemu-devel@nongnu.org; Thu, 02 Aug 2018 10:24:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1flEWx-0007yn-QB for qemu-devel@nongnu.org; Thu, 02 Aug 2018 10:24:44 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46857 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1flEWx-0007y6-If for qemu-devel@nongnu.org; Thu, 02 Aug 2018 10:24:43 -0400 From: Stefan Markovic Date: Thu, 2 Aug 2018 16:16:04 +0200 Message-Id: <1533219424-7627-18-git-send-email-stefan.markovic@rt-rk.com> In-Reply-To: <1533219424-7627-1-git-send-email-stefan.markovic@rt-rk.com> References: <1533219424-7627-1-git-send-email-stefan.markovic@rt-rk.com> Subject: [Qemu-devel] [PATCH v6 17/77] target/mips: Add placeholder and invocation of decode_nanomips_opc() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: laurent@vivier.eu, riku.voipio@iki.fi, philippe.mathieu.daude@gmail.com, aurelien@aurel32.net, richard.henderson@linaro.org, amarkovic@wavecomp.com, smarkovic@wavecomp.com, pjovanovic@wavecomp.com, pburton@wavecomp.com, arikalo@wavecomp.com From: Aleksandar Markovic Add empty body and invocation of decode_nanomips_opc() if the bit ISA_NANOMIPS32 is set in ctx->insn_flags. Reviewed-by: Richard Henderson Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/translate.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index c1843c1..c59ef5c 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16468,6 +16468,19 @@ enum { NM_EVP = 0x01, }; + +/* + * + * nanoMIPS decoding engine + * + */ + +static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) +{ + return 2; +} + + /* SmartMIPS extension to MIPS32 */ #if defined(TARGET_MIPS64) @@ -21273,6 +21286,9 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); insn_bytes = 4; decode_opc(env, ctx); + } else if (ctx->insn_flags & ISA_NANOMIPS32) { + ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next); + insn_bytes = decode_nanomips_opc(env, ctx); } else if (ctx->insn_flags & ASE_MICROMIPS) { ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next); insn_bytes = decode_micromips_opc(env, ctx); -- 1.9.1