From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56926) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1flEYS-0007Ma-B1 for qemu-devel@nongnu.org; Thu, 02 Aug 2018 10:26:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1flEYO-0000ew-9a for qemu-devel@nongnu.org; Thu, 02 Aug 2018 10:26:16 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:51441 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1flEYO-0000cC-2X for qemu-devel@nongnu.org; Thu, 02 Aug 2018 10:26:12 -0400 From: Stefan Markovic Date: Thu, 2 Aug 2018 16:16:08 +0200 Message-Id: <1533219424-7627-22-git-send-email-stefan.markovic@rt-rk.com> In-Reply-To: <1533219424-7627-1-git-send-email-stefan.markovic@rt-rk.com> References: <1533219424-7627-1-git-send-email-stefan.markovic@rt-rk.com> Subject: [Qemu-devel] [PATCH v6 21/77] target/mips: Add emulation of nanoMIPS 16-bit shift instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: laurent@vivier.eu, riku.voipio@iki.fi, philippe.mathieu.daude@gmail.com, aurelien@aurel32.net, richard.henderson@linaro.org, amarkovic@wavecomp.com, smarkovic@wavecomp.com, pjovanovic@wavecomp.com, pburton@wavecomp.com, arikalo@wavecomp.com From: Yongbok Kim Add emulation of nanoMIPS 16-bit shift instructions. Reviewed-by: Richard Henderson Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/translate.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 9c6c3e1b..edbb439 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16542,6 +16542,21 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) case NM_P16_MV: break; case NM_P16_SHIFT: + { + int shift = extract32(ctx->opcode, 0, 3); + uint32_t opc = 0; + shift = (shift == 0) ? 8 : shift; + + switch (extract32(ctx->opcode, 3, 1)) { + case NM_SLL16: + opc = OPC_SLL; + break; + case NM_SRL16: + opc = OPC_SRL; + break; + } + gen_shift_imm(ctx, opc, rt, rs, shift); + } break; case NM_P16C: break; -- 1.9.1